Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Kevin Hilman:
 "About 10 days worth of small bug fixes, and the (hopefully) final
  round fixes for from arm-soc land for the -rc cycle.  Nothing special
  to note, but here's a brief summary of fixes by SoC type:

   - OMAP:
        small set of misc DT fixes; boot fix for THUMB2 kernel

   - mediatek:
        PMIC fixes; DT fix for model name

   - exynos:
        wakeup interupt fixes for 3250

   - mvebu:
        revert mbus patch which broke DMA masters

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: dts: am335x-boneblack: disable RTC-only sleep to avoid hardware damage
  ARM: dts: AM35xx: fix system control module clocks
  arm64: dts: mt8173-evb: fix model name
  ARM: exynos: Fix wake-up interrupts for Exynos3250
  ARM: dts: Fix n900 dts file to work around 4.1 touchscreen regression on n900
  ARM: dts: Fix dm816x to use right compatible flag for MUSB
  ARM: OMAP3: Fix booting with thumb2 kernel
  Revert "bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge window"
  bus: mvebu-mbus: do not set WIN_CTRL_SYNCBARRIER on non io-coherent platforms.
  ARM: mvebu: armada-xp-linksys-mamba: Disable internal RTC
  soc: mediatek: Add compile dependency to pmic-wrapper
  soc: mediatek: PMIC wrap: Fix register state machine handling
  soc: mediatek: PMIC wrap: Fix clock rate handling

12 files changed, 72 insertions, 171 deletions

diff --git a/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt b/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt
index 4b641c7bf1c2..09089a6d69ed 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/tsc2005.txt
@@ -32,8 +32,8 @@ Example:
                 touchscreen-fuzz-x = <4>;
                 touchscreen-fuzz-y = <7>;
                 touchscreen-fuzz-pressure = <2>;
-                touchscreen-max-x = <4096>;
-                touchscreen-max-y = <4096>;
+                touchscreen-size-x = <4096>;
+                touchscreen-size-y = <4096>;
                 touchscreen-max-pressure = <2048>;
 
                 ti,x-plate-ohms = <280>;
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index c3255e0c90aa..dbb3f4d2bf84 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -223,6 +223,25 @@
 /include/ "tps65217.dtsi"
 
 &tps {
+        /*
+         * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
+         * mode") at poweroff.  Most BeagleBone versions do not support RTC-only
+         * mode and risk hardware damage if this mode is entered.
+         *
+         * For details, see linux-omap mailing list May 2015 thread
+         *      [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
+         * In particular, messages:
+         *      http://www.spinics.net/lists/linux-omap/msg118585.html
+         *      http://www.spinics.net/lists/linux-omap/msg118615.html
+         *
+         * You can override this later with
+         *      &tps {  /delete-property/ ti,pmic-shutdown-controller;  }
+         * if you want to use RTC-only mode and made sure you are not affected
+         * by the hardware problems. (Tip: double-check by performing a current
+         * measurement after shutdown: it should be less than 1 mA.)
+         */
+        ti,pmic-shutdown-controller;
+
         regulators {
                 dcdc1_reg: regulator@0 {
                         regulator-name = "vdds_dpr";
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
index 518b8fde88b0..18cc826e9db5 100644
--- a/arch/arm/boot/dts/am35xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -12,7 +12,7 @@
                 #clock-cells = <0>;
                 compatible = "ti,am35xx-gate-clock";
                 clocks = <&ipss_ick>;
-                reg = <0x059c>;
+                reg = <0x032c>;
                 ti,bit-shift = <1>;
         };
 
@@ -20,7 +20,7 @@
                 #clock-cells = <0>;
                 compatible = "ti,gate-clock";
                 clocks = <&rmii_ck>;
-                reg = <0x059c>;
+                reg = <0x032c>;
                 ti,bit-shift = <9>;
         };
 
@@ -28,7 +28,7 @@
                 #clock-cells = <0>;
                 compatible = "ti,am35xx-gate-clock";
                 clocks = <&ipss_ick>;
-                reg = <0x059c>;
+                reg = <0x032c>;
                 ti,bit-shift = <2>;
         };
 
@@ -36,7 +36,7 @@
                 #clock-cells = <0>;
                 compatible = "ti,gate-clock";
                 clocks = <&pclk_ck>;
-                reg = <0x059c>;
+                reg = <0x032c>;
                 ti,bit-shift = <10>;
         };
 
@@ -44,7 +44,7 @@
                 #clock-cells = <0>;
                 compatible = "ti,am35xx-gate-clock";
                 clocks = <&ipss_ick>;
-                reg = <0x059c>;
+                reg = <0x032c>;
                 ti,bit-shift = <0>;
         };
 
@@ -52,7 +52,7 @@
                 #clock-cells = <0>;
                 compatible = "ti,gate-clock";
                 clocks = <&sys_ck>;
-                reg = <0x059c>;
+                reg = <0x032c>;
                 ti,bit-shift = <8>;
         };
 
@@ -60,7 +60,7 @@
                 #clock-cells = <0>;
                 compatible = "ti,am35xx-gate-clock";
                 clocks = <&sys_ck>;
-                reg = <0x059c>;
+                reg = <0x032c>;
                 ti,bit-shift = <3>;
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index a2cf2154dcdb..fdd187c55aa5 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -95,6 +95,11 @@
 
                 internal-regs {
 
+                        rtc@10300 {
+                                /* No crystal connected to the internal RTC */
+                                status = "disabled";
+                        };
+
                         /* J10: VCC, NC, RX, NC, TX, GND  */
                         serial@12000 {
                                 status = "okay";
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index de8427be830a..289806adb343 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -382,7 +382,7 @@
                         ti,hwmods = "usb_otg_hs";
 
                         usb0: usb@47401000 {
-                                compatible = "ti,musb-am33xx";
+                                compatible = "ti,musb-dm816";
                                 reg = <0x47401400 0x400
                                        0x47401000 0x200>;
                                 reg-names = "mc", "control";
@@ -422,7 +422,7 @@
                         };
 
                         usb1: usb@47401800 {
-                                compatible = "ti,musb-am33xx";
+                                compatible = "ti,musb-dm816";
                                 reg = <0x47401c00 0x400
                                        0x47401800 0x200>;
                                 reg-names = "mc", "control";
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 5c16145920ea..5f5e0f3d5b64 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -832,8 +832,8 @@
                 touchscreen-fuzz-x = <4>;
                 touchscreen-fuzz-y = <7>;
                 touchscreen-fuzz-pressure = <2>;
-                touchscreen-max-x = <4096>;
-                touchscreen-max-y = <4096>;
+                touchscreen-size-x = <4096>;
+                touchscreen-size-y = <4096>;
                 touchscreen-max-pressure = <2048>;
 
                 ti,x-plate-ohms = <280>;
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index c0b6dccbf7bd..7d23ce04cad5 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -87,8 +87,8 @@ static unsigned int exynos_pmu_spare3;
 static u32 exynos_irqwake_intmask = 0xffffffff;
 
 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
-        { 105, BIT(1) }, /* RTC alarm */
-        { 106, BIT(2) }, /* RTC tick */
+        { 73, BIT(1) }, /* RTC alarm */
+        { 74, BIT(2) }, /* RTC tick */
         { /* sentinel */ },
 };
 
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index d1dedc8195ed..eafd120b53f1 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -203,23 +203,8 @@ save_context_wfi:
          */
         ldr     r1, kernel_flush
         blx     r1
-        /*
-         * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
-         * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
-         * This sequence switches back to ARM.  Note that .align may insert a
-         * nop: bx pc needs to be word-aligned in order to work.
-         */
- THUMB( .thumb          )
- THUMB( .align          )
- THUMB( bx      pc      )
- THUMB( nop             )
-        .arm
-
         b       omap3_do_wfi
-
-/*
- * Local variables
- */
+ENDPROC(omap34xx_cpu_suspend)
 omap3_do_wfi_sram_addr:
         .word omap3_do_wfi_sram
 kernel_flush:
@@ -364,10 +349,7 @@ exit_nonoff_modes:
  * ===================================
  */
         ldmfd   sp!, {r4 - r11, pc}     @ restore regs and return
-
-/*
- * Local variables
- */
+ENDPROC(omap3_do_wfi)
 sdrc_power:
         .word   SDRC_POWER_V
 cm_idlest1_core:
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 43d54017b779..d0ab012fa379 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -16,7 +16,8 @@
 #include "mt8173.dtsi"
 
 / {
-        model = "mediatek,mt8173-evb";
+        model = "MediaTek MT8173 evaluation board";
+        compatible = "mediatek,mt8173-evb", "mediatek,mt8173";
 
         aliases {
                 serial0 = &uart0;
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index fb9ec6221730..6f047dcb94c2 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -58,7 +58,6 @@
 #include <linux/debugfs.h>
 #include <linux/log2.h>
 #include <linux/syscore_ops.h>
-#include <linux/memblock.h>
 
 /*
  * DDR target is the same on all platforms.
@@ -70,6 +69,7 @@
  */
 #define WIN_CTRL_OFF            0x0000
 #define   WIN_CTRL_ENABLE       BIT(0)
+/* Only on HW I/O coherency capable platforms */
 #define   WIN_CTRL_SYNCBARRIER  BIT(1)
 #define   WIN_CTRL_TGT_MASK     0xf0
 #define   WIN_CTRL_TGT_SHIFT    4
@@ -102,9 +102,7 @@
 
 /* Relative to mbusbridge_base */
 #define MBUS_BRIDGE_CTRL_OFF    0x0
-#define  MBUS_BRIDGE_SIZE_MASK  0xffff0000
 #define MBUS_BRIDGE_BASE_OFF    0x4
-#define  MBUS_BRIDGE_BASE_MASK  0xffff0000
 
 /* Maximum number of windows, for all known platforms */
 #define MBUS_WINS_MAX           20
@@ -323,8 +321,9 @@ static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
         ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
                 (attr << WIN_CTRL_ATTR_SHIFT)    |
                 (target << WIN_CTRL_TGT_SHIFT)   |
-                WIN_CTRL_SYNCBARRIER             |
                 WIN_CTRL_ENABLE;
+        if (mbus->hw_io_coherency)
+                ctrl |= WIN_CTRL_SYNCBARRIER;
 
         writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
         writel(ctrl, addr + WIN_CTRL_OFF);
@@ -577,106 +576,36 @@ static unsigned int armada_xp_mbus_win_remap_offset(int win)
                 return MVEBU_MBUS_NO_REMAP;
 }
 
-/*
- * Use the memblock information to find the MBus bridge hole in the
- * physical address space.
- */
-static void __init
-mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
-{
-        struct memblock_region *r;
-        uint64_t s = 0;
-
-        for_each_memblock(memory, r) {
-                /*
-                 * This part of the memory is above 4 GB, so we don't
-                 * care for the MBus bridge hole.
-                 */
-                if (r->base >= 0x100000000)
-                        continue;
-
-                /*
-                 * The MBus bridge hole is at the end of the RAM under
-                 * the 4 GB limit.
-                 */
-                if (r->base + r->size > s)
-                        s = r->base + r->size;
-        }
-
-        *start = s;
-        *end = 0x100000000;
-}
-
 static void __init
 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
 {
         int i;
         int cs;
-        uint64_t mbus_bridge_base, mbus_bridge_end;
 
         mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 
-        mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
-
         for (i = 0, cs = 0; i < 4; i++) {
-                u64 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
-                u64 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
-                u64 end;
-                struct mbus_dram_window *w;
-
-                /* Ignore entries that are not enabled */
-                if (!(size & DDR_SIZE_ENABLED))
-                        continue;
-
-                /*
-                 * Ignore entries whose base address is above 2^32,
-                 * since devices cannot DMA to such high addresses
-                 */
-                if (base & DDR_BASE_CS_HIGH_MASK)
-                        continue;
-
-                base = base & DDR_BASE_CS_LOW_MASK;
-                size = (size | ~DDR_SIZE_MASK) + 1;
-                end = base + size;
-
-                /*
-                 * Adjust base/size of the current CS to make sure it
-                 * doesn't overlap with the MBus bridge hole. This is
-                 * particularly important for devices that do DMA from
-                 * DRAM to a SRAM mapped in a MBus window, such as the
-                 * CESA cryptographic engine.
-                 */
+                u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
+                u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
 
                 /*
-                 * The CS is fully enclosed inside the MBus bridge
-                 * area, so ignore it.
+                 * We only take care of entries for which the chip
+                 * select is enabled, and that don't have high base
+                 * address bits set (devices can only access the first
+                 * 32 bits of the memory).
                  */
-                if (base >= mbus_bridge_base && end <= mbus_bridge_end)
-                        continue;
+                if ((size & DDR_SIZE_ENABLED) &&
+                    !(base & DDR_BASE_CS_HIGH_MASK)) {
+                        struct mbus_dram_window *w;
 
-                /*
-                 * Beginning of CS overlaps with end of MBus, raise CS
-                 * base address, and shrink its size.
-                 */
-                if (base >= mbus_bridge_base && end > mbus_bridge_end) {
-                        size -= mbus_bridge_end - base;
-                        base = mbus_bridge_end;
+                        w = &mvebu_mbus_dram_info.cs[cs++];
+                        w->cs_index = i;
+                        w->mbus_attr = 0xf & ~(1 << i);
+                        if (mbus->hw_io_coherency)
+                                w->mbus_attr |= ATTR_HW_COHERENCY;
+                        w->base = base & DDR_BASE_CS_LOW_MASK;
+                        w->size = (size | ~DDR_SIZE_MASK) + 1;
                 }
-
-                /*
-                 * End of CS overlaps with beginning of MBus, shrink
-                 * CS size.
-                 */
-                if (base < mbus_bridge_base && end > mbus_bridge_base)
-                        size -= end - mbus_bridge_base;
-
-                w = &mvebu_mbus_dram_info.cs[cs++];
-                w->cs_index = i;
-                w->mbus_attr = 0xf & ~(1 << i);
-                if (mbus->hw_io_coherency)
-                        w->mbus_attr |= ATTR_HW_COHERENCY;
-                w->base = base;
-                w->size = size;
         }
         mvebu_mbus_dram_info.num_cs = cs;
 }
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index bcdb22d5e215..3c1850332a90 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -4,6 +4,7 @@
 config MTK_PMIC_WRAP
         tristate "MediaTek PMIC Wrapper Support"
         depends on ARCH_MEDIATEK
+        depends on RESET_CONTROLLER
         select REGMAP
         help
           Say yes here to add support for MediaTek PMIC Wrapper found
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index db5be1eec54c..f432291feee9 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -443,11 +443,6 @@ static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
 {
         int ret;
-        u32 val;
-
-        val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
-        if (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR)
-                pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
 
         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
         if (ret)
@@ -462,11 +457,6 @@ static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
 {
         int ret;
-        u32 val;
-
-        val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
-        if (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR)
-                pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
 
         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
         if (ret)
@@ -480,6 +470,8 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
 
         *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
 
+        pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
+
         return 0;
 }
 
@@ -563,45 +555,17 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
 
 static int pwrap_init_reg_clock(struct pmic_wrapper *wrp)
 {
-        unsigned long rate_spi;
-        int ck_mhz;
-
-        rate_spi = clk_get_rate(wrp->clk_spi);
-
-        if (rate_spi > 26000000)
-                ck_mhz = 26;
-        else if (rate_spi > 18000000)
-                ck_mhz = 18;
-        else
-                ck_mhz = 0;
-
-        switch (ck_mhz) {
-        case 18:
-                if (pwrap_is_mt8135(wrp))
-                        pwrap_writel(wrp, 0xc, PWRAP_CSHEXT);
-                pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE);
-                pwrap_writel(wrp, 0xc, PWRAP_CSHEXT_READ);
-                pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
-                pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
-                break;
-        case 26:
-                if (pwrap_is_mt8135(wrp))
-                        pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
+        if (pwrap_is_mt8135(wrp)) {
+                pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
                 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
                 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
                 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
                 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
-                break;
-        case 0:
-                if (pwrap_is_mt8135(wrp))
-                        pwrap_writel(wrp, 0xf, PWRAP_CSHEXT);
-                pwrap_writel(wrp, 0xf, PWRAP_CSHEXT_WRITE);
-                pwrap_writel(wrp, 0xf, PWRAP_CSHEXT_READ);
-                pwrap_writel(wrp, 0xf, PWRAP_CSLEXT_START);
-                pwrap_writel(wrp, 0xf, PWRAP_CSLEXT_END);
-                break;
-        default:
-                return -EINVAL;
+        } else {
+                pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
+                pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
+                pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
+                pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
         }
 
         return 0;