drm/nve0: magic up some support for GF117

Seen in the wild, don't have the hardware but this hacks things up to
treat it the same as GF119 for now.

Should be relatively safe, I'd be very surprised if anything major
changed outside of PGRAPH.  PGRAPH (3D etc) is disabled by default
however until it's confirmed working.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

6 files changed, 63 insertions, 25 deletions

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index 0b7951a85943..ebc9caa951f6 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -1399,7 +1399,7 @@ nvc0_grctx_generate_90c0(struct nvc0_graph_priv *priv)
 {
         int i;
 
-        for (i = 0; nv_device(priv)->chipset == 0xd9 && i < 4; i++) {
+        for (i = 0; nv_device(priv)->chipset >= 0xd0 && i < 4; i++) {
                 nv_mthd(priv, 0x90c0, 0x2700 + (i * 0x40), 0x00000000);
                 nv_mthd(priv, 0x90c0, 0x2720 + (i * 0x40), 0x00000000);
                 nv_mthd(priv, 0x90c0, 0x2704 + (i * 0x40), 0x00000000);
@@ -1415,7 +1415,7 @@ nvc0_grctx_generate_90c0(struct nvc0_graph_priv *priv)
         nv_mthd(priv, 0x90c0, 0x27ac, 0x00000000);
         nv_mthd(priv, 0x90c0, 0x27cc, 0x00000000);
         nv_mthd(priv, 0x90c0, 0x27ec, 0x00000000);
-        for (i = 0; nv_device(priv)->chipset == 0xd9 && i < 4; i++) {
+        for (i = 0; nv_device(priv)->chipset >= 0xd0 && i < 4; i++) {
                 nv_mthd(priv, 0x90c0, 0x2710 + (i * 0x40), 0x00014000);
                 nv_mthd(priv, 0x90c0, 0x2730 + (i * 0x40), 0x00014000);
                 nv_mthd(priv, 0x90c0, 0x2714 + (i * 0x40), 0x00000040);
@@ -1615,7 +1615,7 @@ static void
 nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv)
 {
 
-        if (nv_device(priv)->chipset == 0xd9) {
+        if (nv_device(priv)->chipset >= 0xd0) {
                 nv_wr32(priv, 0x405800, 0x0f8000bf);
                 nv_wr32(priv, 0x405830, 0x02180218);
                 nv_wr32(priv, 0x405834, 0x08000000);
@@ -1658,10 +1658,10 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
         nv_wr32(priv, 0x4064ac, 0x00003fff);
         nv_wr32(priv, 0x4064b4, 0x00000000);
         nv_wr32(priv, 0x4064b8, 0x00000000);
-        if (nv_device(priv)->chipset == 0xd9)
+        if (nv_device(priv)->chipset >= 0xd0)
                 nv_wr32(priv, 0x4064bc, 0x00000000);
         if (nv_device(priv)->chipset == 0xc1 ||
-            nv_device(priv)->chipset == 0xd9) {
+            nv_device(priv)->chipset >= 0xd0) {
                 nv_wr32(priv, 0x4064c0, 0x80140078);
                 nv_wr32(priv, 0x4064c4, 0x0086ffff);
         }
@@ -1701,7 +1701,7 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
         /* ROPC_BROADCAST */
         nv_wr32(priv, 0x408800, 0x02802a3c);
         nv_wr32(priv, 0x408804, 0x00000040);
-        if (chipset == 0xd9) {
+        if (chipset >= 0xd0) {
                 nv_wr32(priv, 0x408808, 0x1043e005);
                 nv_wr32(priv, 0x408900, 0x3080b801);
                 nv_wr32(priv, 0x408904, 0x1043e005);
@@ -1735,7 +1735,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
         nv_wr32(priv, 0x418408, 0x00000000);
         nv_wr32(priv, 0x41840c, 0x00001008);
         nv_wr32(priv, 0x418410, 0x0fff0fff);
-        nv_wr32(priv, 0x418414, chipset != 0xd9 ? 0x00200fff : 0x02200fff);
+        nv_wr32(priv, 0x418414, chipset < 0xd0 ? 0x00200fff : 0x02200fff);
         nv_wr32(priv, 0x418450, 0x00000000);
         nv_wr32(priv, 0x418454, 0x00000000);
         nv_wr32(priv, 0x418458, 0x00000000);
@@ -1750,14 +1750,14 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
         nv_wr32(priv, 0x418700, 0x00000002);
         nv_wr32(priv, 0x418704, 0x00000080);
         nv_wr32(priv, 0x418708, 0x00000000);
-        nv_wr32(priv, 0x41870c, chipset != 0xd9 ? 0x07c80000 : 0x00000000);
+        nv_wr32(priv, 0x41870c, chipset < 0xd0 ? 0x07c80000 : 0x00000000);
         nv_wr32(priv, 0x418710, 0x00000000);
-        nv_wr32(priv, 0x418800, chipset != 0xd9 ? 0x0006860a : 0x7006860a);
+        nv_wr32(priv, 0x418800, chipset < 0xd0 ? 0x0006860a : 0x7006860a);
         nv_wr32(priv, 0x418808, 0x00000000);
         nv_wr32(priv, 0x41880c, 0x00000000);
         nv_wr32(priv, 0x418810, 0x00000000);
         nv_wr32(priv, 0x418828, 0x00008442);
-        if (chipset == 0xc1 || chipset == 0xd9)
+        if (chipset == 0xc1 || chipset >= 0xd0)
                 nv_wr32(priv, 0x418830, 0x10000001);
         else
                 nv_wr32(priv, 0x418830, 0x00000001);
@@ -1768,7 +1768,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
         nv_wr32(priv, 0x4188f0, 0x00000000);
         nv_wr32(priv, 0x4188f4, 0x00000000);
         nv_wr32(priv, 0x4188f8, 0x00000000);
-        if (chipset == 0xd9)
+        if (chipset >= 0xd0)
                 nv_wr32(priv, 0x4188fc, 0x20100008);
         else if (chipset == 0xc1)
                 nv_wr32(priv, 0x4188fc, 0x00100018);
@@ -1787,7 +1787,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
                 nv_wr32(priv, 0x418a14 + (i * 0x20), 0x00000000);
                 nv_wr32(priv, 0x418a18 + (i * 0x20), 0x00000000);
         }
-        nv_wr32(priv, 0x418b00, chipset != 0xd9 ? 0x00000000 : 0x00000006);
+        nv_wr32(priv, 0x418b00, chipset < 0xd0 ? 0x00000000 : 0x00000006);
         nv_wr32(priv, 0x418b08, 0x0a418820);
         nv_wr32(priv, 0x418b0c, 0x062080e6);
         nv_wr32(priv, 0x418b10, 0x020398a4);
@@ -1804,7 +1804,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
         nv_wr32(priv, 0x418c24, 0x00000000);
         nv_wr32(priv, 0x418c28, 0x00000000);
         nv_wr32(priv, 0x418c2c, 0x00000000);
-        if (chipset == 0xc1 || chipset == 0xd9)
+        if (chipset == 0xc1 || chipset >= 0xd0)
                 nv_wr32(priv, 0x418c6c, 0x00000001);
         nv_wr32(priv, 0x418c80, 0x20200004);
         nv_wr32(priv, 0x418c8c, 0x00000001);
@@ -1823,7 +1823,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
         nv_wr32(priv, 0x419818, 0x00000000);
         nv_wr32(priv, 0x41983c, 0x00038bc7);
         nv_wr32(priv, 0x419848, 0x00000000);
-        if (chipset == 0xc1 || chipset == 0xd9)
+        if (chipset == 0xc1 || chipset >= 0xd0)
                 nv_wr32(priv, 0x419864, 0x00000129);
         else
                 nv_wr32(priv, 0x419864, 0x0000012a);
@@ -1836,7 +1836,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
         nv_wr32(priv, 0x419a14, 0x00000200);
         nv_wr32(priv, 0x419a1c, 0x00000000);
         nv_wr32(priv, 0x419a20, 0x00000800);
-        if (chipset == 0xd9)
+        if (chipset >= 0xd0)
                 nv_wr32(priv, 0x00419ac4, 0x0017f440);
         else if (chipset != 0xc0 && chipset != 0xc8)
                 nv_wr32(priv, 0x00419ac4, 0x0007f440);
@@ -1847,16 +1847,16 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
         nv_wr32(priv, 0x419b10, 0x0a418820);
         nv_wr32(priv, 0x419b14, 0x000000e6);
         nv_wr32(priv, 0x419bd0, 0x00900103);
-        if (chipset == 0xc1 || chipset == 0xd9)
+        if (chipset == 0xc1 || chipset >= 0xd0)
                 nv_wr32(priv, 0x419be0, 0x00400001);
         else
                 nv_wr32(priv, 0x419be0, 0x00000001);
         nv_wr32(priv, 0x419be4, 0x00000000);
-        nv_wr32(priv, 0x419c00, chipset != 0xd9 ? 0x00000002 : 0x0000000a);
+        nv_wr32(priv, 0x419c00, chipset < 0xd0 ? 0x00000002 : 0x0000000a);
         nv_wr32(priv, 0x419c04, 0x00000006);
         nv_wr32(priv, 0x419c08, 0x00000002);
         nv_wr32(priv, 0x419c20, 0x00000000);
-        if (nv_device(priv)->chipset == 0xd9) {
+        if (nv_device(priv)->chipset >= 0xd0) {
                 nv_wr32(priv, 0x419c24, 0x00084210);
                 nv_wr32(priv, 0x419c28, 0x3cf3cf3c);
                 nv_wr32(priv, 0x419cb0, 0x00020048);
@@ -1868,12 +1868,12 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
         }
         nv_wr32(priv, 0x419ce8, 0x00000000);
         nv_wr32(priv, 0x419cf4, 0x00000183);
-        if (chipset == 0xc1 || chipset == 0xd9)
+        if (chipset == 0xc1 || chipset >= 0xd0)
                 nv_wr32(priv, 0x419d20, 0x12180000);
         else
                 nv_wr32(priv, 0x419d20, 0x02180000);
         nv_wr32(priv, 0x419d24, 0x00001fff);
-        if (chipset == 0xc1 || chipset == 0xd9)
+        if (chipset == 0xc1 || chipset >= 0xd0)
                 nv_wr32(priv, 0x419d44, 0x02180218);
         nv_wr32(priv, 0x419e04, 0x00000000);
         nv_wr32(priv, 0x419e08, 0x00000000);
@@ -2210,7 +2210,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
         nv_icmd(priv, 0x00000215, 0x00000040);
         nv_icmd(priv, 0x00000216, 0x00000040);
         nv_icmd(priv, 0x00000217, 0x00000040);
-        if (nv_device(priv)->chipset == 0xd9) {
+        if (nv_device(priv)->chipset >= 0xd0) {
                 for (i = 0x0400; i <= 0x0417; i++)
                         nv_icmd(priv, i, 0x00000040);
         }
@@ -2222,7 +2222,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
         nv_icmd(priv, 0x0000021d, 0x0000c080);
         nv_icmd(priv, 0x0000021e, 0x0000c080);
         nv_icmd(priv, 0x0000021f, 0x0000c080);
-        if (nv_device(priv)->chipset == 0xd9) {
+        if (nv_device(priv)->chipset >= 0xd0) {
                 for (i = 0x0440; i <= 0x0457; i++)
                         nv_icmd(priv, i, 0x0000c080);
         }
@@ -2789,7 +2789,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
         nv_icmd(priv, 0x00000585, 0x0000003f);
         nv_icmd(priv, 0x00000576, 0x00000003);
         if (nv_device(priv)->chipset == 0xc1 ||
-            nv_device(priv)->chipset == 0xd9)
+            nv_device(priv)->chipset >= 0xd0)
                 nv_icmd(priv, 0x0000057b, 0x00000059);
         nv_icmd(priv, 0x00000586, 0x00000040);
         nv_icmd(priv, 0x00000582, 0x00000080);
@@ -2891,7 +2891,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
         nv_icmd(priv, 0x00000957, 0x00000003);
         nv_icmd(priv, 0x0000095e, 0x20164010);
         nv_icmd(priv, 0x0000095f, 0x00000020);
-        if (nv_device(priv)->chipset == 0xd9)
+        if (nv_device(priv)->chipset >= 0xd0)
                 nv_icmd(priv, 0x0000097d, 0x00000020);
         nv_icmd(priv, 0x00000683, 0x00000006);
         nv_icmd(priv, 0x00000685, 0x003fffff);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
index b86cc60dcd56..f7055af0f2a6 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
@@ -87,6 +87,11 @@ chipsets:
 .b16 #nvd9_gpc_mmio_tail
 .b16 #nvd9_tpc_mmio_head
 .b16 #nvd9_tpc_mmio_tail
+.b8  0xd7 0 0 0
+.b16 #nvd9_gpc_mmio_head
+.b16 #nvd9_gpc_mmio_tail
+.b16 #nvd9_tpc_mmio_head
+.b16 #nvd9_tpc_mmio_tail
 .b8  0 0 0 0
 
 // GPC mmio lists
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
index 0bcfa4d447e5..7fbdebb2bafb 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
@@ -62,6 +62,9 @@ chipsets:
 .b8  0xd9 0 0 0
 .b16 #nvd9_hub_mmio_head
 .b16 #nvd9_hub_mmio_tail
+.b8  0xd7 0 0 0
+.b16 #nvd9_hub_mmio_head
+.b16 #nvd9_hub_mmio_tail
 .b8  0 0 0 0
 
 nvc0_hub_mmio_head:
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index 5ce49412e482..2dcd13796188 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -531,9 +531,10 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 {
         struct nouveau_device *device = nv_device(parent);
         struct nvc0_graph_priv *priv;
+        bool enable = device->chipset != 0xd7;
         int ret, i;
 
-        ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
+        ret = nouveau_graph_create(parent, engine, oclass, enable, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
index af033dc24440..c870dad0f670 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
@@ -118,6 +118,7 @@ nvc0_graph_class(void *obj)
                 return 0x9197;
         case 0xc8:
         case 0xd9:
+        case 0xd7:
                 return 0x9297;
         case 0xe4:
         case 0xe7:
diff --git a/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c
index 4393eb4d6564..00f869ee53e3 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/device/nvc0.c
@@ -285,6 +285,34 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] = &nvd0_disp_oclass;
                 break;
+        case 0xd7:
+                device->cname = "GF117";
+                device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
+                device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
+                device->oclass[NVDEV_SUBDEV_I2C    ] = &nvd0_i2c_oclass;
+                device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
+                device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
+                device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
+                device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
+                device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
+                device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
+                device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
+                device->oclass[NVDEV_SUBDEV_IBUS   ] = &nvc0_ibus_oclass;
+                device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
+                device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
+                device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
+                device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
+                device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
+                device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
+                device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
+                device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+                device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
+                device->oclass[NVDEV_ENGINE_DISP   ] = &nvd0_disp_oclass;
+                break;
         default:
                 nv_fatal(device, "unknown Fermi chipset\n");
                 return -EINVAL;