Merge tag 'sunxi-core-for-3.14-2' of https://github.com/mripard/linux into next/soc

From Maxime Ripard:
Second round of core additions for the Allwinner SoCs

Fixes to select missing configuration options, and update of the maintainer
file.

* tag 'sunxi-core-for-3.14-2' of https://github.com/mripard/linux:
  ARM: sunxi: select ARM_PSCI
  MAINTAINERS: Update Allwinner sunXi maintainer files
  ARM: sunxi: Select RESET_CONTROLLER
  ARM: sun6i: Add SMP support for the Allwinner A31
  dt-bindings: fix example of allwinner interrupt controller
  ARM: sunxi: Register the A31 reset IP in init_time
  ARM: sunxi: Select ARCH_HAS_RESET_CONTROLLER
  reset: Add Allwinner SoCs Reset Controller Driver

Signed-off-by: Kevin Hilman <khilman@linaro.org>

10 files changed, 353 insertions, 2 deletions

diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
index 3d3b2b91e333..32cec4b26cd0 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
@@ -14,5 +14,5 @@ intc: interrupt-controller {
         compatible = "allwinner,sun4i-ic";
         reg = <0x01c20400 0x400>;
         interrupt-controller;
-        #interrupt-cells = <2>;
+        #interrupt-cells = <1>;
 };
diff --git a/MAINTAINERS b/MAINTAINERS
index 6ea1fb247a8c..b6d1afbf9920 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -766,7 +766,12 @@ ARM/Allwinner A1X SoC support
 M:      Maxime Ripard <maxime.ripard@free-electrons.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
-F:      arch/arm/mach-sunxi/
+N:      sun[x4567]i
+
+ARM/Allwinner SoC Clock Support
+M:      Emilio López <emilio@elopez.com.ar>
+S:      Maintained
+F:      drivers/clk/sunxi/
 
 ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
 M:      Andrew Victor <linux@maxim.org.za>
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index c9e72c89066a..8053b1befc5e 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1,7 +1,9 @@
 config ARCH_SUNXI
         bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
+        select ARCH_HAS_RESET_CONTROLLER
         select ARCH_REQUIRE_GPIOLIB
         select ARM_GIC
+        select ARM_PSCI
         select CLKSRC_MMIO
         select CLKSRC_OF
         select COMMON_CLK
@@ -10,5 +12,6 @@ config ARCH_SUNXI
         select HAVE_SMP
         select PINCTRL
         select PINCTRL_SUNXI
+        select RESET_CONTROLLER
         select SPARSE_IRQ
         select SUN4I_TIMER
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 93bebfc3ff9f..d9397202d6ec 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-sunxi/common.h b/arch/arm/mach-sunxi/common.h
new file mode 100644
index 000000000000..9e5ac4756cbb
--- /dev/null
+++ b/arch/arm/mach-sunxi/common.h
@@ -0,0 +1,19 @@
+/*
+ * Core functions for Allwinner SoCs
+ *
+ * Copyright (C) 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_SUNXI_COMMON_H_
+#define __ARCH_SUNXI_COMMON_H_
+
+void sun6i_secondary_startup(void);
+extern struct smp_operations sun6i_smp_ops;
+
+#endif /* __ARCH_SUNXI_COMMON_H_ */
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index 000000000000..a10d494fb37b
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,9 @@
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        .section ".text.head", "ax"
+
+ENTRY(sun6i_secondary_startup)
+        msr     cpsr_fsxc, #0xd3
+        b       secondary_startup
+ENDPROC(sun6i_secondary_startup)
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
new file mode 100644
index 000000000000..7b141d8342a1
--- /dev/null
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -0,0 +1,124 @@
+/*
+ * SMP support for Allwinner SoCs
+ *
+ * Copyright (C) 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Based on code
+ *  Copyright (C) 2012-2013 Allwinner Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/memory.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/smp.h>
+
+#include "common.h"
+
+#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu)    ((cpu) * 0x40 + 0x64)
+#define CPUCFG_CPU_RST_CTRL_REG(cpu)            (((cpu) + 1) * 0x40)
+#define CPUCFG_CPU_CTRL_REG(cpu)                (((cpu) + 1) * 0x40 + 0x04)
+#define CPUCFG_CPU_STATUS_REG(cpu)              (((cpu) + 1) * 0x40 + 0x08)
+#define CPUCFG_GEN_CTRL_REG                     0x184
+#define CPUCFG_PRIVATE0_REG                     0x1a4
+#define CPUCFG_PRIVATE1_REG                     0x1a8
+#define CPUCFG_DBG_CTL0_REG                     0x1e0
+#define CPUCFG_DBG_CTL1_REG                     0x1e4
+
+#define PRCM_CPU_PWROFF_REG                     0x100
+#define PRCM_CPU_PWR_CLAMP_REG(cpu)             (((cpu) * 4) + 0x140)
+
+static void __iomem *cpucfg_membase;
+static void __iomem *prcm_membase;
+
+static DEFINE_SPINLOCK(cpu_lock);
+
+static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *node;
+
+        node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
+        if (!node) {
+                pr_err("Missing A31 PRCM node in the device tree\n");
+                return;
+        }
+
+        prcm_membase = of_iomap(node, 0);
+        if (!prcm_membase) {
+                pr_err("Couldn't map A31 PRCM registers\n");
+                return;
+        }
+
+        node = of_find_compatible_node(NULL, NULL,
+                                       "allwinner,sun6i-a31-cpuconfig");
+        if (!node) {
+                pr_err("Missing A31 CPU config node in the device tree\n");
+                return;
+        }
+
+        cpucfg_membase = of_iomap(node, 0);
+        if (!cpucfg_membase)
+                pr_err("Couldn't map A31 CPU config registers\n");
+
+}
+
+static int sun6i_smp_boot_secondary(unsigned int cpu,
+                                    struct task_struct *idle)
+{
+        u32 reg;
+        int i;
+
+        if (!(prcm_membase && cpucfg_membase))
+                return -EFAULT;
+
+        spin_lock(&cpu_lock);
+
+        /* Set CPU boot address */
+        writel(virt_to_phys(sun6i_secondary_startup),
+               cpucfg_membase + CPUCFG_PRIVATE0_REG);
+
+        /* Assert the CPU core in reset */
+        writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
+
+        /* Assert the L1 cache in reset */
+        reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
+        writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
+
+        /* Disable external debug access */
+        reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
+        writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
+
+        /* Power up the CPU */
+        for (i = 0; i <= 8; i++)
+                writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
+        mdelay(10);
+
+        /* Clear CPU power-off gating */
+        reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
+        writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
+        mdelay(1);
+
+        /* Deassert the CPU core reset */
+        writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
+
+        /* Enable back the external debug accesses */
+        reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
+        writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
+
+        spin_unlock(&cpu_lock);
+
+        return 0;
+}
+
+struct smp_operations sun6i_smp_ops __initdata = {
+        .smp_prepare_cpus       = sun6i_smp_prepare_cpus,
+        .smp_boot_secondary     = sun6i_smp_boot_secondary,
+};
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 61d3a387f01c..aeea6ceea725 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -10,6 +10,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -23,6 +25,8 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 
+#include "common.h"
+
 #define SUN4I_WATCHDOG_CTRL_REG         0x00
 #define SUN4I_WATCHDOG_CTRL_RESTART             BIT(0)
 #define SUN4I_WATCHDOG_MODE_REG         0x04
@@ -132,10 +136,20 @@ static const char * const sun6i_board_dt_compat[] = {
         NULL,
 };
 
+extern void __init sun6i_reset_init(void);
+static void __init sun6i_timer_init(void)
+{
+        of_clk_init(NULL);
+        sun6i_reset_init();
+        clocksource_of_init();
+}
+
 DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
         .init_machine   = sunxi_dt_init,
+        .init_time      = sun6i_timer_init,
         .dt_compat      = sun6i_board_dt_compat,
         .restart        = sun6i_restart,
+        .smp            = smp_ops(sun6i_smp_ops),
 MACHINE_END
 
 static const char * const sun7i_board_dt_compat[] = {
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1e2d83f2b995..cc29832c9638 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_RESET_CONTROLLER) += core.o
+obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
new file mode 100644
index 000000000000..695bd3496eba
--- /dev/null
+++ b/drivers/reset/reset-sunxi.c
@@ -0,0 +1,175 @@
+/*
+ * Allwinner SoCs Reset Controller driver
+ *
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+struct sunxi_reset_data {
+        spinlock_t                      lock;
+        void __iomem                    *membase;
+        struct reset_controller_dev     rcdev;
+};
+
+static int sunxi_reset_assert(struct reset_controller_dev *rcdev,
+                              unsigned long id)
+{
+        struct sunxi_reset_data *data = container_of(rcdev,
+                                                     struct sunxi_reset_data,
+                                                     rcdev);
+        int bank = id / BITS_PER_LONG;
+        int offset = id % BITS_PER_LONG;
+        unsigned long flags;
+        u32 reg;
+
+        spin_lock_irqsave(&data->lock, flags);
+
+        reg = readl(data->membase + (bank * 4));
+        writel(reg & ~BIT(offset), data->membase + (bank * 4));
+
+        spin_unlock_irqrestore(&data->lock, flags);
+
+        return 0;
+}
+
+static int sunxi_reset_deassert(struct reset_controller_dev *rcdev,
+                                unsigned long id)
+{
+        struct sunxi_reset_data *data = container_of(rcdev,
+                                                     struct sunxi_reset_data,
+                                                     rcdev);
+        int bank = id / BITS_PER_LONG;
+        int offset = id % BITS_PER_LONG;
+        unsigned long flags;
+        u32 reg;
+
+        spin_lock_irqsave(&data->lock, flags);
+
+        reg = readl(data->membase + (bank * 4));
+        writel(reg | BIT(offset), data->membase + (bank * 4));
+
+        spin_unlock_irqrestore(&data->lock, flags);
+
+        return 0;
+}
+
+static struct reset_control_ops sunxi_reset_ops = {
+        .assert         = sunxi_reset_assert,
+        .deassert       = sunxi_reset_deassert,
+};
+
+static int sunxi_reset_init(struct device_node *np)
+{
+        struct sunxi_reset_data *data;
+        struct resource res;
+        resource_size_t size;
+        int ret;
+
+        data = kzalloc(sizeof(*data), GFP_KERNEL);
+        if (!data)
+                return -ENOMEM;
+
+        ret = of_address_to_resource(np, 0, &res);
+        if (ret)
+                goto err_alloc;
+
+        size = resource_size(&res);
+        if (!request_mem_region(res.start, size, np->name)) {
+                ret = -EBUSY;
+                goto err_alloc;
+        }
+
+        data->membase = ioremap(res.start, size);
+        if (!data->membase) {
+                ret = -ENOMEM;
+                goto err_alloc;
+        }
+
+        data->rcdev.owner = THIS_MODULE;
+        data->rcdev.nr_resets = size * 32;
+        data->rcdev.ops = &sunxi_reset_ops;
+        data->rcdev.of_node = np;
+        reset_controller_register(&data->rcdev);
+
+        return 0;
+
+err_alloc:
+        kfree(data);
+        return ret;
+};
+
+/*
+ * These are the reset controller we need to initialize early on in
+ * our system, before we can even think of using a regular device
+ * driver for it.
+ */
+static const struct of_device_id sunxi_early_reset_dt_ids[] __initdata = {
+        { .compatible = "allwinner,sun6i-a31-ahb1-reset", },
+        { /* sentinel */ },
+};
+
+void __init sun6i_reset_init(void)
+{
+        struct device_node *np;
+
+        for_each_matching_node(np, sunxi_early_reset_dt_ids)
+                sunxi_reset_init(np);
+}
+
+/*
+ * And these are the controllers we can register through the regular
+ * device model.
+ */
+static const struct of_device_id sunxi_reset_dt_ids[] = {
+         { .compatible = "allwinner,sun6i-a31-clock-reset", },
+         { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, sunxi_reset_dt_ids);
+
+static int sunxi_reset_probe(struct platform_device *pdev)
+{
+        return sunxi_reset_init(pdev->dev.of_node);
+}
+
+static int sunxi_reset_remove(struct platform_device *pdev)
+{
+        struct sunxi_reset_data *data = platform_get_drvdata(pdev);
+
+        reset_controller_unregister(&data->rcdev);
+        iounmap(data->membase);
+        kfree(data);
+
+        return 0;
+}
+
+static struct platform_driver sunxi_reset_driver = {
+        .probe  = sunxi_reset_probe,
+        .remove = sunxi_reset_remove,
+        .driver = {
+                .name           = "sunxi-reset",
+                .owner          = THIS_MODULE,
+                .of_match_table = sunxi_reset_dt_ids,
+        },
+};
+module_platform_driver(sunxi_reset_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
+MODULE_DESCRIPTION("Allwinner SoCs Reset Controller Driver");
+MODULE_LICENSE("GPL");