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authorMike Frysinger <vapier@gentoo.org>2011-03-30 03:59:00 -0400
committerMike Frysinger <vapier@gentoo.org>2011-05-25 08:13:42 -0400
commit3dd666067d2b285724c828946e83100ea4c43d4b (patch)
treebb0e0c060013e12a7d6674f8139a5fec59cf6fbc
parent6adc521e7127732512ebd7fcfd3926d7970a82e1 (diff)
Blackfin: clean up style in irq defines
These files had a lot of whitespace damage, mostly due to copying and pasting original files that had damage. The BF561 header also had a lot of unused CONFIG_DEF_xxx defines, so punt them all. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat
-rw-r--r--arch/blackfin/mach-bf518/include/mach/irq.h218
-rw-r--r--arch/blackfin/mach-bf527/include/mach/irq.h222
-rw-r--r--arch/blackfin/mach-bf533/include/mach/irq.h109
-rw-r--r--arch/blackfin/mach-bf537/include/mach/irq.h303
-rw-r--r--arch/blackfin/mach-bf538/include/mach/irq.h45
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h46
-rw-r--r--arch/blackfin/mach-bf561/include/mach/irq.h379
7 files changed, 627 insertions, 695 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
index daf1fa5bbb00..edf8efd457dc 100644
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -9,7 +9,7 @@
9 9
10#include <mach-common/irq.h> 10#include <mach-common/irq.h>
11 11
12#define NR_PERI_INTS (2 * 32) 12#define NR_PERI_INTS (2 * 32)
13 13
14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
@@ -25,23 +25,23 @@
25#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ 25#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
26#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ 26#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
27#define IRQ_RTC BFIN_IRQ(14) /* RTC */ 27#define IRQ_RTC BFIN_IRQ(14) /* RTC */
28#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */ 28#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
29#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ 29#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
30#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ 30#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
31#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */ 31#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
32#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */ 32#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
33#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */ 33#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
34#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ 34#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
35#define IRQ_TWI BFIN_IRQ(20) /* TWI */ 35#define IRQ_TWI BFIN_IRQ(20) /* TWI */
36#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */ 36#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
37#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ 37#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
38#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ 38#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
39#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ 39#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
40#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ 40#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
41#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ 41#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
42#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ 42#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
43#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */ 43#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
44#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ 44#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
45#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */ 45#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
46#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ 46#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
47#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */ 47#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
@@ -67,90 +67,90 @@
67#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */ 67#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
68#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */ 68#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
69 69
70#define SYS_IRQS BFIN_IRQ(63) /* 70 */ 70#define SYS_IRQS BFIN_IRQ(63) /* 70 */
71 71
72#define IRQ_PF0 71 72#define IRQ_PF0 71
73#define IRQ_PF1 72 73#define IRQ_PF1 72
74#define IRQ_PF2 73 74#define IRQ_PF2 73
75#define IRQ_PF3 74 75#define IRQ_PF3 74
76#define IRQ_PF4 75 76#define IRQ_PF4 75
77#define IRQ_PF5 76 77#define IRQ_PF5 76
78#define IRQ_PF6 77 78#define IRQ_PF6 77
79#define IRQ_PF7 78 79#define IRQ_PF7 78
80#define IRQ_PF8 79 80#define IRQ_PF8 79
81#define IRQ_PF9 80 81#define IRQ_PF9 80
82#define IRQ_PF10 81 82#define IRQ_PF10 81
83#define IRQ_PF11 82 83#define IRQ_PF11 82
84#define IRQ_PF12 83 84#define IRQ_PF12 83
85#define IRQ_PF13 84 85#define IRQ_PF13 84
86#define IRQ_PF14 85 86#define IRQ_PF14 85
87#define IRQ_PF15 86 87#define IRQ_PF15 86
88 88
89#define IRQ_PG0 87 89#define IRQ_PG0 87
90#define IRQ_PG1 88 90#define IRQ_PG1 88
91#define IRQ_PG2 89 91#define IRQ_PG2 89
92#define IRQ_PG3 90 92#define IRQ_PG3 90
93#define IRQ_PG4 91 93#define IRQ_PG4 91
94#define IRQ_PG5 92 94#define IRQ_PG5 92
95#define IRQ_PG6 93 95#define IRQ_PG6 93
96#define IRQ_PG7 94 96#define IRQ_PG7 94
97#define IRQ_PG8 95 97#define IRQ_PG8 95
98#define IRQ_PG9 96 98#define IRQ_PG9 96
99#define IRQ_PG10 97 99#define IRQ_PG10 97
100#define IRQ_PG11 98 100#define IRQ_PG11 98
101#define IRQ_PG12 99 101#define IRQ_PG12 99
102#define IRQ_PG13 100 102#define IRQ_PG13 100
103#define IRQ_PG14 101 103#define IRQ_PG14 101
104#define IRQ_PG15 102 104#define IRQ_PG15 102
105 105
106#define IRQ_PH0 103 106#define IRQ_PH0 103
107#define IRQ_PH1 104 107#define IRQ_PH1 104
108#define IRQ_PH2 105 108#define IRQ_PH2 105
109#define IRQ_PH3 106 109#define IRQ_PH3 106
110#define IRQ_PH4 107 110#define IRQ_PH4 107
111#define IRQ_PH5 108 111#define IRQ_PH5 108
112#define IRQ_PH6 109 112#define IRQ_PH6 109
113#define IRQ_PH7 110 113#define IRQ_PH7 110
114#define IRQ_PH8 111 114#define IRQ_PH8 111
115#define IRQ_PH9 112 115#define IRQ_PH9 112
116#define IRQ_PH10 113 116#define IRQ_PH10 113
117#define IRQ_PH11 114 117#define IRQ_PH11 114
118#define IRQ_PH12 115 118#define IRQ_PH12 115
119#define IRQ_PH13 116 119#define IRQ_PH13 116
120#define IRQ_PH14 117 120#define IRQ_PH14 117
121#define IRQ_PH15 118 121#define IRQ_PH15 118
122 122
123#define GPIO_IRQ_BASE IRQ_PF0 123#define GPIO_IRQ_BASE IRQ_PF0
124 124
125#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */ 125#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
126#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */ 126#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
127#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */ 127#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
128#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */ 128#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
129#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */ 129#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
130#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */ 130#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
131#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */ 131#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
132#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ 132#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
133 133
134#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 134#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
135 135
136/* IAR0 BIT FIELDS */ 136/* IAR0 BIT FIELDS */
137#define IRQ_PLL_WAKEUP_POS 0 137#define IRQ_PLL_WAKEUP_POS 0
138#define IRQ_DMA0_ERROR_POS 4 138#define IRQ_DMA0_ERROR_POS 4
139#define IRQ_DMAR0_BLK_POS 8 139#define IRQ_DMAR0_BLK_POS 8
140#define IRQ_DMAR1_BLK_POS 12 140#define IRQ_DMAR1_BLK_POS 12
141#define IRQ_DMAR0_OVR_POS 16 141#define IRQ_DMAR0_OVR_POS 16
142#define IRQ_DMAR1_OVR_POS 20 142#define IRQ_DMAR1_OVR_POS 20
143#define IRQ_PPI_ERROR_POS 24 143#define IRQ_PPI_ERROR_POS 24
144#define IRQ_MAC_ERROR_POS 28 144#define IRQ_MAC_ERROR_POS 28
145 145
146/* IAR1 BIT FIELDS */ 146/* IAR1 BIT FIELDS */
147#define IRQ_SPORT0_ERROR_POS 0 147#define IRQ_SPORT0_ERROR_POS 0
148#define IRQ_SPORT1_ERROR_POS 4 148#define IRQ_SPORT1_ERROR_POS 4
149#define IRQ_PTP_ERROR_POS 8 149#define IRQ_PTP_ERROR_POS 8
150#define IRQ_UART0_ERROR_POS 16 150#define IRQ_UART0_ERROR_POS 16
151#define IRQ_UART1_ERROR_POS 20 151#define IRQ_UART1_ERROR_POS 20
152#define IRQ_RTC_POS 24 152#define IRQ_RTC_POS 24
153#define IRQ_PPI_POS 28 153#define IRQ_PPI_POS 28
154 154
155/* IAR2 BIT FIELDS */ 155/* IAR2 BIT FIELDS */
156#define IRQ_SPORT0_RX_POS 0 156#define IRQ_SPORT0_RX_POS 0
@@ -159,19 +159,19 @@
159#define IRQ_SPORT1_RX_POS 8 159#define IRQ_SPORT1_RX_POS 8
160#define IRQ_SPI1_POS 8 160#define IRQ_SPI1_POS 8
161#define IRQ_SPORT1_TX_POS 12 161#define IRQ_SPORT1_TX_POS 12
162#define IRQ_TWI_POS 16 162#define IRQ_TWI_POS 16
163#define IRQ_SPI0_POS 20 163#define IRQ_SPI0_POS 20
164#define IRQ_UART0_RX_POS 24 164#define IRQ_UART0_RX_POS 24
165#define IRQ_UART0_TX_POS 28 165#define IRQ_UART0_TX_POS 28
166 166
167/* IAR3 BIT FIELDS */ 167/* IAR3 BIT FIELDS */
168#define IRQ_UART1_RX_POS 0 168#define IRQ_UART1_RX_POS 0
169#define IRQ_UART1_TX_POS 4 169#define IRQ_UART1_TX_POS 4
170#define IRQ_OPTSEC_POS 8 170#define IRQ_OPTSEC_POS 8
171#define IRQ_CNT_POS 12 171#define IRQ_CNT_POS 12
172#define IRQ_MAC_RX_POS 16 172#define IRQ_MAC_RX_POS 16
173#define IRQ_PORTH_INTA_POS 20 173#define IRQ_PORTH_INTA_POS 20
174#define IRQ_MAC_TX_POS 24 174#define IRQ_MAC_TX_POS 24
175#define IRQ_PORTH_INTB_POS 28 175#define IRQ_PORTH_INTB_POS 28
176 176
177/* IAR4 BIT FIELDS */ 177/* IAR4 BIT FIELDS */
@@ -187,19 +187,19 @@
187/* IAR5 BIT FIELDS */ 187/* IAR5 BIT FIELDS */
188#define IRQ_PORTG_INTA_POS 0 188#define IRQ_PORTG_INTA_POS 0
189#define IRQ_PORTG_INTB_POS 4 189#define IRQ_PORTG_INTB_POS 4
190#define IRQ_MEM_DMA0_POS 8 190#define IRQ_MEM_DMA0_POS 8
191#define IRQ_MEM_DMA1_POS 12 191#define IRQ_MEM_DMA1_POS 12
192#define IRQ_WATCH_POS 16 192#define IRQ_WATCH_POS 16
193#define IRQ_PORTF_INTA_POS 20 193#define IRQ_PORTF_INTA_POS 20
194#define IRQ_PORTF_INTB_POS 24 194#define IRQ_PORTF_INTB_POS 24
195#define IRQ_SPI0_ERROR_POS 28 195#define IRQ_SPI0_ERROR_POS 28
196 196
197/* IAR6 BIT FIELDS */ 197/* IAR6 BIT FIELDS */
198#define IRQ_SPI1_ERROR_POS 0 198#define IRQ_SPI1_ERROR_POS 0
199#define IRQ_RSI_INT0_POS 12 199#define IRQ_RSI_INT0_POS 12
200#define IRQ_RSI_INT1_POS 16 200#define IRQ_RSI_INT1_POS 16
201#define IRQ_PWM_TRIP_POS 20 201#define IRQ_PWM_TRIP_POS 20
202#define IRQ_PWM_SYNC_POS 24 202#define IRQ_PWM_SYNC_POS 24
203#define IRQ_PTP_STAT_POS 28 203#define IRQ_PTP_STAT_POS 28
204 204
205#endif /* _BF518_IRQ_H_ */ 205#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
index 555d42ad08ed..ed7310ff819b 100644
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ b/arch/blackfin/mach-bf527/include/mach/irq.h
@@ -9,7 +9,7 @@
9 9
10#include <mach-common/irq.h> 10#include <mach-common/irq.h>
11 11
12#define NR_PERI_INTS (2 * 32) 12#define NR_PERI_INTS (2 * 32)
13 13
14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
@@ -24,21 +24,21 @@
24#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ 24#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
25#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ 25#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
26#define IRQ_RTC BFIN_IRQ(14) /* RTC */ 26#define IRQ_RTC BFIN_IRQ(14) /* RTC */
27#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */ 27#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
28#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ 28#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
29#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ 29#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
30#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */ 30#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
31#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ 31#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
32#define IRQ_TWI BFIN_IRQ(20) /* TWI */ 32#define IRQ_TWI BFIN_IRQ(20) /* TWI */
33#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */ 33#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
34#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ 34#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
35#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ 35#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
36#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ 36#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
37#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ 37#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
38#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ 38#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
39#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ 39#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
40#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */ 40#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
41#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ 41#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
42#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 42#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
43#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 43#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
44#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ 44#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
@@ -67,108 +67,108 @@
67#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */ 67#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
68#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */ 68#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
69 69
70#define SYS_IRQS BFIN_IRQ(63) /* 70 */ 70#define SYS_IRQS BFIN_IRQ(63) /* 70 */
71 71
72#define IRQ_PF0 71 72#define IRQ_PF0 71
73#define IRQ_PF1 72 73#define IRQ_PF1 72
74#define IRQ_PF2 73 74#define IRQ_PF2 73
75#define IRQ_PF3 74 75#define IRQ_PF3 74
76#define IRQ_PF4 75 76#define IRQ_PF4 75
77#define IRQ_PF5 76 77#define IRQ_PF5 76
78#define IRQ_PF6 77 78#define IRQ_PF6 77
79#define IRQ_PF7 78 79#define IRQ_PF7 78
80#define IRQ_PF8 79 80#define IRQ_PF8 79
81#define IRQ_PF9 80 81#define IRQ_PF9 80
82#define IRQ_PF10 81 82#define IRQ_PF10 81
83#define IRQ_PF11 82 83#define IRQ_PF11 82
84#define IRQ_PF12 83 84#define IRQ_PF12 83
85#define IRQ_PF13 84 85#define IRQ_PF13 84
86#define IRQ_PF14 85 86#define IRQ_PF14 85
87#define IRQ_PF15 86 87#define IRQ_PF15 86
88 88
89#define IRQ_PG0 87 89#define IRQ_PG0 87
90#define IRQ_PG1 88 90#define IRQ_PG1 88
91#define IRQ_PG2 89 91#define IRQ_PG2 89
92#define IRQ_PG3 90 92#define IRQ_PG3 90
93#define IRQ_PG4 91 93#define IRQ_PG4 91
94#define IRQ_PG5 92 94#define IRQ_PG5 92
95#define IRQ_PG6 93 95#define IRQ_PG6 93
96#define IRQ_PG7 94 96#define IRQ_PG7 94
97#define IRQ_PG8 95 97#define IRQ_PG8 95
98#define IRQ_PG9 96 98#define IRQ_PG9 96
99#define IRQ_PG10 97 99#define IRQ_PG10 97
100#define IRQ_PG11 98 100#define IRQ_PG11 98
101#define IRQ_PG12 99 101#define IRQ_PG12 99
102#define IRQ_PG13 100 102#define IRQ_PG13 100
103#define IRQ_PG14 101 103#define IRQ_PG14 101
104#define IRQ_PG15 102 104#define IRQ_PG15 102
105 105
106#define IRQ_PH0 103 106#define IRQ_PH0 103
107#define IRQ_PH1 104 107#define IRQ_PH1 104
108#define IRQ_PH2 105 108#define IRQ_PH2 105
109#define IRQ_PH3 106 109#define IRQ_PH3 106
110#define IRQ_PH4 107 110#define IRQ_PH4 107
111#define IRQ_PH5 108 111#define IRQ_PH5 108
112#define IRQ_PH6 109 112#define IRQ_PH6 109
113#define IRQ_PH7 110 113#define IRQ_PH7 110
114#define IRQ_PH8 111 114#define IRQ_PH8 111
115#define IRQ_PH9 112 115#define IRQ_PH9 112
116#define IRQ_PH10 113 116#define IRQ_PH10 113
117#define IRQ_PH11 114 117#define IRQ_PH11 114
118#define IRQ_PH12 115 118#define IRQ_PH12 115
119#define IRQ_PH13 116 119#define IRQ_PH13 116
120#define IRQ_PH14 117 120#define IRQ_PH14 117
121#define IRQ_PH15 118 121#define IRQ_PH15 118
122 122
123#define GPIO_IRQ_BASE IRQ_PF0 123#define GPIO_IRQ_BASE IRQ_PF0
124 124
125#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */ 125#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
126#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */ 126#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
127#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */ 127#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
128#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */ 128#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
129#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */ 129#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
130#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */ 130#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
131#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */ 131#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
132#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ 132#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
133 133
134#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 134#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
135 135
136/* IAR0 BIT FIELDS */ 136/* IAR0 BIT FIELDS */
137#define IRQ_PLL_WAKEUP_POS 0 137#define IRQ_PLL_WAKEUP_POS 0
138#define IRQ_DMA0_ERROR_POS 4 138#define IRQ_DMA0_ERROR_POS 4
139#define IRQ_DMAR0_BLK_POS 8 139#define IRQ_DMAR0_BLK_POS 8
140#define IRQ_DMAR1_BLK_POS 12 140#define IRQ_DMAR1_BLK_POS 12
141#define IRQ_DMAR0_OVR_POS 16 141#define IRQ_DMAR0_OVR_POS 16
142#define IRQ_DMAR1_OVR_POS 20 142#define IRQ_DMAR1_OVR_POS 20
143#define IRQ_PPI_ERROR_POS 24 143#define IRQ_PPI_ERROR_POS 24
144#define IRQ_MAC_ERROR_POS 28 144#define IRQ_MAC_ERROR_POS 28
145 145
146/* IAR1 BIT FIELDS */ 146/* IAR1 BIT FIELDS */
147#define IRQ_SPORT0_ERROR_POS 0 147#define IRQ_SPORT0_ERROR_POS 0
148#define IRQ_SPORT1_ERROR_POS 4 148#define IRQ_SPORT1_ERROR_POS 4
149#define IRQ_UART0_ERROR_POS 16 149#define IRQ_UART0_ERROR_POS 16
150#define IRQ_UART1_ERROR_POS 20 150#define IRQ_UART1_ERROR_POS 20
151#define IRQ_RTC_POS 24 151#define IRQ_RTC_POS 24
152#define IRQ_PPI_POS 28 152#define IRQ_PPI_POS 28
153 153
154/* IAR2 BIT FIELDS */ 154/* IAR2 BIT FIELDS */
155#define IRQ_SPORT0_RX_POS 0 155#define IRQ_SPORT0_RX_POS 0
156#define IRQ_SPORT0_TX_POS 4 156#define IRQ_SPORT0_TX_POS 4
157#define IRQ_SPORT1_RX_POS 8 157#define IRQ_SPORT1_RX_POS 8
158#define IRQ_SPORT1_TX_POS 12 158#define IRQ_SPORT1_TX_POS 12
159#define IRQ_TWI_POS 16 159#define IRQ_TWI_POS 16
160#define IRQ_SPI_POS 20 160#define IRQ_SPI_POS 20
161#define IRQ_UART0_RX_POS 24 161#define IRQ_UART0_RX_POS 24
162#define IRQ_UART0_TX_POS 28 162#define IRQ_UART0_TX_POS 28
163 163
164/* IAR3 BIT FIELDS */ 164/* IAR3 BIT FIELDS */
165#define IRQ_UART1_RX_POS 0 165#define IRQ_UART1_RX_POS 0
166#define IRQ_UART1_TX_POS 4 166#define IRQ_UART1_TX_POS 4
167#define IRQ_OPTSEC_POS 8 167#define IRQ_OPTSEC_POS 8
168#define IRQ_CNT_POS 12 168#define IRQ_CNT_POS 12
169#define IRQ_MAC_RX_POS 16 169#define IRQ_MAC_RX_POS 16
170#define IRQ_PORTH_INTA_POS 20 170#define IRQ_PORTH_INTA_POS 20
171#define IRQ_MAC_TX_POS 24 171#define IRQ_MAC_TX_POS 24
172#define IRQ_PORTH_INTB_POS 28 172#define IRQ_PORTH_INTB_POS 28
173 173
174/* IAR4 BIT FIELDS */ 174/* IAR4 BIT FIELDS */
@@ -184,21 +184,21 @@
184/* IAR5 BIT FIELDS */ 184/* IAR5 BIT FIELDS */
185#define IRQ_PORTG_INTA_POS 0 185#define IRQ_PORTG_INTA_POS 0
186#define IRQ_PORTG_INTB_POS 4 186#define IRQ_PORTG_INTB_POS 4
187#define IRQ_MEM_DMA0_POS 8 187#define IRQ_MEM_DMA0_POS 8
188#define IRQ_MEM_DMA1_POS 12 188#define IRQ_MEM_DMA1_POS 12
189#define IRQ_WATCH_POS 16 189#define IRQ_WATCH_POS 16
190#define IRQ_PORTF_INTA_POS 20 190#define IRQ_PORTF_INTA_POS 20
191#define IRQ_PORTF_INTB_POS 24 191#define IRQ_PORTF_INTB_POS 24
192#define IRQ_SPI_ERROR_POS 28 192#define IRQ_SPI_ERROR_POS 28
193 193
194/* IAR6 BIT FIELDS */ 194/* IAR6 BIT FIELDS */
195#define IRQ_NFC_ERROR_POS 0 195#define IRQ_NFC_ERROR_POS 0
196#define IRQ_HDMA_ERROR_POS 4 196#define IRQ_HDMA_ERROR_POS 4
197#define IRQ_HDMA_POS 8 197#define IRQ_HDMA_POS 8
198#define IRQ_USB_EINT_POS 12 198#define IRQ_USB_EINT_POS 12
199#define IRQ_USB_INT0_POS 16 199#define IRQ_USB_INT0_POS 16
200#define IRQ_USB_INT1_POS 20 200#define IRQ_USB_INT1_POS 20
201#define IRQ_USB_INT2_POS 24 201#define IRQ_USB_INT2_POS 24
202#define IRQ_USB_DMA_POS 28 202#define IRQ_USB_DMA_POS 28
203 203
204#endif /* _BF527_IRQ_H_ */ 204#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
index c4c29fc4ea90..ed19567f96d3 100644
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -9,33 +9,34 @@
9 9
10#include <mach-common/irq.h> 10#include <mach-common/irq.h>
11 11
12#define SYS_IRQS 31 12#define NR_PERI_INTS 24
13#define NR_PERI_INTS 24
14 13
15#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
16#define IRQ_DMA_ERROR 8 /*DMA Error (general) */ 15#define IRQ_DMA_ERROR 8 /* DMA Error (general) */
17#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */ 16#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */
18#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */ 17#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */
19#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */ 18#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */
20#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */ 19#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */
21#define IRQ_UART0_ERROR 13 /*UART Error Interrupt */ 20#define IRQ_UART0_ERROR 13 /* UART Error Interrupt */
22#define IRQ_RTC 14 /*RTC Interrupt */ 21#define IRQ_RTC 14 /* RTC Interrupt */
23#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */ 22#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */
24#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */ 23#define IRQ_SPORT0_RX 16 /* DMA1 Interrupt (SPORT0 RX) */
25#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */ 24#define IRQ_SPORT0_TX 17 /* DMA2 Interrupt (SPORT0 TX) */
26#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */ 25#define IRQ_SPORT1_RX 18 /* DMA3 Interrupt (SPORT1 RX) */
27#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */ 26#define IRQ_SPORT1_TX 19 /* DMA4 Interrupt (SPORT1 TX) */
28#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */ 27#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */
29#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */ 28#define IRQ_UART0_RX 21 /* DMA6 Interrupt (UART RX) */
30#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */ 29#define IRQ_UART0_TX 22 /* DMA7 Interrupt (UART TX) */
31#define IRQ_TIMER0 23 /*Timer 0 */ 30#define IRQ_TIMER0 23 /* Timer 0 */
32#define IRQ_TIMER1 24 /*Timer 1 */ 31#define IRQ_TIMER1 24 /* Timer 1 */
33#define IRQ_TIMER2 25 /*Timer 2 */ 32#define IRQ_TIMER2 25 /* Timer 2 */
34#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */ 33#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */
35#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */ 34#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */
36#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */ 35#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */
37#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */ 36#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */
38#define IRQ_WATCH 30 /*Watch Dog Timer */ 37#define IRQ_WATCH 30 /* Watch Dog Timer */
38
39#define SYS_IRQS 31
39 40
40#define IRQ_PF0 33 41#define IRQ_PF0 33
41#define IRQ_PF1 34 42#define IRQ_PF1 34
@@ -58,34 +59,34 @@
58 59
59#define NR_MACH_IRQS (IRQ_PF15 + 1) 60#define NR_MACH_IRQS (IRQ_PF15 + 1)
60 61
61/* IAR0 BIT FIELDS*/ 62/* IAR0 BIT FIELDS */
62#define RTC_ERROR_POS 28 63#define RTC_ERROR_POS 28
63#define UART_ERROR_POS 24 64#define UART_ERROR_POS 24
64#define SPORT1_ERROR_POS 20 65#define SPORT1_ERROR_POS 20
65#define SPI_ERROR_POS 16 66#define SPI_ERROR_POS 16
66#define SPORT0_ERROR_POS 12 67#define SPORT0_ERROR_POS 12
67#define PPI_ERROR_POS 8 68#define PPI_ERROR_POS 8
68#define DMA_ERROR_POS 4 69#define DMA_ERROR_POS 4
69#define PLLWAKE_ERROR_POS 0 70#define PLLWAKE_ERROR_POS 0
70 71
71/* IAR1 BIT FIELDS*/ 72/* IAR1 BIT FIELDS */
72#define DMA7_UARTTX_POS 28 73#define DMA7_UARTTX_POS 28
73#define DMA6_UARTRX_POS 24 74#define DMA6_UARTRX_POS 24
74#define DMA5_SPI_POS 20 75#define DMA5_SPI_POS 20
75#define DMA4_SPORT1TX_POS 16 76#define DMA4_SPORT1TX_POS 16
76#define DMA3_SPORT1RX_POS 12 77#define DMA3_SPORT1RX_POS 12
77#define DMA2_SPORT0TX_POS 8 78#define DMA2_SPORT0TX_POS 8
78#define DMA1_SPORT0RX_POS 4 79#define DMA1_SPORT0RX_POS 4
79#define DMA0_PPI_POS 0 80#define DMA0_PPI_POS 0
80 81
81/* IAR2 BIT FIELDS*/ 82/* IAR2 BIT FIELDS */
82#define WDTIMER_POS 28 83#define WDTIMER_POS 28
83#define MEMDMA1_POS 24 84#define MEMDMA1_POS 24
84#define MEMDMA0_POS 20 85#define MEMDMA0_POS 20
85#define PFB_POS 16 86#define PFB_POS 16
86#define PFA_POS 12 87#define PFA_POS 12
87#define TIMER2_POS 8 88#define TIMER2_POS 8
88#define TIMER1_POS 4 89#define TIMER1_POS 4
89#define TIMER0_POS 0 90#define TIMER0_POS 0
90 91
91#endif /* _BF533_IRQ_H_ */ 92#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 2a8194eadb4c..09234b75aa77 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -9,154 +9,155 @@
9 9
10#include <mach-common/irq.h> 10#include <mach-common/irq.h>
11 11
12#define SYS_IRQS 39 12#define NR_PERI_INTS 32
13#define NR_PERI_INTS 32 13
14 14#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */
15#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */ 15#define IRQ_DMA_ERROR 8 /* DMA Error (general) */
16#define IRQ_DMA_ERROR 8 /*DMA Error (general) */ 16#define IRQ_GENERIC_ERROR 9 /* GENERIC Error Interrupt */
17#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */ 17#define IRQ_RTC 10 /* RTC Interrupt */
18#define IRQ_RTC 10 /*RTC Interrupt */ 18#define IRQ_PPI 11 /* DMA0 Interrupt (PPI) */
19#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */ 19#define IRQ_SPORT0_RX 12 /* DMA3 Interrupt (SPORT0 RX) */
20#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */ 20#define IRQ_SPORT0_TX 13 /* DMA4 Interrupt (SPORT0 TX) */
21#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */ 21#define IRQ_SPORT1_RX 14 /* DMA5 Interrupt (SPORT1 RX) */
22#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */ 22#define IRQ_SPORT1_TX 15 /* DMA6 Interrupt (SPORT1 TX) */
23#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */ 23#define IRQ_TWI 16 /* TWI Interrupt */
24#define IRQ_TWI 16 /*TWI Interrupt */ 24#define IRQ_SPI 17 /* DMA7 Interrupt (SPI) */
25#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */ 25#define IRQ_UART0_RX 18 /* DMA8 Interrupt (UART0 RX) */
26#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */ 26#define IRQ_UART0_TX 19 /* DMA9 Interrupt (UART0 TX) */
27#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */ 27#define IRQ_UART1_RX 20 /* DMA10 Interrupt (UART1 RX) */
28#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */ 28#define IRQ_UART1_TX 21 /* DMA11 Interrupt (UART1 TX) */
29#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */ 29#define IRQ_CAN_RX 22 /* CAN Receive Interrupt */
30#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */ 30#define IRQ_CAN_TX 23 /* CAN Transmit Interrupt */
31#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */ 31#define IRQ_MAC_RX 24 /* DMA1 (Ethernet RX) Interrupt */
32#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */ 32#define IRQ_MAC_TX 25 /* DMA2 (Ethernet TX) Interrupt */
33#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */ 33#define IRQ_TIMER0 26 /* Timer 0 */
34#define IRQ_TIMER0 26 /*Timer 0 */ 34#define IRQ_TIMER1 27 /* Timer 1 */
35#define IRQ_TIMER1 27 /*Timer 1 */ 35#define IRQ_TIMER2 28 /* Timer 2 */
36#define IRQ_TIMER2 28 /*Timer 2 */ 36#define IRQ_TIMER3 29 /* Timer 3 */
37#define IRQ_TIMER3 29 /*Timer 3 */ 37#define IRQ_TIMER4 30 /* Timer 4 */
38#define IRQ_TIMER4 30 /*Timer 4 */ 38#define IRQ_TIMER5 31 /* Timer 5 */
39#define IRQ_TIMER5 31 /*Timer 5 */ 39#define IRQ_TIMER6 32 /* Timer 6 */
40#define IRQ_TIMER6 32 /*Timer 6 */ 40#define IRQ_TIMER7 33 /* Timer 7 */
41#define IRQ_TIMER7 33 /*Timer 7 */ 41#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
42#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */ 42#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
43#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */ 43#define IRQ_MEM_DMA0 36 /* (Memory DMA Stream 0) */
44#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */ 44#define IRQ_MEM_DMA1 37 /* (Memory DMA Stream 1) */
45#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */ 45#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
46#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */ 46#define IRQ_WATCH 38 /* Watch Dog Timer */
47#define IRQ_WATCH 38 /*Watch Dog Timer */ 47
48 48#define SYS_IRQS 39
49#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */ 49
50#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */ 50#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
51#define IRQ_MAC_ERROR 44 /*MAC Status/Error Interrupt */ 51#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
52#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */ 52#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
53#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */ 53#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
54#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */ 54#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
55#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */ 55#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
56#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */ 56#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
57 57#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
58#define IRQ_PF0 50 58
59#define IRQ_PF1 51 59#define IRQ_PF0 50
60#define IRQ_PF2 52 60#define IRQ_PF1 51
61#define IRQ_PF3 53 61#define IRQ_PF2 52
62#define IRQ_PF4 54 62#define IRQ_PF3 53
63#define IRQ_PF5 55 63#define IRQ_PF4 54
64#define IRQ_PF6 56 64#define IRQ_PF5 55
65#define IRQ_PF7 57 65#define IRQ_PF6 56
66#define IRQ_PF8 58 66#define IRQ_PF7 57
67#define IRQ_PF9 59 67#define IRQ_PF8 58
68#define IRQ_PF10 60 68#define IRQ_PF9 59
69#define IRQ_PF11 61 69#define IRQ_PF10 60
70#define IRQ_PF12 62 70#define IRQ_PF11 61
71#define IRQ_PF13 63 71#define IRQ_PF12 62
72#define IRQ_PF14 64 72#define IRQ_PF13 63
73#define IRQ_PF15 65 73#define IRQ_PF14 64
74 74#define IRQ_PF15 65
75#define IRQ_PG0 66 75
76#define IRQ_PG1 67 76#define IRQ_PG0 66
77#define IRQ_PG2 68 77#define IRQ_PG1 67
78#define IRQ_PG3 69 78#define IRQ_PG2 68
79#define IRQ_PG4 70 79#define IRQ_PG3 69
80#define IRQ_PG5 71 80#define IRQ_PG4 70
81#define IRQ_PG6 72 81#define IRQ_PG5 71
82#define IRQ_PG7 73 82#define IRQ_PG6 72
83#define IRQ_PG8 74 83#define IRQ_PG7 73
84#define IRQ_PG9 75 84#define IRQ_PG8 74
85#define IRQ_PG10 76 85#define IRQ_PG9 75
86#define IRQ_PG11 77 86#define IRQ_PG10 76
87#define IRQ_PG12 78 87#define IRQ_PG11 77
88#define IRQ_PG13 79 88#define IRQ_PG12 78
89#define IRQ_PG14 80 89#define IRQ_PG13 79
90#define IRQ_PG15 81 90#define IRQ_PG14 80
91 91#define IRQ_PG15 81
92#define IRQ_PH0 82 92
93#define IRQ_PH1 83 93#define IRQ_PH0 82
94#define IRQ_PH2 84 94#define IRQ_PH1 83
95#define IRQ_PH3 85 95#define IRQ_PH2 84
96#define IRQ_PH4 86 96#define IRQ_PH3 85
97#define IRQ_PH5 87 97#define IRQ_PH4 86
98#define IRQ_PH6 88 98#define IRQ_PH5 87
99#define IRQ_PH7 89 99#define IRQ_PH6 88
100#define IRQ_PH8 90 100#define IRQ_PH7 89
101#define IRQ_PH9 91 101#define IRQ_PH8 90
102#define IRQ_PH10 92 102#define IRQ_PH9 91
103#define IRQ_PH11 93 103#define IRQ_PH10 92
104#define IRQ_PH12 94 104#define IRQ_PH11 93
105#define IRQ_PH13 95 105#define IRQ_PH12 94
106#define IRQ_PH14 96 106#define IRQ_PH13 95
107#define IRQ_PH15 97 107#define IRQ_PH14 96
108 108#define IRQ_PH15 97
109#define GPIO_IRQ_BASE IRQ_PF0 109
110 110#define GPIO_IRQ_BASE IRQ_PF0
111#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */ 111
112#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */ 112#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
113#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */ 113#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
114#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */ 114#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
115#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */ 115#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
116#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */ 116#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
117#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */ 117#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
118#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */ 118#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
119 119#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
120#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 120
121 121#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
122/* IAR0 BIT FIELDS*/ 122
123#define IRQ_PLL_WAKEUP_POS 0 123/* IAR0 BIT FIELDS */
124#define IRQ_DMA_ERROR_POS 4 124#define IRQ_PLL_WAKEUP_POS 0
125#define IRQ_ERROR_POS 8 125#define IRQ_DMA_ERROR_POS 4
126#define IRQ_RTC_POS 12 126#define IRQ_ERROR_POS 8
127#define IRQ_PPI_POS 16 127#define IRQ_RTC_POS 12
128#define IRQ_SPORT0_RX_POS 20 128#define IRQ_PPI_POS 16
129#define IRQ_SPORT0_TX_POS 24 129#define IRQ_SPORT0_RX_POS 20
130#define IRQ_SPORT1_RX_POS 28 130#define IRQ_SPORT0_TX_POS 24
131 131#define IRQ_SPORT1_RX_POS 28
132/* IAR1 BIT FIELDS*/ 132
133#define IRQ_SPORT1_TX_POS 0 133/* IAR1 BIT FIELDS */
134#define IRQ_TWI_POS 4 134#define IRQ_SPORT1_TX_POS 0
135#define IRQ_SPI_POS 8 135#define IRQ_TWI_POS 4
136#define IRQ_UART0_RX_POS 12 136#define IRQ_SPI_POS 8
137#define IRQ_UART0_TX_POS 16 137#define IRQ_UART0_RX_POS 12
138#define IRQ_UART1_RX_POS 20 138#define IRQ_UART0_TX_POS 16
139#define IRQ_UART1_TX_POS 24 139#define IRQ_UART1_RX_POS 20
140#define IRQ_CAN_RX_POS 28 140#define IRQ_UART1_TX_POS 24
141 141#define IRQ_CAN_RX_POS 28
142/* IAR2 BIT FIELDS*/ 142
143#define IRQ_CAN_TX_POS 0 143/* IAR2 BIT FIELDS */
144#define IRQ_MAC_RX_POS 4 144#define IRQ_CAN_TX_POS 0
145#define IRQ_MAC_TX_POS 8 145#define IRQ_MAC_RX_POS 4
146#define IRQ_TIMER0_POS 12 146#define IRQ_MAC_TX_POS 8
147#define IRQ_TIMER1_POS 16 147#define IRQ_TIMER0_POS 12
148#define IRQ_TIMER2_POS 20 148#define IRQ_TIMER1_POS 16
149#define IRQ_TIMER3_POS 24 149#define IRQ_TIMER2_POS 20
150#define IRQ_TIMER4_POS 28 150#define IRQ_TIMER3_POS 24
151 151#define IRQ_TIMER4_POS 28
152/* IAR3 BIT FIELDS*/ 152
153#define IRQ_TIMER5_POS 0 153/* IAR3 BIT FIELDS */
154#define IRQ_TIMER6_POS 4 154#define IRQ_TIMER5_POS 0
155#define IRQ_TIMER7_POS 8 155#define IRQ_TIMER6_POS 4
156#define IRQ_PROG_INTA_POS 12 156#define IRQ_TIMER7_POS 8
157#define IRQ_PORTG_INTB_POS 16 157#define IRQ_PROG_INTA_POS 12
158#define IRQ_MEM_DMA0_POS 20 158#define IRQ_PORTG_INTB_POS 16
159#define IRQ_MEM_DMA1_POS 24 159#define IRQ_MEM_DMA0_POS 20
160#define IRQ_WATCH_POS 28 160#define IRQ_MEM_DMA1_POS 24
161 161#define IRQ_WATCH_POS 28
162#endif /* _BF537_IRQ_H_ */ 162
163#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
index 08d47675d71f..07ca069d37cd 100644
--- a/arch/blackfin/mach-bf538/include/mach/irq.h
+++ b/arch/blackfin/mach-bf538/include/mach/irq.h
@@ -9,7 +9,7 @@
9 9
10#include <mach-common/irq.h> 10#include <mach-common/irq.h>
11 11
12#define NR_PERI_INTS (2 * 32) 12#define NR_PERI_INTS (2 * 32)
13 13
14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
@@ -62,26 +62,26 @@
62 62
63#define SYS_IRQS BFIN_IRQ(63) /* 70 */ 63#define SYS_IRQS BFIN_IRQ(63) /* 70 */
64 64
65#define IRQ_PF0 71 65#define IRQ_PF0 71
66#define IRQ_PF1 72 66#define IRQ_PF1 72
67#define IRQ_PF2 73 67#define IRQ_PF2 73
68#define IRQ_PF3 74 68#define IRQ_PF3 74
69#define IRQ_PF4 75 69#define IRQ_PF4 75
70#define IRQ_PF5 76 70#define IRQ_PF5 76
71#define IRQ_PF6 77 71#define IRQ_PF6 77
72#define IRQ_PF7 78 72#define IRQ_PF7 78
73#define IRQ_PF8 79 73#define IRQ_PF8 79
74#define IRQ_PF9 80 74#define IRQ_PF9 80
75#define IRQ_PF10 81 75#define IRQ_PF10 81
76#define IRQ_PF11 82 76#define IRQ_PF11 82
77#define IRQ_PF12 83 77#define IRQ_PF12 83
78#define IRQ_PF13 84 78#define IRQ_PF13 84
79#define IRQ_PF14 85 79#define IRQ_PF14 85
80#define IRQ_PF15 86 80#define IRQ_PF15 86
81 81
82#define GPIO_IRQ_BASE IRQ_PF0 82#define GPIO_IRQ_BASE IRQ_PF0
83 83
84#define NR_MACH_IRQS (IRQ_PF15 + 1) 84#define NR_MACH_IRQS (IRQ_PF15 + 1)
85 85
86/* IAR0 BIT FIELDS */ 86/* IAR0 BIT FIELDS */
87#define IRQ_PLL_WAKEUP_POS 0 87#define IRQ_PLL_WAKEUP_POS 0
@@ -144,4 +144,5 @@
144#define IRQ_CAN_TX_POS 0 144#define IRQ_CAN_TX_POS 0
145#define IRQ_MEM1_DMA0_POS 4 145#define IRQ_MEM1_DMA0_POS 4
146#define IRQ_MEM1_DMA1_POS 8 146#define IRQ_MEM1_DMA1_POS 8
147#endif /* _BF538_IRQ_H_ */ 147
148#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 19f209ff4329..533b8095b540 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -9,7 +9,7 @@
9 9
10#include <mach-common/irq.h> 10#include <mach-common/irq.h>
11 11
12#define NR_PERI_INTS (32 * 3) 12#define NR_PERI_INTS (3 * 32)
13 13
14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
15#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */ 15#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
@@ -282,35 +282,35 @@
282#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */ 282#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
283#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */ 283#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
284 284
285#define GPIO_IRQ_BASE IRQ_PA0 285#define GPIO_IRQ_BASE IRQ_PA0
286 286
287#define NR_MACH_IRQS (IRQ_PJ15 + 1) 287#define NR_MACH_IRQS (IRQ_PJ15 + 1)
288 288
289/* For compatibility reasons with existing code */ 289/* For compatibility reasons with existing code */
290 290
291#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR 291#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
292#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR 292#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
293#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR 293#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
294#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR 294#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
295#define IRQ_SPI0_ERR IRQ_SPI0_ERROR 295#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
296#define IRQ_UART0_ERR IRQ_UART0_ERROR 296#define IRQ_UART0_ERR IRQ_UART0_ERROR
297#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR 297#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
298#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR 298#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
299#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR 299#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
300#define IRQ_SPI1_ERR IRQ_SPI1_ERROR 300#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
301#define IRQ_SPI2_ERR IRQ_SPI2_ERROR 301#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
302#define IRQ_UART1_ERR IRQ_UART1_ERROR 302#define IRQ_UART1_ERR IRQ_UART1_ERROR
303#define IRQ_UART2_ERR IRQ_UART2_ERROR 303#define IRQ_UART2_ERR IRQ_UART2_ERROR
304#define IRQ_CAN0_ERR IRQ_CAN0_ERROR 304#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
305#define IRQ_MXVR_ERR IRQ_MXVR_ERROR 305#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
306#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR 306#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
307#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR 307#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
308#define IRQ_UART3_ERR IRQ_UART3_ERROR 308#define IRQ_UART3_ERR IRQ_UART3_ERROR
309#define IRQ_HOST_ERR IRQ_HOST_ERROR 309#define IRQ_HOST_ERR IRQ_HOST_ERROR
310#define IRQ_PIXC_ERR IRQ_PIXC_ERROR 310#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
311#define IRQ_NFC_ERR IRQ_NFC_ERROR 311#define IRQ_NFC_ERR IRQ_NFC_ERROR
312#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR 312#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
313#define IRQ_CAN1_ERR IRQ_CAN1_ERROR 313#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
314#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR 314#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
315 315
316/* IAR0 BIT FIELDS */ 316/* IAR0 BIT FIELDS */
@@ -451,4 +451,4 @@ struct bfin_pint_regs {
451 451
452#endif 452#endif
453 453
454#endif /* _BF548_IRQ_H_ */ 454#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h
index aa8f5953a1ac..391091efcfe3 100644
--- a/arch/blackfin/mach-bf561/include/mach/irq.h
+++ b/arch/blackfin/mach-bf561/include/mach/irq.h
@@ -9,106 +9,97 @@
9 9
10#include <mach-common/irq.h> 10#include <mach-common/irq.h>
11 11
12#define SYS_IRQS 71 12#define NR_PERI_INTS (2 * 32)
13#define NR_PERI_INTS 64
14 13
15#define IVG_BASE 7 14#define IVG_BASE 7
16/* IVG 7 */ 15#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
17#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */ 16#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
18#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */ 17#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
19#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */ 18#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */
20#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */ 19#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */
21#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */ 20#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */
22#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */ 21#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
23#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */ 22#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */
24#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */ 23#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */
25#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */ 24#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
26#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */ 25#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
27#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */ 26#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
28#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */ 27#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed */
29#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */ 28#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
30/* IVG 8 */ 29#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
31#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */ 30#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
32#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ 31#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */
33#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ 32#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
34#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */ 33#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */
35#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */ 34#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */
36#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */ 35#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */
37#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */ 36#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */
38#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */ 37#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */
39#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */ 38#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */
40#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */ 39#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */
41#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */ 40#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
42#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */ 41#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
43#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */ 42#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
44#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */ 43#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
45#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */ 44#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
46/* IVG 9 */ 45#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
47#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */ 46#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
48#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */ 47#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */
49#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */ 48#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
50#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */ 49#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */
51#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */ 50#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
52#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */ 51#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */
53#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */ 52#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
54#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */ 53#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */
55#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */ 54#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
56#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */ 55#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */
57#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */ 56#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
58#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */ 57#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */
59#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */ 58#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */
60#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */ 59#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
61#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */ 60#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
62#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */ 61#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
63#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */ 62#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
64#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */ 63#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
65#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */ 64#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
66/* IVG 10 */ 65#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */
67#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */ 66#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */
68#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */ 67#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */
69#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */ 68#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */
70#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */ 69#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */
71#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */ 70#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */
72#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */ 71#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
73#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */ 72#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
74#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */ 73#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
75#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */ 74#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
76#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */ 75#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
77#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */ 76#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
78#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */ 77#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
79/* IVG 11 */ 78#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */
80#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */ 79#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
81#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */ 80#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
82#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */ 81#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
83#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */ 82#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
84#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */ 83#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
85#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
86#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
87#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
88/* IVG 8 */
89#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
90#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
91#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0 84#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
92#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */ 85#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */
93#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */ 86#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
94#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1 87#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
95/* IVG 9 */ 88#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
96#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
97#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0 89#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
98#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */ 90#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */
99#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1 91#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
100/* IVG 12 */ 92#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
101#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
102#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0 93#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
103#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */ 94#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */
104#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1 95#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
105/* IVG 13 */ 96#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */
106#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */ 97#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */
107/* IVG 7 */ 98#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
108#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */
109#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
110#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ 99#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
111#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */ 100#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* Supplemental interrupt 1 */
101
102#define SYS_IRQS 71
112 103
113#define IRQ_PF0 73 104#define IRQ_PF0 73
114#define IRQ_PF1 74 105#define IRQ_PF1 74
@@ -163,146 +154,84 @@
163 154
164#define NR_MACH_IRQS (IRQ_PF47 + 1) 155#define NR_MACH_IRQS (IRQ_PF47 + 1)
165 156
166/*
167 * DEFAULT PRIORITIES:
168 */
169
170#define CONFIG_DEF_PLL_WAKEUP 7
171#define CONFIG_DEF_DMA1_ERROR 7
172#define CONFIG_DEF_DMA2_ERROR 7
173#define CONFIG_DEF_IMDMA_ERROR 7
174#define CONFIG_DEF_PPI1_ERROR 7
175#define CONFIG_DEF_PPI2_ERROR 7
176#define CONFIG_DEF_SPORT0_ERROR 7
177#define CONFIG_DEF_SPORT1_ERROR 7
178#define CONFIG_DEF_SPI_ERROR 7
179#define CONFIG_DEF_UART_ERROR 7
180#define CONFIG_DEF_RESERVED_ERROR 7
181#define CONFIG_DEF_DMA1_0 8
182#define CONFIG_DEF_DMA1_1 8
183#define CONFIG_DEF_DMA1_2 8
184#define CONFIG_DEF_DMA1_3 8
185#define CONFIG_DEF_DMA1_4 8
186#define CONFIG_DEF_DMA1_5 8
187#define CONFIG_DEF_DMA1_6 8
188#define CONFIG_DEF_DMA1_7 8
189#define CONFIG_DEF_DMA1_8 8
190#define CONFIG_DEF_DMA1_9 8
191#define CONFIG_DEF_DMA1_10 8
192#define CONFIG_DEF_DMA1_11 8
193#define CONFIG_DEF_DMA2_0 9
194#define CONFIG_DEF_DMA2_1 9
195#define CONFIG_DEF_DMA2_2 9
196#define CONFIG_DEF_DMA2_3 9
197#define CONFIG_DEF_DMA2_4 9
198#define CONFIG_DEF_DMA2_5 9
199#define CONFIG_DEF_DMA2_6 9
200#define CONFIG_DEF_DMA2_7 9
201#define CONFIG_DEF_DMA2_8 9
202#define CONFIG_DEF_DMA2_9 9
203#define CONFIG_DEF_DMA2_10 9
204#define CONFIG_DEF_DMA2_11 9
205#define CONFIG_DEF_TIMER0 10
206#define CONFIG_DEF_TIMER1 10
207#define CONFIG_DEF_TIMER2 10
208#define CONFIG_DEF_TIMER3 10
209#define CONFIG_DEF_TIMER4 10
210#define CONFIG_DEF_TIMER5 10
211#define CONFIG_DEF_TIMER6 10
212#define CONFIG_DEF_TIMER7 10
213#define CONFIG_DEF_TIMER8 10
214#define CONFIG_DEF_TIMER9 10
215#define CONFIG_DEF_TIMER10 10
216#define CONFIG_DEF_TIMER11 10
217#define CONFIG_DEF_PROG0_INTA 11
218#define CONFIG_DEF_PROG0_INTB 11
219#define CONFIG_DEF_PROG1_INTA 11
220#define CONFIG_DEF_PROG1_INTB 11
221#define CONFIG_DEF_PROG2_INTA 11
222#define CONFIG_DEF_PROG2_INTB 11
223#define CONFIG_DEF_DMA1_WRRD0 8
224#define CONFIG_DEF_DMA1_WRRD1 8
225#define CONFIG_DEF_DMA2_WRRD0 9
226#define CONFIG_DEF_DMA2_WRRD1 9
227#define CONFIG_DEF_IMDMA_WRRD0 12
228#define CONFIG_DEF_IMDMA_WRRD1 12
229#define CONFIG_DEF_WATCH 13
230#define CONFIG_DEF_RESERVED_1 7
231#define CONFIG_DEF_RESERVED_2 7
232#define CONFIG_DEF_SUPPLE_0 7
233#define CONFIG_DEF_SUPPLE_1 7
234
235/* IAR0 BIT FIELDS */ 157/* IAR0 BIT FIELDS */
236#define IRQ_PLL_WAKEUP_POS 0 158#define IRQ_PLL_WAKEUP_POS 0
237#define IRQ_DMA1_ERROR_POS 4 159#define IRQ_DMA1_ERROR_POS 4
238#define IRQ_DMA2_ERROR_POS 8 160#define IRQ_DMA2_ERROR_POS 8
239#define IRQ_IMDMA_ERROR_POS 12 161#define IRQ_IMDMA_ERROR_POS 12
240#define IRQ_PPI0_ERROR_POS 16 162#define IRQ_PPI0_ERROR_POS 16
241#define IRQ_PPI1_ERROR_POS 20 163#define IRQ_PPI1_ERROR_POS 20
242#define IRQ_SPORT0_ERROR_POS 24 164#define IRQ_SPORT0_ERROR_POS 24
243#define IRQ_SPORT1_ERROR_POS 28 165#define IRQ_SPORT1_ERROR_POS 28
166
244/* IAR1 BIT FIELDS */ 167/* IAR1 BIT FIELDS */
245#define IRQ_SPI_ERROR_POS 0 168#define IRQ_SPI_ERROR_POS 0
246#define IRQ_UART_ERROR_POS 4 169#define IRQ_UART_ERROR_POS 4
247#define IRQ_RESERVED_ERROR_POS 8 170#define IRQ_RESERVED_ERROR_POS 8
248#define IRQ_DMA1_0_POS 12 171#define IRQ_DMA1_0_POS 12
249#define IRQ_DMA1_1_POS 16 172#define IRQ_DMA1_1_POS 16
250#define IRQ_DMA1_2_POS 20 173#define IRQ_DMA1_2_POS 20
251#define IRQ_DMA1_3_POS 24 174#define IRQ_DMA1_3_POS 24
252#define IRQ_DMA1_4_POS 28 175#define IRQ_DMA1_4_POS 28
176
253/* IAR2 BIT FIELDS */ 177/* IAR2 BIT FIELDS */
254#define IRQ_DMA1_5_POS 0 178#define IRQ_DMA1_5_POS 0
255#define IRQ_DMA1_6_POS 4 179#define IRQ_DMA1_6_POS 4
256#define IRQ_DMA1_7_POS 8 180#define IRQ_DMA1_7_POS 8
257#define IRQ_DMA1_8_POS 12 181#define IRQ_DMA1_8_POS 12
258#define IRQ_DMA1_9_POS 16 182#define IRQ_DMA1_9_POS 16
259#define IRQ_DMA1_10_POS 20 183#define IRQ_DMA1_10_POS 20
260#define IRQ_DMA1_11_POS 24 184#define IRQ_DMA1_11_POS 24
261#define IRQ_DMA2_0_POS 28 185#define IRQ_DMA2_0_POS 28
186
262/* IAR3 BIT FIELDS */ 187/* IAR3 BIT FIELDS */
263#define IRQ_DMA2_1_POS 0 188#define IRQ_DMA2_1_POS 0
264#define IRQ_DMA2_2_POS 4 189#define IRQ_DMA2_2_POS 4
265#define IRQ_DMA2_3_POS 8 190#define IRQ_DMA2_3_POS 8
266#define IRQ_DMA2_4_POS 12 191#define IRQ_DMA2_4_POS 12
267#define IRQ_DMA2_5_POS 16 192#define IRQ_DMA2_5_POS 16
268#define IRQ_DMA2_6_POS 20 193#define IRQ_DMA2_6_POS 20
269#define IRQ_DMA2_7_POS 24 194#define IRQ_DMA2_7_POS 24
270#define IRQ_DMA2_8_POS 28 195#define IRQ_DMA2_8_POS 28
196
271/* IAR4 BIT FIELDS */ 197/* IAR4 BIT FIELDS */
272#define IRQ_DMA2_9_POS 0 198#define IRQ_DMA2_9_POS 0
273#define IRQ_DMA2_10_POS 4 199#define IRQ_DMA2_10_POS 4
274#define IRQ_DMA2_11_POS 8 200#define IRQ_DMA2_11_POS 8
275#define IRQ_TIMER0_POS 12 201#define IRQ_TIMER0_POS 12
276#define IRQ_TIMER1_POS 16 202#define IRQ_TIMER1_POS 16
277#define IRQ_TIMER2_POS 20 203#define IRQ_TIMER2_POS 20
278#define IRQ_TIMER3_POS 24 204#define IRQ_TIMER3_POS 24
279#define IRQ_TIMER4_POS 28 205#define IRQ_TIMER4_POS 28
206
280/* IAR5 BIT FIELDS */ 207/* IAR5 BIT FIELDS */
281#define IRQ_TIMER5_POS 0 208#define IRQ_TIMER5_POS 0
282#define IRQ_TIMER6_POS 4 209#define IRQ_TIMER6_POS 4
283#define IRQ_TIMER7_POS 8 210#define IRQ_TIMER7_POS 8
284#define IRQ_TIMER8_POS 12 211#define IRQ_TIMER8_POS 12
285#define IRQ_TIMER9_POS 16 212#define IRQ_TIMER9_POS 16
286#define IRQ_TIMER10_POS 20 213#define IRQ_TIMER10_POS 20
287#define IRQ_TIMER11_POS 24 214#define IRQ_TIMER11_POS 24
288#define IRQ_PROG0_INTA_POS 28 215#define IRQ_PROG0_INTA_POS 28
216
289/* IAR6 BIT FIELDS */ 217/* IAR6 BIT FIELDS */
290#define IRQ_PROG0_INTB_POS 0 218#define IRQ_PROG0_INTB_POS 0
291#define IRQ_PROG1_INTA_POS 4 219#define IRQ_PROG1_INTA_POS 4
292#define IRQ_PROG1_INTB_POS 8 220#define IRQ_PROG1_INTB_POS 8
293#define IRQ_PROG2_INTA_POS 12 221#define IRQ_PROG2_INTA_POS 12
294#define IRQ_PROG2_INTB_POS 16 222#define IRQ_PROG2_INTB_POS 16
295#define IRQ_DMA1_WRRD0_POS 20 223#define IRQ_DMA1_WRRD0_POS 20
296#define IRQ_DMA1_WRRD1_POS 24 224#define IRQ_DMA1_WRRD1_POS 24
297#define IRQ_DMA2_WRRD0_POS 28 225#define IRQ_DMA2_WRRD0_POS 28
226
298/* IAR7 BIT FIELDS */ 227/* IAR7 BIT FIELDS */
299#define IRQ_DMA2_WRRD1_POS 0 228#define IRQ_DMA2_WRRD1_POS 0
300#define IRQ_IMDMA_WRRD0_POS 4 229#define IRQ_IMDMA_WRRD0_POS 4
301#define IRQ_IMDMA_WRRD1_POS 8 230#define IRQ_IMDMA_WRRD1_POS 8
302#define IRQ_WDTIMER_POS 12 231#define IRQ_WDTIMER_POS 12
303#define IRQ_RESERVED_1_POS 16 232#define IRQ_RESERVED_1_POS 16
304#define IRQ_RESERVED_2_POS 20 233#define IRQ_RESERVED_2_POS 20
305#define IRQ_SUPPLE_0_POS 24 234#define IRQ_SUPPLE_0_POS 24
306#define IRQ_SUPPLE_1_POS 28 235#define IRQ_SUPPLE_1_POS 28
307 236
308#endif /* _BF561_IRQ_H_ */ 237#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 23:09:34 -0500