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authorChen-Yu Tsai <wens@csie.org>2014-07-15 13:15:45 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-07-18 16:36:49 -0400
commit3dca65f8a67c525cbddfb1fca149435ab4ce37b0 (patch)
treea8998d471b60d39aee3befaa89ea9c5787554ade
parented29861ae87953e0d559baaf9d225e8f8a8ff19a (diff)
ARM: dts: sun6i: Add A31 GMAC gigabit ethernet controller node
The A31 has the same GMAC found on the A20 SoC, except it has an extra reset control. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index b78a5aa4bccc..578fde202cc1 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -691,6 +691,23 @@
691 status = "disabled"; 691 status = "disabled";
692 }; 692 };
693 693
694 gmac: ethernet@01c30000 {
695 compatible = "allwinner,sun7i-a20-gmac";
696 reg = <0x01c30000 0x1054>;
697 interrupts = <0 82 4>;
698 interrupt-names = "macirq";
699 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
700 clock-names = "stmmaceth", "allwinner_gmac_tx";
701 resets = <&ahb1_rst 17>;
702 reset-names = "stmmaceth";
703 snps,pbl = <2>;
704 snps,fixed-burst;
705 snps,force_sf_dma_mode;
706 status = "disabled";
707 #address-cells = <1>;
708 #size-cells = <0>;
709 };
710
694 timer@01c60000 { 711 timer@01c60000 {
695 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; 712 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
696 reg = <0x01c60000 0x1000>; 713 reg = <0x01c60000 0x1000>;