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authorDaniel Vetter <daniel.vetter@ffwll.ch>2015-04-01 07:43:46 -0400
committerJani Nikula <jani.nikula@intel.com>2015-04-14 10:03:12 -0400
commit37ef01ab5d24d1d520dc79f6a98099d451c2a901 (patch)
treeed1e53e3d615e3189d81151e03ed7eec350b57e0
parente0d6149b3debce1a7e17dfda7c2829935917dc58 (diff)
drm/i915: Dont enable CS_PARSER_ERROR interrupts at all
We stopped handling them in commit aaecdf611a05cac26a94713bad25297e60225c29 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Tue Nov 4 15:52:22 2014 +0100 drm/i915: Stop gathering error states for CS error interrupts but just clearing is apparently not enough: A sufficiently dead gpu left behind by firmware (*cough* coreboot *cough*) can keep the gpu in an endless loop of such interrupts, eventually leading to the nmi firing. And definitely to what looks like a machine hang. Since we don't even enable these interrupts on gen5+ let's do the same on earlier platforms. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=93171 Tested-by: Mono <mono-for-kernel-org@donderklumpen.de> Tested-by: info@gluglug.org.uk Cc: stable@vger.kernel.org Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 14ecb4d13a1a..6d494432b19f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3598,14 +3598,12 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
3598 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3598 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3599 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3599 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3600 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3600 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3601 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 3601 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3602 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3603 I915_WRITE16(IMR, dev_priv->irq_mask); 3602 I915_WRITE16(IMR, dev_priv->irq_mask);
3604 3603
3605 I915_WRITE16(IER, 3604 I915_WRITE16(IER,
3606 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3605 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3607 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3606 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3608 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3609 I915_USER_INTERRUPT); 3607 I915_USER_INTERRUPT);
3610 POSTING_READ16(IER); 3608 POSTING_READ16(IER);
3611 3609
@@ -3767,14 +3765,12 @@ static int i915_irq_postinstall(struct drm_device *dev)
3767 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3765 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3768 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3766 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3769 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3767 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3770 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 3768 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3771 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3772 3769
3773 enable_mask = 3770 enable_mask =
3774 I915_ASLE_INTERRUPT | 3771 I915_ASLE_INTERRUPT |
3775 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3772 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3776 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3773 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3777 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3778 I915_USER_INTERRUPT; 3774 I915_USER_INTERRUPT;
3779 3775
3780 if (I915_HAS_HOTPLUG(dev)) { 3776 if (I915_HAS_HOTPLUG(dev)) {