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authorArnd Bergmann <arnd@arndb.de>2015-03-11 16:14:55 -0400
committerArnd Bergmann <arnd@arndb.de>2015-03-11 16:14:55 -0400
commit369237ab1fe5539091320f47781d6fe2db0241b9 (patch)
treedde849f93c9d7f9b9cef8128030dbaa939f77265
parent605e0f904bb6b9ba13f8d7918f3c016ac00b86bc (diff)
parent3915d36fabf143dffdf91c5372d3b0a23722af52 (diff)
Merge tag 'renesas-r8a7778-ccf-and-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/multiplatform
Pull "Renesas ARM Based SoC r8a7778 CCF and Multiplatform Updates for v4.1" from Simon Horman: * Add CCF and them multiplatform support to r8a7778 SoC and its bockw board. * tag 'renesas-r8a7778-ccf-and-multiplatform-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (21 commits) ARM: shmobile: r8a7778: enable multiplatform target ARM: shmobile: bockw: add sound to DT ARM: shmobile: r8a7778: add sound to DT ARM: shmobile: bockw: add devices hooked up to i2c0 to DT DT: i2c: add trivial binding for OKI ML86V7667 video decoder ARM: shmobile: r8a7778: common clock framework CPG driver ARM: shmobile: bockw dts: set extal clock frequency ARM: shmobile: bockw dts: Move Ethernet node to BSC ARM: shmobile: r8a7778 dtsi: Add Bus State Controller node ARM: shmobile: bockw: add USB, VIN pin descriptions to DT ARM: shmobile: r8a7778: add internal ethernet controller to DT ARM: shmobile: r8a7778: add MSTP clock assignments to DT ARM: shmobile: r8a7778: implement SoC and board CCF support ARM: shmobile: r8a7778: Common clock framework DT description ARM: shmobile: r8a7778: add CPG register bits header ARM: shmobile: r8a7778: synchronize dts with reference platform drivers: bus: Add Simple Power-Managed Bus Driver drivers: bus: Add Renesas Bus State Controller (BSC) DT Bindings drivers: bus: Add Simple Power-Managed Bus DT Bindings drivers: bus: Sort Makefile entries alphabetically ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/bus/renesas,bsc.txt46
-rw-r--r--Documentation/devicetree/bindings/bus/simple-pm-bus.txt44
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt25
-rw-r--r--Documentation/devicetree/bindings/i2c/trivial-devices.txt1
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw.dts174
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi293
-rw-r--r--arch/arm/mach-shmobile/Kconfig4
-rw-r--r--arch/arm/mach-shmobile/board-bockw-reference.c2
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c19
-rw-r--r--drivers/bus/Kconfig53
-rw-r--r--drivers/bus/Makefile15
-rw-r--r--drivers/bus/simple-pm-bus.c58
-rw-r--r--drivers/clk/shmobile/Makefile1
-rw-r--r--drivers/clk/shmobile/clk-r8a7778.c143
-rw-r--r--include/dt-bindings/clock/r8a7778-clock.h71
-rw-r--r--include/linux/clk/shmobile.h1
17 files changed, 924 insertions, 27 deletions
diff --git a/Documentation/devicetree/bindings/bus/renesas,bsc.txt b/Documentation/devicetree/bindings/bus/renesas,bsc.txt
new file mode 100644
index 000000000000..90e947269437
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/renesas,bsc.txt
@@ -0,0 +1,46 @@
1Renesas Bus State Controller (BSC)
2==================================
3
4The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
5Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs.
6It provides an external bus for connecting multiple external devices to the
7SoC, driving several chip select lines, for e.g. NOR FLASH, Ethernet and USB.
8
9While the BSC is a fairly simple memory-mapped bus, it may be part of a PM
10domain, and may have a gateable functional clock.
11Before a device connected to the BSC can be accessed, the PM domain
12containing the BSC must be powered on, and the functional clock
13driving the BSC must be enabled.
14
15The bindings for the BSC extend the bindings for "simple-pm-bus".
16
17
18Required properties
19 - compatible: Must contain an SoC-specific value, and "renesas,bsc" and
20 "simple-pm-bus" as fallbacks.
21 SoC-specific values can be:
22 "renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4)
23 "renesas,bsc-sh73a0" for SH-Mobile AG5 (sh73a0)
24 - #address-cells, #size-cells, ranges: Must describe the mapping between
25 parent address and child address spaces.
26 - reg: Must contain the base address and length to access the bus controller.
27
28Optional properties:
29 - interrupts: Must contain a reference to the BSC interrupt, if available.
30 - clocks: Must contain a reference to the functional clock, if available.
31 - power-domains: Must contain a reference to the PM domain, if available.
32
33
34Example:
35
36 bsc: bus@fec10000 {
37 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
38 "simple-pm-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 ranges = <0 0 0x20000000>;
42 reg = <0xfec10000 0x400>;
43 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
44 clocks = <&zb_clk>;
45 power-domains = <&pd_a4s>;
46 };
diff --git a/Documentation/devicetree/bindings/bus/simple-pm-bus.txt b/Documentation/devicetree/bindings/bus/simple-pm-bus.txt
new file mode 100644
index 000000000000..d032237512c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/simple-pm-bus.txt
@@ -0,0 +1,44 @@
1Simple Power-Managed Bus
2========================
3
4A Simple Power-Managed Bus is a transparent bus that doesn't need a real
5driver, as it's typically initialized by the boot loader.
6
7However, its bus controller is part of a PM domain, or under the control of a
8functional clock. Hence, the bus controller's PM domain and/or clock must be
9enabled for child devices connected to the bus (either on-SoC or externally)
10to function.
11
12While "simple-pm-bus" follows the "simple-bus" set of properties, as specified
13in ePAPR, it is not an extension of "simple-bus".
14
15
16Required properties:
17 - compatible: Must contain at least "simple-pm-bus".
18 Must not contain "simple-bus".
19 It's recommended to let this be preceded by one or more
20 vendor-specific compatible values.
21 - #address-cells, #size-cells, ranges: Must describe the mapping between
22 parent address and child address spaces.
23
24Optional platform-specific properties for clock or PM domain control (at least
25one of them is required):
26 - clocks: Must contain a reference to the functional clock(s),
27 - power-domains: Must contain a reference to the PM domain.
28Please refer to the binding documentation for the clock and/or PM domain
29providers for more details.
30
31
32Example:
33
34 bsc: bus@fec10000 {
35 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
36 "simple-pm-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges = <0 0 0x20000000>;
40 reg = <0xfec10000 0x400>;
41 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
42 clocks = <&zb_clk>;
43 power-domains = <&pd_a4s>;
44 };
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
new file mode 100644
index 000000000000..2f3747fdcf1c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
@@ -0,0 +1,25 @@
1* Renesas R8A7778 Clock Pulse Generator (CPG)
2
3The CPG generates core clocks for the R8A7778. It includes two PLLs and
4several fixed ratio dividers
5
6Required Properties:
7
8 - compatible: Must be "renesas,r8a7778-cpg-clocks"
9 - reg: Base address and length of the memory resource used by the CPG
10 - #clock-cells: Must be 1
11 - clock-output-names: The names of the clocks. Supported clocks are
12 "plla", "pllb", "b", "out", "p", "s", and "s1".
13
14
15Example
16-------
17
18 cpg_clocks: cpg_clocks@ffc80000 {
19 compatible = "renesas,r8a7778-cpg-clocks";
20 reg = <0xffc80000 0x80>;
21 #clock-cells = <1>;
22 clocks = <&extal_clk>;
23 clock-output-names = "plla", "pllb", "b",
24 "out", "p", "s", "s1";
25 };
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index aaa8325004d2..7cbd62ba1f6c 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -77,6 +77,7 @@ nxp,pca9556 Octal SMBus and I2C registered interface
77nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset 77nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
78nxp,pcf8563 Real-time clock/calendar 78nxp,pcf8563 Real-time clock/calendar
79nxp,pcf85063 Tiny Real-Time Clock 79nxp,pcf85063 Tiny Real-Time Clock
80oki,ml86v7667 OKI ML86V7667 video decoder
80ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus 81ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
81pericom,pt7c4338 Real-time Clock Module 82pericom,pt7c4338 Real-time Clock Module
82plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch 83plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0d467b877ec7..16f4a6761f5e 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -477,6 +477,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
477 r7s72100-genmai.dtb \ 477 r7s72100-genmai.dtb \
478 r8a73a4-ape6evm.dtb \ 478 r8a73a4-ape6evm.dtb \
479 r8a7740-armadillo800eva.dtb \ 479 r8a7740-armadillo800eva.dtb \
480 r8a7778-bockw.dtb \
480 r8a7779-marzen.dtb \ 481 r8a7779-marzen.dtb \
481 r8a7790-lager.dtb \ 482 r8a7790-lager.dtb \
482 r8a7791-henninger.dtb \ 483 r8a7791-henninger.dtb \
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index 46a884d45175..787fa6f9f46d 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -16,17 +16,191 @@
16 16
17/dts-v1/; 17/dts-v1/;
18#include "r8a7778.dtsi" 18#include "r8a7778.dtsi"
19#include <dt-bindings/interrupt-controller/irq.h>
20#include <dt-bindings/gpio/gpio.h>
19 21
20/ { 22/ {
21 model = "bockw"; 23 model = "bockw";
22 compatible = "renesas,bockw", "renesas,r8a7778"; 24 compatible = "renesas,bockw", "renesas,r8a7778";
23 25
26 aliases {
27 serial0 = &scif0;
28 };
29
24 chosen { 30 chosen {
25 bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw"; 31 bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw";
32 stdout-path = &scif0;
26 }; 33 };
27 34
28 memory { 35 memory {
29 device_type = "memory"; 36 device_type = "memory";
30 reg = <0x60000000 0x10000000>; 37 reg = <0x60000000 0x10000000>;
31 }; 38 };
39
40 fixedregulator3v3: fixedregulator@0 {
41 compatible = "regulator-fixed";
42 regulator-name = "fixed-3.3V";
43 regulator-min-microvolt = <3300000>;
44 regulator-max-microvolt = <3300000>;
45 regulator-boot-on;
46 regulator-always-on;
47 };
48
49 sound {
50 compatible = "simple-audio-card";
51
52 simple-audio-card,format = "left_j";
53 simple-audio-card,bitclock-master = <&sndcodec>;
54 simple-audio-card,frame-master = <&sndcodec>;
55
56 sndcpu: simple-audio-card,cpu {
57 sound-dai = <&rcar_sound>;
58 };
59
60 sndcodec: simple-audio-card,codec {
61 sound-dai = <&ak4643>;
62 system-clock-frequency = <11289600>;
63 };
64 };
65};
66
67&bsc {
68 ethernet@18300000 {
69 compatible = "smsc,lan9220", "smsc,lan9115";
70 reg = <0x18300000 0x1000>;
71
72 phy-mode = "mii";
73 interrupt-parent = <&irqpin>;
74 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
75 reg-io-width = <4>;
76 vddvario-supply = <&fixedregulator3v3>;
77 vdd33a-supply = <&fixedregulator3v3>;
78 };
79};
80
81&extal_clk {
82 clock-frequency = <33333333>;
83};
84
85&i2c0 {
86 status = "okay";
87
88 ak4643: sound-codec@12 {
89 compatible = "asahi-kasei,ak4643";
90 #sound-dai-cells = <0>;
91 reg = <0x12>;
92 };
93
94 camera@41 {
95 compatible = "oki,ml86v7667";
96 reg = <0x41>;
97 };
98
99 camera@43 {
100 compatible = "oki,ml86v7667";
101 reg = <0x43>;
102 };
103
104 rx8581: rtc@51 {
105 compatible = "epson,rx8581";
106 reg = <0x51>;
107 };
108};
109
110&mmcif {
111 pinctrl-0 = <&mmc_pins>;
112 pinctrl-names = "default";
113
114 vmmc-supply = <&fixedregulator3v3>;
115 bus-width = <8>;
116 broken-cd;
117 status = "okay";
118};
119
120&irqpin {
121 status = "okay";
122};
123
124&tmu0 {
125 status = "okay";
126};
127
128&pfc {
129 scif0_pins: serial0 {
130 renesas,groups = "scif0_data_a", "scif0_ctrl";
131 renesas,function = "scif0";
132 };
133
134 mmc_pins: mmc {
135 renesas,groups = "mmc_data8", "mmc_ctrl";
136 renesas,function = "mmc";
137 };
138
139 sdhi0_pins: sd0 {
140 renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
141 "sdhi0_cd";
142 renesas,function = "sdhi0";
143 };
144
145 hspi0_pins: hspi0 {
146 renesas,groups = "hspi0_a";
147 renesas,function = "hspi0";
148 };
149
150 usb0_pins: usb0 {
151 renesas,groups = "usb0";
152 renesas,function = "usb0";
153 };
154
155 usb1_pins: usb1 {
156 renesas,groups = "usb1";
157 renesas,function = "usb1";
158 };
159
160 vin0_pins: vin0 {
161 renesas,groups = "vin0_data8", "vin0_clk";
162 renesas,function = "vin0";
163 };
164
165 vin1_pins: vin1 {
166 renesas,groups = "vin1_data8", "vin1_clk";
167 renesas,function = "vin1";
168 };
169};
170
171&sdhi0 {
172 pinctrl-0 = <&sdhi0_pins>;
173 pinctrl-names = "default";
174
175 vmmc-supply = <&fixedregulator3v3>;
176 bus-width = <4>;
177 status = "okay";
178 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
179};
180
181&hspi0 {
182 pinctrl-0 = <&hspi0_pins>;
183 pinctrl-names = "default";
184 status = "okay";
185
186 flash: flash@0 {
187 #address-cells = <1>;
188 #size-cells = <1>;
189 compatible = "spansion,s25fl008k";
190 reg = <0>;
191 spi-max-frequency = <104000000>;
192 m25p,fast-read;
193
194 partition@0 {
195 label = "data(spi)";
196 reg = <0x00000000 0x00100000>;
197 };
198 };
199};
200
201&scif0 {
202 pinctrl-0 = <&scif0_pins>;
203 pinctrl-names = "default";
204
205 status = "okay";
32}; 206};
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index ef8533910029..868f97309533 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -16,6 +16,7 @@
16 16
17/include/ "skeleton.dtsi" 17/include/ "skeleton.dtsi"
18 18
19#include <dt-bindings/clock/r8a7778-clock.h>
19#include <dt-bindings/interrupt-controller/irq.h> 20#include <dt-bindings/interrupt-controller/irq.h>
20 21
21/ { 22/ {
@@ -40,6 +41,24 @@
40 spi2 = &hspi2; 41 spi2 = &hspi2;
41 }; 42 };
42 43
44 bsc: bus@1c000000 {
45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges = <0 0 0x1c000000>;
49 };
50
51 ether: ethernet@fde00000 {
52 compatible = "renesas,ether-r8a7778";
53 reg = <0xfde00000 0x400>;
54 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
56 phy-mode = "rmii";
57 #address-cells = <1>;
58 #size-cells = <0>;
59 status = "disabled";
60 };
61
43 gic: interrupt-controller@fe438000 { 62 gic: interrupt-controller@fe438000 {
44 compatible = "arm,cortex-a9-gic"; 63 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>; 64 #interrupt-cells = <3>;
@@ -132,6 +151,7 @@
132 compatible = "renesas,i2c-r8a7778"; 151 compatible = "renesas,i2c-r8a7778";
133 reg = <0xffc70000 0x1000>; 152 reg = <0xffc70000 0x1000>;
134 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; 153 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
135 status = "disabled"; 155 status = "disabled";
136 }; 156 };
137 157
@@ -141,6 +161,7 @@
141 compatible = "renesas,i2c-r8a7778"; 161 compatible = "renesas,i2c-r8a7778";
142 reg = <0xffc71000 0x1000>; 162 reg = <0xffc71000 0x1000>;
143 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 163 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
144 status = "disabled"; 165 status = "disabled";
145 }; 166 };
146 167
@@ -150,6 +171,7 @@
150 compatible = "renesas,i2c-r8a7778"; 171 compatible = "renesas,i2c-r8a7778";
151 reg = <0xffc72000 0x1000>; 172 reg = <0xffc72000 0x1000>;
152 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; 173 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
153 status = "disabled"; 175 status = "disabled";
154 }; 176 };
155 177
@@ -159,6 +181,7 @@
159 compatible = "renesas,i2c-r8a7778"; 181 compatible = "renesas,i2c-r8a7778";
160 reg = <0xffc73000 0x1000>; 182 reg = <0xffc73000 0x1000>;
161 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; 183 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
162 status = "disabled"; 185 status = "disabled";
163 }; 186 };
164 187
@@ -168,6 +191,8 @@
168 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 191 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
169 <0 33 IRQ_TYPE_LEVEL_HIGH>, 192 <0 33 IRQ_TYPE_LEVEL_HIGH>,
170 <0 34 IRQ_TYPE_LEVEL_HIGH>; 193 <0 34 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
195 clock-names = "fck";
171 196
172 #renesas,channels = <3>; 197 #renesas,channels = <3>;
173 198
@@ -180,6 +205,8 @@
180 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, 205 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
181 <0 37 IRQ_TYPE_LEVEL_HIGH>, 206 <0 37 IRQ_TYPE_LEVEL_HIGH>,
182 <0 38 IRQ_TYPE_LEVEL_HIGH>; 207 <0 38 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
209 clock-names = "fck";
183 210
184 #renesas,channels = <3>; 211 #renesas,channels = <3>;
185 212
@@ -192,16 +219,75 @@
192 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, 219 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
193 <0 41 IRQ_TYPE_LEVEL_HIGH>, 220 <0 41 IRQ_TYPE_LEVEL_HIGH>,
194 <0 42 IRQ_TYPE_LEVEL_HIGH>; 221 <0 42 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
223 clock-names = "fck";
195 224
196 #renesas,channels = <3>; 225 #renesas,channels = <3>;
197 226
198 status = "disabled"; 227 status = "disabled";
199 }; 228 };
200 229
230 rcar_sound: sound@ffd90000 {
231 #sound-dai-cells = <1>;
232 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
233 reg = <0xffd90000 0x1000>, /* SRU */
234 <0xffd91000 0x1240>, /* SSI */
235 <0xfffe0000 0x24>; /* ADG */
236 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
237 <&mstp3_clks R8A7778_CLK_SSI7>,
238 <&mstp3_clks R8A7778_CLK_SSI6>,
239 <&mstp3_clks R8A7778_CLK_SSI5>,
240 <&mstp3_clks R8A7778_CLK_SSI4>,
241 <&mstp0_clks R8A7778_CLK_SSI3>,
242 <&mstp0_clks R8A7778_CLK_SSI2>,
243 <&mstp0_clks R8A7778_CLK_SSI1>,
244 <&mstp0_clks R8A7778_CLK_SSI0>,
245 <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
246 <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
247 <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
248 <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
249 <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
250 <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
251 <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
252 <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
253 <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
254 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
255 <&cpg_clocks R8A7778_CLK_S1>;
256 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
257 "ssi.3", "ssi.2", "ssi.1", "ssi.0",
258 "src.8", "src.7", "src.6", "src.5", "src.4",
259 "src.3", "src.2", "src.1", "src.0",
260 "clk_a", "clk_b", "clk_c", "clk_i";
261
262 status = "disabled";
263
264 rcar_sound,src {
265 src3: src@3 { };
266 src4: src@4 { };
267 src5: src@5 { };
268 src6: src@6 { };
269 src7: src@7 { };
270 src8: src@8 { };
271 src9: src@9 { };
272 };
273
274 rcar_sound,ssi {
275 ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
276 ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
277 ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
278 ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
279 ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
280 ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
281 ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
282 };
283 };
284
201 scif0: serial@ffe40000 { 285 scif0: serial@ffe40000 {
202 compatible = "renesas,scif-r8a7778", "renesas,scif"; 286 compatible = "renesas,scif-r8a7778", "renesas,scif";
203 reg = <0xffe40000 0x100>; 287 reg = <0xffe40000 0x100>;
204 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; 288 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
290 clock-names = "sci_ick";
205 status = "disabled"; 291 status = "disabled";
206 }; 292 };
207 293
@@ -209,6 +295,8 @@
209 compatible = "renesas,scif-r8a7778", "renesas,scif"; 295 compatible = "renesas,scif-r8a7778", "renesas,scif";
210 reg = <0xffe41000 0x100>; 296 reg = <0xffe41000 0x100>;
211 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; 297 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
299 clock-names = "sci_ick";
212 status = "disabled"; 300 status = "disabled";
213 }; 301 };
214 302
@@ -216,6 +304,8 @@
216 compatible = "renesas,scif-r8a7778", "renesas,scif"; 304 compatible = "renesas,scif-r8a7778", "renesas,scif";
217 reg = <0xffe42000 0x100>; 305 reg = <0xffe42000 0x100>;
218 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 306 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
308 clock-names = "sci_ick";
219 status = "disabled"; 309 status = "disabled";
220 }; 310 };
221 311
@@ -223,6 +313,8 @@
223 compatible = "renesas,scif-r8a7778", "renesas,scif"; 313 compatible = "renesas,scif-r8a7778", "renesas,scif";
224 reg = <0xffe43000 0x100>; 314 reg = <0xffe43000 0x100>;
225 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 315 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
317 clock-names = "sci_ick";
226 status = "disabled"; 318 status = "disabled";
227 }; 319 };
228 320
@@ -230,6 +322,8 @@
230 compatible = "renesas,scif-r8a7778", "renesas,scif"; 322 compatible = "renesas,scif-r8a7778", "renesas,scif";
231 reg = <0xffe44000 0x100>; 323 reg = <0xffe44000 0x100>;
232 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 324 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
326 clock-names = "sci_ick";
233 status = "disabled"; 327 status = "disabled";
234 }; 328 };
235 329
@@ -237,6 +331,8 @@
237 compatible = "renesas,scif-r8a7778", "renesas,scif"; 331 compatible = "renesas,scif-r8a7778", "renesas,scif";
238 reg = <0xffe45000 0x100>; 332 reg = <0xffe45000 0x100>;
239 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 333 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
335 clock-names = "sci_ick";
240 status = "disabled"; 336 status = "disabled";
241 }; 337 };
242 338
@@ -244,6 +340,7 @@
244 compatible = "renesas,sh-mmcif"; 340 compatible = "renesas,sh-mmcif";
245 reg = <0xffe4e000 0x100>; 341 reg = <0xffe4e000 0x100>;
246 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; 342 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
247 status = "disabled"; 344 status = "disabled";
248 }; 345 };
249 346
@@ -251,6 +348,7 @@
251 compatible = "renesas,sdhi-r8a7778"; 348 compatible = "renesas,sdhi-r8a7778";
252 reg = <0xffe4c000 0x100>; 349 reg = <0xffe4c000 0x100>;
253 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; 350 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
254 status = "disabled"; 352 status = "disabled";
255 }; 353 };
256 354
@@ -258,6 +356,7 @@
258 compatible = "renesas,sdhi-r8a7778"; 356 compatible = "renesas,sdhi-r8a7778";
259 reg = <0xffe4d000 0x100>; 357 reg = <0xffe4d000 0x100>;
260 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 358 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
261 status = "disabled"; 360 status = "disabled";
262 }; 361 };
263 362
@@ -265,6 +364,7 @@
265 compatible = "renesas,sdhi-r8a7778"; 364 compatible = "renesas,sdhi-r8a7778";
266 reg = <0xffe4f000 0x100>; 365 reg = <0xffe4f000 0x100>;
267 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 366 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
268 status = "disabled"; 368 status = "disabled";
269 }; 369 };
270 370
@@ -272,6 +372,7 @@
272 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 372 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
273 reg = <0xfffc7000 0x18>; 373 reg = <0xfffc7000 0x18>;
274 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; 374 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
275 #address-cells = <1>; 376 #address-cells = <1>;
276 #size-cells = <0>; 377 #size-cells = <0>;
277 status = "disabled"; 378 status = "disabled";
@@ -281,6 +382,7 @@
281 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 382 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
282 reg = <0xfffc8000 0x18>; 383 reg = <0xfffc8000 0x18>;
283 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 384 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
284 #address-cells = <1>; 386 #address-cells = <1>;
285 #size-cells = <0>; 387 #size-cells = <0>;
286 status = "disabled"; 388 status = "disabled";
@@ -290,8 +392,199 @@
290 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 392 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
291 reg = <0xfffc6000 0x18>; 393 reg = <0xfffc6000 0x18>;
292 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 394 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
293 #address-cells = <1>; 396 #address-cells = <1>;
294 #size-cells = <0>; 397 #size-cells = <0>;
295 status = "disabled"; 398 status = "disabled";
296 }; 399 };
400
401 clocks {
402 #address-cells = <1>;
403 #size-cells = <1>;
404 ranges;
405
406 /* External input clock */
407 extal_clk: extal_clk {
408 compatible = "fixed-clock";
409 #clock-cells = <0>;
410 clock-frequency = <0>;
411 clock-output-names = "extal";
412 };
413
414 /* Special CPG clocks */
415 cpg_clocks: cpg_clocks@ffc80000 {
416 compatible = "renesas,r8a7778-cpg-clocks";
417 reg = <0xffc80000 0x80>;
418 #clock-cells = <1>;
419 clocks = <&extal_clk>;
420 clock-output-names = "plla", "pllb", "b",
421 "out", "p", "s", "s1";
422 };
423
424 /* Audio clocks; frequencies are set by boards if applicable. */
425 audio_clk_a: audio_clk_a {
426 compatible = "fixed-clock";
427 #clock-cells = <0>;
428 clock-output-names = "audio_clk_a";
429 };
430 audio_clk_b: audio_clk_b {
431 compatible = "fixed-clock";
432 #clock-cells = <0>;
433 clock-output-names = "audio_clk_b";
434 };
435 audio_clk_c: audio_clk_c {
436 compatible = "fixed-clock";
437 #clock-cells = <0>;
438 clock-output-names = "audio_clk_c";
439 };
440
441 /* Fixed ratio clocks */
442 g_clk: g_clk {
443 compatible = "fixed-factor-clock";
444 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
445 #clock-cells = <0>;
446 clock-div = <12>;
447 clock-mult = <1>;
448 clock-output-names = "g";
449 };
450 i_clk: i_clk {
451 compatible = "fixed-factor-clock";
452 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
453 #clock-cells = <0>;
454 clock-div = <1>;
455 clock-mult = <1>;
456 clock-output-names = "i";
457 };
458 s3_clk: s3_clk {
459 compatible = "fixed-factor-clock";
460 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
461 #clock-cells = <0>;
462 clock-div = <4>;
463 clock-mult = <1>;
464 clock-output-names = "s3";
465 };
466 s4_clk: s4_clk {
467 compatible = "fixed-factor-clock";
468 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
469 #clock-cells = <0>;
470 clock-div = <8>;
471 clock-mult = <1>;
472 clock-output-names = "s4";
473 };
474 z_clk: z_clk {
475 compatible = "fixed-factor-clock";
476 clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
477 #clock-cells = <0>;
478 clock-div = <1>;
479 clock-mult = <1>;
480 clock-output-names = "z";
481 };
482
483 /* Gate clocks */
484 mstp0_clks: mstp0_clks@ffc80030 {
485 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
486 reg = <0xffc80030 4>;
487 clocks = <&cpg_clocks R8A7778_CLK_P>,
488 <&cpg_clocks R8A7778_CLK_P>,
489 <&cpg_clocks R8A7778_CLK_P>,
490 <&cpg_clocks R8A7778_CLK_P>,
491 <&cpg_clocks R8A7778_CLK_P>,
492 <&cpg_clocks R8A7778_CLK_P>,
493 <&cpg_clocks R8A7778_CLK_P>,
494 <&cpg_clocks R8A7778_CLK_P>,
495 <&cpg_clocks R8A7778_CLK_P>,
496 <&cpg_clocks R8A7778_CLK_P>,
497 <&cpg_clocks R8A7778_CLK_P>,
498 <&cpg_clocks R8A7778_CLK_P>,
499 <&cpg_clocks R8A7778_CLK_P>,
500 <&cpg_clocks R8A7778_CLK_P>,
501 <&cpg_clocks R8A7778_CLK_P>,
502 <&cpg_clocks R8A7778_CLK_P>,
503 <&cpg_clocks R8A7778_CLK_P>,
504 <&cpg_clocks R8A7778_CLK_P>,
505 <&cpg_clocks R8A7778_CLK_S>;
506 #clock-cells = <1>;
507 clock-indices = <
508 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
509 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
510 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
511 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
512 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
513 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
514 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
515 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
516 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
517 R8A7778_CLK_HSPI
518 >;
519 clock-output-names =
520 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
521 "scif1", "scif2", "scif3", "scif4", "scif5",
522 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
523 "ssi2", "ssi3", "sru", "hspi";
524 };
525 mstp1_clks: mstp1_clks@ffc80034 {
526 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
527 reg = <0xffc80034 4>, <0xffc80044 4>;
528 clocks = <&cpg_clocks R8A7778_CLK_P>,
529 <&cpg_clocks R8A7778_CLK_S>,
530 <&cpg_clocks R8A7778_CLK_S>,
531 <&cpg_clocks R8A7778_CLK_P>;
532 #clock-cells = <1>;
533 clock-indices = <
534 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
535 R8A7778_CLK_VIN1 R8A7778_CLK_USB
536 >;
537 clock-output-names =
538 "ether", "vin0", "vin1", "usb";
539 };
540 mstp3_clks: mstp3_clks@ffc8003c {
541 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
542 reg = <0xffc8003c 4>;
543 clocks = <&s4_clk>,
544 <&cpg_clocks R8A7778_CLK_P>,
545 <&cpg_clocks R8A7778_CLK_P>,
546 <&cpg_clocks R8A7778_CLK_P>,
547 <&cpg_clocks R8A7778_CLK_P>,
548 <&cpg_clocks R8A7778_CLK_P>,
549 <&cpg_clocks R8A7778_CLK_P>,
550 <&cpg_clocks R8A7778_CLK_P>,
551 <&cpg_clocks R8A7778_CLK_P>;
552 #clock-cells = <1>;
553 clock-indices = <
554 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
555 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
556 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
557 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
558 R8A7778_CLK_SSI8
559 >;
560 clock-output-names =
561 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
562 "ssi5", "ssi6", "ssi7", "ssi8";
563 };
564 mstp5_clks: mstp5_clks@ffc80054 {
565 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
566 reg = <0xffc80054 4>;
567 clocks = <&cpg_clocks R8A7778_CLK_P>,
568 <&cpg_clocks R8A7778_CLK_P>,
569 <&cpg_clocks R8A7778_CLK_P>,
570 <&cpg_clocks R8A7778_CLK_P>,
571 <&cpg_clocks R8A7778_CLK_P>,
572 <&cpg_clocks R8A7778_CLK_P>,
573 <&cpg_clocks R8A7778_CLK_P>,
574 <&cpg_clocks R8A7778_CLK_P>,
575 <&cpg_clocks R8A7778_CLK_P>;
576 #clock-cells = <1>;
577 clock-indices = <
578 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
579 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
580 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
581 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
582 R8A7778_CLK_SRU_SRC8
583 >;
584 clock-output-names =
585 "sru-src0", "sru-src1", "sru-src2",
586 "sru-src3", "sru-src4", "sru-src5",
587 "sru-src6", "sru-src7", "sru-src8";
588 };
589 };
297}; 590};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index a4ef122f85a0..15a7dba2a683 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -62,6 +62,10 @@ config ARCH_R8A7740
62 select ARCH_RMOBILE 62 select ARCH_RMOBILE
63 select RENESAS_INTC_IRQPIN 63 select RENESAS_INTC_IRQPIN
64 64
65config ARCH_R8A7778
66 bool "R-Car M1A (R8A77781)"
67 select ARCH_RCAR_GEN1
68
65config ARCH_R8A7779 69config ARCH_R8A7779
66 bool "R-Car H1 (R8A77790)" 70 bool "R-Car H1 (R8A77790)"
67 select ARCH_RCAR_GEN1 71 select ARCH_RCAR_GEN1
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index d649ade4a202..9a74efda3d18 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -36,7 +36,9 @@ static void __init bockw_init(void)
36 void __iomem *fpga; 36 void __iomem *fpga;
37 void __iomem *pfc; 37 void __iomem *pfc;
38 38
39#ifndef CONFIG_COMMON_CLK
39 r8a7778_clock_init(); 40 r8a7778_clock_init();
41#endif
40 r8a7778_init_irq_extpin_dt(1); 42 r8a7778_init_irq_extpin_dt(1);
41 r8a7778_add_dt_devices(); 43 r8a7778_add_dt_devices();
42 44
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index cef8895a9b82..c49aa094fe17 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -15,6 +15,7 @@
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 */ 16 */
17 17
18#include <linux/clk/shmobile.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/io.h> 20#include <linux/io.h>
20#include <linux/irqchip/arm-gic.h> 21#include <linux/irqchip/arm-gic.h>
@@ -41,6 +42,21 @@
41#include "irqs.h" 42#include "irqs.h"
42#include "r8a7778.h" 43#include "r8a7778.h"
43 44
45#define MODEMR 0xffcc0020
46
47#ifdef CONFIG_COMMON_CLK
48static void __init r8a7778_timer_init(void)
49{
50 u32 mode;
51 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
52
53 BUG_ON(!modemr);
54 mode = ioread32(modemr);
55 iounmap(modemr);
56 r8a7778_clocks_init(mode);
57}
58#endif
59
44/* SCIF */ 60/* SCIF */
45#define R8A7778_SCIF(index, baseaddr, irq) \ 61#define R8A7778_SCIF(index, baseaddr, irq) \
46static struct plat_sci_port scif##index##_platform_data = { \ 62static struct plat_sci_port scif##index##_platform_data = { \
@@ -608,6 +624,9 @@ DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
608 .init_early = shmobile_init_delay, 624 .init_early = shmobile_init_delay,
609 .init_irq = r8a7778_init_irq_dt, 625 .init_irq = r8a7778_init_irq_dt,
610 .init_late = shmobile_init_late, 626 .init_late = shmobile_init_late,
627#ifdef CONFIG_COMMON_CLK
628 .init_time = r8a7778_timer_init,
629#endif
611 .dt_compat = r8a7778_compat_dt, 630 .dt_compat = r8a7778_compat_dt,
612MACHINE_END 631MACHINE_END
613 632
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index b99729e36860..7e9c2674af81 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -4,6 +4,21 @@
4 4
5menu "Bus devices" 5menu "Bus devices"
6 6
7config ARM_CCI
8 bool "ARM CCI driver support"
9 depends on ARM && OF && CPU_V7
10 help
11 Driver supporting the CCI cache coherent interconnect for ARM
12 platforms.
13
14config ARM_CCN
15 bool "ARM CCN driver support"
16 depends on ARM || ARM64
17 depends on PERF_EVENTS
18 help
19 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
20 interconnect.
21
7config BRCMSTB_GISB_ARB 22config BRCMSTB_GISB_ARB
8 bool "Broadcom STB GISB bus arbiter" 23 bool "Broadcom STB GISB bus arbiter"
9 depends on ARM || MIPS 24 depends on ARM || MIPS
@@ -27,15 +42,6 @@ config MVEBU_MBUS
27 Driver needed for the MBus configuration on Marvell EBU SoCs 42 Driver needed for the MBus configuration on Marvell EBU SoCs
28 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP). 43 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
29 44
30config OMAP_OCP2SCP
31 tristate "OMAP OCP2SCP DRIVER"
32 depends on ARCH_OMAP2PLUS
33 help
34 Driver to enable ocp2scp module which transforms ocp interface
35 protocol to scp protocol. In OMAP4, USB PHY is connected via
36 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
37 OCP2SCP.
38
39config OMAP_INTERCONNECT 45config OMAP_INTERCONNECT
40 tristate "OMAP INTERCONNECT DRIVER" 46 tristate "OMAP INTERCONNECT DRIVER"
41 depends on ARCH_OMAP2PLUS 47 depends on ARCH_OMAP2PLUS
@@ -43,20 +49,27 @@ config OMAP_INTERCONNECT
43 help 49 help
44 Driver to enable OMAP interconnect error handling driver. 50 Driver to enable OMAP interconnect error handling driver.
45 51
46config ARM_CCI 52config OMAP_OCP2SCP
47 bool "ARM CCI driver support" 53 tristate "OMAP OCP2SCP DRIVER"
48 depends on ARM && OF && CPU_V7 54 depends on ARCH_OMAP2PLUS
49 help 55 help
50 Driver supporting the CCI cache coherent interconnect for ARM 56 Driver to enable ocp2scp module which transforms ocp interface
51 platforms. 57 protocol to scp protocol. In OMAP4, USB PHY is connected via
58 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
59 OCP2SCP.
52 60
53config ARM_CCN 61config SIMPLE_PM_BUS
54 bool "ARM CCN driver support" 62 bool "Simple Power-Managed Bus Driver"
55 depends on ARM || ARM64 63 depends on OF && PM
56 depends on PERF_EVENTS 64 depends on ARCH_SHMOBILE || COMPILE_TEST
57 help 65 help
58 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 66 Driver for transparent busses that don't need a real driver, but
59 interconnect. 67 where the bus controller is part of a PM domain, or under the control
68 of a functional clock, and thus relies on runtime PM for managing
69 this PM domain and/or clock.
70 An example of such a bus controller is the Renesas Bus State
71 Controller (BSC, sometimes called "LBSC within Bus Bridge", or
72 "External Bus Interface") as found on several Renesas ARM SoCs.
60 73
61config VEXPRESS_CONFIG 74config VEXPRESS_CONFIG
62 bool "Versatile Express configuration bus" 75 bool "Versatile Express configuration bus"
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 2973c18cbcc2..e023a2bec664 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -2,16 +2,17 @@
2# Makefile for the bus drivers. 2# Makefile for the bus drivers.
3# 3#
4 4
5# Interconnect bus drivers for ARM platforms
6obj-$(CONFIG_ARM_CCI) += arm-cci.o
7obj-$(CONFIG_ARM_CCN) += arm-ccn.o
8
5obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o 9obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o
6obj-$(CONFIG_IMX_WEIM) += imx-weim.o 10obj-$(CONFIG_IMX_WEIM) += imx-weim.o
7obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o 11obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
8obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
9 12
10# Interconnect bus driver for OMAP SoCs. 13# Interconnect bus driver for OMAP SoCs.
11obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o 14obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
12 15
13# Interconnect bus drivers for ARM platforms 16obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
14obj-$(CONFIG_ARM_CCI) += arm-cci.o 17obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
15obj-$(CONFIG_ARM_CCN) += arm-ccn.o
16
17obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o 18obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o
diff --git a/drivers/bus/simple-pm-bus.c b/drivers/bus/simple-pm-bus.c
new file mode 100644
index 000000000000..c5eb46cbf388
--- /dev/null
+++ b/drivers/bus/simple-pm-bus.c
@@ -0,0 +1,58 @@
1/*
2 * Simple Power-Managed Bus Driver
3 *
4 * Copyright (C) 2014-2015 Glider bvba
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/module.h>
12#include <linux/of_platform.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15
16
17static int simple_pm_bus_probe(struct platform_device *pdev)
18{
19 struct device_node *np = pdev->dev.of_node;
20
21 dev_dbg(&pdev->dev, "%s\n", __func__);
22
23 pm_runtime_enable(&pdev->dev);
24
25 if (np)
26 of_platform_populate(np, NULL, NULL, &pdev->dev);
27
28 return 0;
29}
30
31static int simple_pm_bus_remove(struct platform_device *pdev)
32{
33 dev_dbg(&pdev->dev, "%s\n", __func__);
34
35 pm_runtime_disable(&pdev->dev);
36 return 0;
37}
38
39static const struct of_device_id simple_pm_bus_of_match[] = {
40 { .compatible = "simple-pm-bus", },
41 { /* sentinel */ }
42};
43MODULE_DEVICE_TABLE(of, simple_pm_bus_of_match);
44
45static struct platform_driver simple_pm_bus_driver = {
46 .probe = simple_pm_bus_probe,
47 .remove = simple_pm_bus_remove,
48 .driver = {
49 .name = "simple-pm-bus",
50 .of_match_table = simple_pm_bus_of_match,
51 },
52};
53
54module_platform_driver(simple_pm_bus_driver);
55
56MODULE_DESCRIPTION("Simple Power-Managed Bus Driver");
57MODULE_AUTHOR("Geert Uytterhoeven <geert+renesas@glider.be>");
58MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index 0689d7fb2666..97c71c885e4f 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
2obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o 2obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
3obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o 3obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o
4obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o 4obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o
5obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
5obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o 6obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
6obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o 7obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
7obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o 8obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
diff --git a/drivers/clk/shmobile/clk-r8a7778.c b/drivers/clk/shmobile/clk-r8a7778.c
new file mode 100644
index 000000000000..cb33b57274bf
--- /dev/null
+++ b/drivers/clk/shmobile/clk-r8a7778.c
@@ -0,0 +1,143 @@
1/*
2 * r8a7778 Core CPG Clocks
3 *
4 * Copyright (C) 2014 Ulrich Hecht
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/shmobile.h>
14#include <linux/of_address.h>
15
16struct r8a7778_cpg {
17 struct clk_onecell_data data;
18 spinlock_t lock;
19 void __iomem *reg;
20};
21
22/* PLL multipliers per bits 11, 12, and 18 of MODEMR */
23struct {
24 unsigned long plla_mult;
25 unsigned long pllb_mult;
26} r8a7778_rates[] __initdata = {
27 [0] = { 21, 21 },
28 [1] = { 24, 24 },
29 [2] = { 28, 28 },
30 [3] = { 32, 32 },
31 [5] = { 24, 21 },
32 [6] = { 28, 21 },
33 [7] = { 32, 24 },
34};
35
36/* Clock dividers per bits 1 and 2 of MODEMR */
37struct {
38 const char *name;
39 unsigned int div[4];
40} r8a7778_divs[6] __initdata = {
41 { "b", { 12, 12, 16, 18 } },
42 { "out", { 12, 12, 16, 18 } },
43 { "p", { 16, 12, 16, 12 } },
44 { "s", { 4, 3, 4, 3 } },
45 { "s1", { 8, 6, 8, 6 } },
46};
47
48static u32 cpg_mode_rates __initdata;
49static u32 cpg_mode_divs __initdata;
50
51static struct clk * __init
52r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
53 const char *name)
54{
55 if (!strcmp(name, "plla")) {
56 return clk_register_fixed_factor(NULL, "plla",
57 of_clk_get_parent_name(np, 0), 0,
58 r8a7778_rates[cpg_mode_rates].plla_mult, 1);
59 } else if (!strcmp(name, "pllb")) {
60 return clk_register_fixed_factor(NULL, "pllb",
61 of_clk_get_parent_name(np, 0), 0,
62 r8a7778_rates[cpg_mode_rates].pllb_mult, 1);
63 } else {
64 unsigned int i;
65
66 for (i = 0; i < ARRAY_SIZE(r8a7778_divs); i++) {
67 if (!strcmp(name, r8a7778_divs[i].name)) {
68 return clk_register_fixed_factor(NULL,
69 r8a7778_divs[i].name,
70 "plla", 0, 1,
71 r8a7778_divs[i].div[cpg_mode_divs]);
72 }
73 }
74 }
75
76 return ERR_PTR(-EINVAL);
77}
78
79
80static void __init r8a7778_cpg_clocks_init(struct device_node *np)
81{
82 struct r8a7778_cpg *cpg;
83 struct clk **clks;
84 unsigned int i;
85 int num_clks;
86
87 num_clks = of_property_count_strings(np, "clock-output-names");
88 if (num_clks < 0) {
89 pr_err("%s: failed to count clocks\n", __func__);
90 return;
91 }
92
93 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
94 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
95 if (cpg == NULL || clks == NULL) {
96 /* We're leaking memory on purpose, there's no point in cleaning
97 * up as the system won't boot anyway.
98 */
99 return;
100 }
101
102 spin_lock_init(&cpg->lock);
103
104 cpg->data.clks = clks;
105 cpg->data.clk_num = num_clks;
106
107 cpg->reg = of_iomap(np, 0);
108 if (WARN_ON(cpg->reg == NULL))
109 return;
110
111 for (i = 0; i < num_clks; ++i) {
112 const char *name;
113 struct clk *clk;
114
115 of_property_read_string_index(np, "clock-output-names", i,
116 &name);
117
118 clk = r8a7778_cpg_register_clock(np, cpg, name);
119 if (IS_ERR(clk))
120 pr_err("%s: failed to register %s %s clock (%ld)\n",
121 __func__, np->name, name, PTR_ERR(clk));
122 else
123 cpg->data.clks[i] = clk;
124 }
125
126 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
127}
128
129CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
130 r8a7778_cpg_clocks_init);
131
132void __init r8a7778_clocks_init(u32 mode)
133{
134 BUG_ON(!(mode & BIT(19)));
135
136 cpg_mode_rates = (!!(mode & BIT(18)) << 2) |
137 (!!(mode & BIT(12)) << 1) |
138 (!!(mode & BIT(11)));
139 cpg_mode_divs = (!!(mode & BIT(2)) << 1) |
140 (!!(mode & BIT(1)));
141
142 of_clk_init(NULL);
143}
diff --git a/include/dt-bindings/clock/r8a7778-clock.h b/include/dt-bindings/clock/r8a7778-clock.h
new file mode 100644
index 000000000000..f6b07c5399de
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7778-clock.h
@@ -0,0 +1,71 @@
1/*
2 * Copyright (C) 2014 Ulrich Hecht
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_R8A7778_H__
11#define __DT_BINDINGS_CLOCK_R8A7778_H__
12
13/* CPG */
14#define R8A7778_CLK_PLLA 0
15#define R8A7778_CLK_PLLB 1
16#define R8A7778_CLK_B 2
17#define R8A7778_CLK_OUT 3
18#define R8A7778_CLK_P 4
19#define R8A7778_CLK_S 5
20#define R8A7778_CLK_S1 6
21
22/* MSTP0 */
23#define R8A7778_CLK_I2C0 30
24#define R8A7778_CLK_I2C1 29
25#define R8A7778_CLK_I2C2 28
26#define R8A7778_CLK_I2C3 27
27#define R8A7778_CLK_SCIF0 26
28#define R8A7778_CLK_SCIF1 25
29#define R8A7778_CLK_SCIF2 24
30#define R8A7778_CLK_SCIF3 23
31#define R8A7778_CLK_SCIF4 22
32#define R8A7778_CLK_SCIF5 21
33#define R8A7778_CLK_TMU0 16
34#define R8A7778_CLK_TMU1 15
35#define R8A7778_CLK_TMU2 14
36#define R8A7778_CLK_SSI0 12
37#define R8A7778_CLK_SSI1 11
38#define R8A7778_CLK_SSI2 10
39#define R8A7778_CLK_SSI3 9
40#define R8A7778_CLK_SRU 8
41#define R8A7778_CLK_HSPI 7
42
43/* MSTP1 */
44#define R8A7778_CLK_ETHER 14
45#define R8A7778_CLK_VIN0 10
46#define R8A7778_CLK_VIN1 9
47#define R8A7778_CLK_USB 0
48
49/* MSTP3 */
50#define R8A7778_CLK_MMC 31
51#define R8A7778_CLK_SDHI0 23
52#define R8A7778_CLK_SDHI1 22
53#define R8A7778_CLK_SDHI2 21
54#define R8A7778_CLK_SSI4 11
55#define R8A7778_CLK_SSI5 10
56#define R8A7778_CLK_SSI6 9
57#define R8A7778_CLK_SSI7 8
58#define R8A7778_CLK_SSI8 7
59
60/* MSTP5 */
61#define R8A7778_CLK_SRU_SRC0 31
62#define R8A7778_CLK_SRU_SRC1 30
63#define R8A7778_CLK_SRU_SRC2 29
64#define R8A7778_CLK_SRU_SRC3 28
65#define R8A7778_CLK_SRU_SRC4 27
66#define R8A7778_CLK_SRU_SRC5 26
67#define R8A7778_CLK_SRU_SRC6 25
68#define R8A7778_CLK_SRU_SRC7 24
69#define R8A7778_CLK_SRU_SRC8 23
70
71#endif /* __DT_BINDINGS_CLOCK_R8A7778_H__ */
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index 9f8a14041dd5..63a8159c4e64 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -16,6 +16,7 @@
16 16
17#include <linux/types.h> 17#include <linux/types.h>
18 18
19void r8a7778_clocks_init(u32 mode);
19void r8a7779_clocks_init(u32 mode); 20void r8a7779_clocks_init(u32 mode);
20void rcar_gen2_clocks_init(u32 mode); 21void rcar_gen2_clocks_init(u32 mode);
21 22
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-29 14:18:30 -0400