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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-08-21 17:38:08 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-08-23 08:52:36 -0400
commit35d8f2eb259e2d32c4bb67e9733ba0cba031f64f (patch)
tree690ec34175ddf88ac877e42688bc2c3c12f85e71
parente27e9708c45879f16fb824a2da94cd65e150a0c8 (diff)
drm/i915: Use POSTING_READ in lcpll code
If we don't use the return value of a mmio read our coding style is to use the POSTING_READ macro. This avoids cluttering the mmio traces. While at it add the missing posting read in the lcpll enable function that Paulo spotted. v2: Drop the _NOTRACE changes, tracing such wait_for loops in the modeset code might actually be rather useful! Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b29954ac6bfd..b4daa640a6d8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6036,13 +6036,14 @@ void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6036 if (val & LCPLL_POWER_DOWN_ALLOW) { 6036 if (val & LCPLL_POWER_DOWN_ALLOW) {
6037 val &= ~LCPLL_POWER_DOWN_ALLOW; 6037 val &= ~LCPLL_POWER_DOWN_ALLOW;
6038 I915_WRITE(LCPLL_CTL, val); 6038 I915_WRITE(LCPLL_CTL, val);
6039 POSTING_READ(LCPLL_CTL);
6039 } 6040 }
6040 6041
6041 val = I915_READ(D_COMP); 6042 val = I915_READ(D_COMP);
6042 val |= D_COMP_COMP_FORCE; 6043 val |= D_COMP_COMP_FORCE;
6043 val &= ~D_COMP_COMP_DISABLE; 6044 val &= ~D_COMP_COMP_DISABLE;
6044 I915_WRITE(D_COMP, val); 6045 I915_WRITE(D_COMP, val);
6045 I915_READ(D_COMP); 6046 POSTING_READ(D_COMP);
6046 6047
6047 val = I915_READ(LCPLL_CTL); 6048 val = I915_READ(LCPLL_CTL);
6048 val &= ~LCPLL_PLL_DISABLE; 6049 val &= ~LCPLL_PLL_DISABLE;