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authorPaul Burton <paul.burton@imgtec.com>2014-03-27 06:57:30 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-03-31 12:17:12 -0400
commit30ee615bb86ba640c9ec7f85fb95c1b0e31c41be (patch)
treeb756df1f38821bb46182fab185ebd2c4f5e0c86c
parent968a0734db05ad907bc8fffabdbe7da5e1e731f6 (diff)
MIPS: Fix core number detection for MT cores
In cores which implement the MT ASE, the CPUNum in the EBase register is a concatenation of the core number & the VPE ID within that core. In order to retrieve the correct core number CPUNum must be shifted appropriately to remove the VPE ID bits. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6666/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/kernel/cpu-probe.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index bd712c91f48b..6e8fb85ce7c3 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -23,6 +23,7 @@
23#include <asm/cpu-type.h> 23#include <asm/cpu-type.h>
24#include <asm/fpu.h> 24#include <asm/fpu.h>
25#include <asm/mipsregs.h> 25#include <asm/mipsregs.h>
26#include <asm/mipsmtregs.h>
26#include <asm/msa.h> 27#include <asm/msa.h>
27#include <asm/watch.h> 28#include <asm/watch.h>
28#include <asm/elf.h> 29#include <asm/elf.h>
@@ -421,8 +422,11 @@ static void decode_configs(struct cpuinfo_mips *c)
421 mips_probe_watch_registers(c); 422 mips_probe_watch_registers(c);
422 423
423#ifndef CONFIG_MIPS_CPS 424#ifndef CONFIG_MIPS_CPS
424 if (cpu_has_mips_r2) 425 if (cpu_has_mips_r2) {
425 c->core = read_c0_ebase() & 0x3ff; 426 c->core = read_c0_ebase() & 0x3ff;
427 if (cpu_has_mipsmt)
428 c->core >>= fls(core_nvpes()) - 1;
429 }
426#endif 430#endif
427} 431}
428 432