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authorSteve Longerbeam <slongerbeam@gmail.com>2014-08-19 13:52:40 -0400
committerPhilipp Zabel <p.zabel@pengutronix.de>2014-09-02 08:55:42 -0400
commit2ffd48f2e7ae06c3d7b2bcde9a0cb211d1a32468 (patch)
tree7969a203b7fa3c3733594aee34795b2a43e7bb16
parentc2d670fd3b16304124162bef99313eaa289f2bc3 (diff)
gpu: ipu-v3: Add Camera Sensor Interface unit
Adds the Camera Sensor Interface (CSI) unit required for video capture. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Removed the unused clk_get_rate in ipu_csi_init_interface and the ipu_csi_ccir_err_detection_enable/disable functions. Checkpatch cleanup. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat
-rw-r--r--drivers/gpu/ipu-v3/Makefile2
-rw-r--r--drivers/gpu/ipu-v3/ipu-common.c44
-rw-r--r--drivers/gpu/ipu-v3/ipu-csi.c741
-rw-r--r--drivers/gpu/ipu-v3/ipu-prv.h6
-rw-r--r--include/video/imx-ipu-v3.h32
5 files changed, 810 insertions, 15 deletions
diff --git a/drivers/gpu/ipu-v3/Makefile b/drivers/gpu/ipu-v3/Makefile
index 0b42836caae1..d22bd06caa6d 100644
--- a/drivers/gpu/ipu-v3/Makefile
+++ b/drivers/gpu/ipu-v3/Makefile
@@ -1,4 +1,4 @@
1obj-$(CONFIG_IMX_IPUV3_CORE) += imx-ipu-v3.o 1obj-$(CONFIG_IMX_IPUV3_CORE) += imx-ipu-v3.o
2 2
3imx-ipu-v3-objs := ipu-common.o ipu-cpmem.o ipu-dc.o ipu-di.o \ 3imx-ipu-v3-objs := ipu-common.o ipu-cpmem.o ipu-csi.o ipu-dc.o ipu-di.o \
4 ipu-dp.o ipu-dmfc.o ipu-smfc.o 4 ipu-dp.o ipu-dmfc.o ipu-smfc.o
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index cae543115856..511c364231a2 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -217,18 +217,6 @@ int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
217} 217}
218EXPORT_SYMBOL_GPL(ipu_module_disable); 218EXPORT_SYMBOL_GPL(ipu_module_disable);
219 219
220int ipu_csi_enable(struct ipu_soc *ipu, int csi)
221{
222 return ipu_module_enable(ipu, csi ? IPU_CONF_CSI1_EN : IPU_CONF_CSI0_EN);
223}
224EXPORT_SYMBOL_GPL(ipu_csi_enable);
225
226int ipu_csi_disable(struct ipu_soc *ipu, int csi)
227{
228 return ipu_module_disable(ipu, csi ? IPU_CONF_CSI1_EN : IPU_CONF_CSI0_EN);
229}
230EXPORT_SYMBOL_GPL(ipu_csi_disable);
231
232int ipu_smfc_enable(struct ipu_soc *ipu) 220int ipu_smfc_enable(struct ipu_soc *ipu)
233{ 221{
234 return ipu_module_enable(ipu, IPU_CONF_SMFC_EN); 222 return ipu_module_enable(ipu, IPU_CONF_SMFC_EN);
@@ -439,6 +427,8 @@ struct ipu_devtype {
439 unsigned long cpmem_ofs; 427 unsigned long cpmem_ofs;
440 unsigned long srm_ofs; 428 unsigned long srm_ofs;
441 unsigned long tpm_ofs; 429 unsigned long tpm_ofs;
430 unsigned long csi0_ofs;
431 unsigned long csi1_ofs;
442 unsigned long disp0_ofs; 432 unsigned long disp0_ofs;
443 unsigned long disp1_ofs; 433 unsigned long disp1_ofs;
444 unsigned long dc_tmpl_ofs; 434 unsigned long dc_tmpl_ofs;
@@ -452,6 +442,8 @@ static struct ipu_devtype ipu_type_imx51 = {
452 .cpmem_ofs = 0x1f000000, 442 .cpmem_ofs = 0x1f000000,
453 .srm_ofs = 0x1f040000, 443 .srm_ofs = 0x1f040000,
454 .tpm_ofs = 0x1f060000, 444 .tpm_ofs = 0x1f060000,
445 .csi0_ofs = 0x1f030000,
446 .csi1_ofs = 0x1f038000,
455 .disp0_ofs = 0x1e040000, 447 .disp0_ofs = 0x1e040000,
456 .disp1_ofs = 0x1e048000, 448 .disp1_ofs = 0x1e048000,
457 .dc_tmpl_ofs = 0x1f080000, 449 .dc_tmpl_ofs = 0x1f080000,
@@ -465,6 +457,8 @@ static struct ipu_devtype ipu_type_imx53 = {
465 .cpmem_ofs = 0x07000000, 457 .cpmem_ofs = 0x07000000,
466 .srm_ofs = 0x07040000, 458 .srm_ofs = 0x07040000,
467 .tpm_ofs = 0x07060000, 459 .tpm_ofs = 0x07060000,
460 .csi0_ofs = 0x07030000,
461 .csi1_ofs = 0x07038000,
468 .disp0_ofs = 0x06040000, 462 .disp0_ofs = 0x06040000,
469 .disp1_ofs = 0x06048000, 463 .disp1_ofs = 0x06048000,
470 .dc_tmpl_ofs = 0x07080000, 464 .dc_tmpl_ofs = 0x07080000,
@@ -478,6 +472,8 @@ static struct ipu_devtype ipu_type_imx6q = {
478 .cpmem_ofs = 0x00300000, 472 .cpmem_ofs = 0x00300000,
479 .srm_ofs = 0x00340000, 473 .srm_ofs = 0x00340000,
480 .tpm_ofs = 0x00360000, 474 .tpm_ofs = 0x00360000,
475 .csi0_ofs = 0x00230000,
476 .csi1_ofs = 0x00238000,
481 .disp0_ofs = 0x00240000, 477 .disp0_ofs = 0x00240000,
482 .disp1_ofs = 0x00248000, 478 .disp1_ofs = 0x00248000,
483 .dc_tmpl_ofs = 0x00380000, 479 .dc_tmpl_ofs = 0x00380000,
@@ -508,6 +504,20 @@ static int ipu_submodules_init(struct ipu_soc *ipu,
508 goto err_cpmem; 504 goto err_cpmem;
509 } 505 }
510 506
507 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
508 IPU_CONF_CSI0_EN, ipu_clk);
509 if (ret) {
510 unit = "csi0";
511 goto err_csi_0;
512 }
513
514 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
515 IPU_CONF_CSI1_EN, ipu_clk);
516 if (ret) {
517 unit = "csi1";
518 goto err_csi_1;
519 }
520
511 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, 521 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
512 IPU_CONF_DI0_EN, ipu_clk); 522 IPU_CONF_DI0_EN, ipu_clk);
513 if (ret) { 523 if (ret) {
@@ -562,6 +572,10 @@ err_dc:
562err_di_1: 572err_di_1:
563 ipu_di_exit(ipu, 0); 573 ipu_di_exit(ipu, 0);
564err_di_0: 574err_di_0:
575 ipu_csi_exit(ipu, 1);
576err_csi_1:
577 ipu_csi_exit(ipu, 0);
578err_csi_0:
565 ipu_cpmem_exit(ipu); 579 ipu_cpmem_exit(ipu);
566err_cpmem: 580err_cpmem:
567 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret); 581 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
@@ -640,6 +654,8 @@ static void ipu_submodules_exit(struct ipu_soc *ipu)
640 ipu_dc_exit(ipu); 654 ipu_dc_exit(ipu);
641 ipu_di_exit(ipu, 1); 655 ipu_di_exit(ipu, 1);
642 ipu_di_exit(ipu, 0); 656 ipu_di_exit(ipu, 0);
657 ipu_csi_exit(ipu, 1);
658 ipu_csi_exit(ipu, 0);
643 ipu_cpmem_exit(ipu); 659 ipu_cpmem_exit(ipu);
644} 660}
645 661
@@ -859,6 +875,10 @@ static int ipu_probe(struct platform_device *pdev)
859 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS); 875 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
860 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n", 876 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
861 ipu_base + devtype->cpmem_ofs); 877 ipu_base + devtype->cpmem_ofs);
878 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
879 ipu_base + devtype->csi0_ofs);
880 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
881 ipu_base + devtype->csi1_ofs);
862 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n", 882 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
863 ipu_base + devtype->disp0_ofs); 883 ipu_base + devtype->disp0_ofs);
864 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n", 884 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c
new file mode 100644
index 000000000000..d6f56471bd2a
--- /dev/null
+++ b/drivers/gpu/ipu-v3/ipu-csi.c
@@ -0,0 +1,741 @@
1/*
2 * Copyright (C) 2012-2014 Mentor Graphics Inc.
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15#include <linux/export.h>
16#include <linux/module.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/delay.h>
20#include <linux/io.h>
21#include <linux/err.h>
22#include <linux/platform_device.h>
23#include <linux/videodev2.h>
24#include <uapi/linux/v4l2-mediabus.h>
25#include <linux/clk.h>
26#include <linux/clk-provider.h>
27#include <linux/clkdev.h>
28
29#include "ipu-prv.h"
30
31struct ipu_csi {
32 void __iomem *base;
33 int id;
34 u32 module;
35 struct clk *clk_ipu; /* IPU bus clock */
36 spinlock_t lock;
37 bool inuse;
38 struct ipu_soc *ipu;
39};
40
41/* CSI Register Offsets */
42#define CSI_SENS_CONF 0x0000
43#define CSI_SENS_FRM_SIZE 0x0004
44#define CSI_ACT_FRM_SIZE 0x0008
45#define CSI_OUT_FRM_CTRL 0x000c
46#define CSI_TST_CTRL 0x0010
47#define CSI_CCIR_CODE_1 0x0014
48#define CSI_CCIR_CODE_2 0x0018
49#define CSI_CCIR_CODE_3 0x001c
50#define CSI_MIPI_DI 0x0020
51#define CSI_SKIP 0x0024
52#define CSI_CPD_CTRL 0x0028
53#define CSI_CPD_RC(n) (0x002c + ((n)*4))
54#define CSI_CPD_RS(n) (0x004c + ((n)*4))
55#define CSI_CPD_GRC(n) (0x005c + ((n)*4))
56#define CSI_CPD_GRS(n) (0x007c + ((n)*4))
57#define CSI_CPD_GBC(n) (0x008c + ((n)*4))
58#define CSI_CPD_GBS(n) (0x00Ac + ((n)*4))
59#define CSI_CPD_BC(n) (0x00Bc + ((n)*4))
60#define CSI_CPD_BS(n) (0x00Dc + ((n)*4))
61#define CSI_CPD_OFFSET1 0x00ec
62#define CSI_CPD_OFFSET2 0x00f0
63
64/* CSI Register Fields */
65#define CSI_SENS_CONF_DATA_FMT_SHIFT 8
66#define CSI_SENS_CONF_DATA_FMT_MASK 0x00000700
67#define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 0L
68#define CSI_SENS_CONF_DATA_FMT_YUV422_YUYV 1L
69#define CSI_SENS_CONF_DATA_FMT_YUV422_UYVY 2L
70#define CSI_SENS_CONF_DATA_FMT_BAYER 3L
71#define CSI_SENS_CONF_DATA_FMT_RGB565 4L
72#define CSI_SENS_CONF_DATA_FMT_RGB555 5L
73#define CSI_SENS_CONF_DATA_FMT_RGB444 6L
74#define CSI_SENS_CONF_DATA_FMT_JPEG 7L
75
76#define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
77#define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
78#define CSI_SENS_CONF_DATA_POL_SHIFT 2
79#define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
80#define CSI_SENS_CONF_SENS_PRTCL_MASK 0x00000070
81#define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
82#define CSI_SENS_CONF_PACK_TIGHT_SHIFT 7
83#define CSI_SENS_CONF_DATA_WIDTH_SHIFT 11
84#define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
85#define CSI_SENS_CONF_DIVRATIO_SHIFT 16
86
87#define CSI_SENS_CONF_DIVRATIO_MASK 0x00ff0000
88#define CSI_SENS_CONF_DATA_DEST_SHIFT 24
89#define CSI_SENS_CONF_DATA_DEST_MASK 0x07000000
90#define CSI_SENS_CONF_JPEG8_EN_SHIFT 27
91#define CSI_SENS_CONF_JPEG_EN_SHIFT 28
92#define CSI_SENS_CONF_FORCE_EOF_SHIFT 29
93#define CSI_SENS_CONF_DATA_EN_POL_SHIFT 31
94
95#define CSI_DATA_DEST_IC 2
96#define CSI_DATA_DEST_IDMAC 4
97
98#define CSI_CCIR_ERR_DET_EN 0x01000000
99#define CSI_HORI_DOWNSIZE_EN 0x80000000
100#define CSI_VERT_DOWNSIZE_EN 0x40000000
101#define CSI_TEST_GEN_MODE_EN 0x01000000
102
103#define CSI_HSC_MASK 0x1fff0000
104#define CSI_HSC_SHIFT 16
105#define CSI_VSC_MASK 0x00000fff
106#define CSI_VSC_SHIFT 0
107
108#define CSI_TEST_GEN_R_MASK 0x000000ff
109#define CSI_TEST_GEN_R_SHIFT 0
110#define CSI_TEST_GEN_G_MASK 0x0000ff00
111#define CSI_TEST_GEN_G_SHIFT 8
112#define CSI_TEST_GEN_B_MASK 0x00ff0000
113#define CSI_TEST_GEN_B_SHIFT 16
114
115#define CSI_MAX_RATIO_SKIP_SMFC_MASK 0x00000007
116#define CSI_MAX_RATIO_SKIP_SMFC_SHIFT 0
117#define CSI_SKIP_SMFC_MASK 0x000000f8
118#define CSI_SKIP_SMFC_SHIFT 3
119#define CSI_ID_2_SKIP_MASK 0x00000300
120#define CSI_ID_2_SKIP_SHIFT 8
121
122#define CSI_COLOR_FIRST_ROW_MASK 0x00000002
123#define CSI_COLOR_FIRST_COMP_MASK 0x00000001
124
125/* MIPI CSI-2 data types */
126#define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */
127#define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */
128#define MIPI_DT_YUV422 0x1e /* UYVY... */
129#define MIPI_DT_RGB444 0x20
130#define MIPI_DT_RGB555 0x21
131#define MIPI_DT_RGB565 0x22
132#define MIPI_DT_RGB666 0x23
133#define MIPI_DT_RGB888 0x24
134#define MIPI_DT_RAW6 0x28
135#define MIPI_DT_RAW7 0x29
136#define MIPI_DT_RAW8 0x2a
137#define MIPI_DT_RAW10 0x2b
138#define MIPI_DT_RAW12 0x2c
139#define MIPI_DT_RAW14 0x2d
140
141/*
142 * Bitfield of CSI bus signal polarities and modes.
143 */
144struct ipu_csi_bus_config {
145 unsigned data_width:4;
146 unsigned clk_mode:3;
147 unsigned ext_vsync:1;
148 unsigned vsync_pol:1;
149 unsigned hsync_pol:1;
150 unsigned pixclk_pol:1;
151 unsigned data_pol:1;
152 unsigned sens_clksrc:1;
153 unsigned pack_tight:1;
154 unsigned force_eof:1;
155 unsigned data_en_pol:1;
156
157 unsigned data_fmt;
158 unsigned mipi_dt;
159};
160
161/*
162 * Enumeration of CSI data bus widths.
163 */
164enum ipu_csi_data_width {
165 IPU_CSI_DATA_WIDTH_4 = 0,
166 IPU_CSI_DATA_WIDTH_8 = 1,
167 IPU_CSI_DATA_WIDTH_10 = 3,
168 IPU_CSI_DATA_WIDTH_12 = 5,
169 IPU_CSI_DATA_WIDTH_16 = 9,
170};
171
172/*
173 * Enumeration of CSI clock modes.
174 */
175enum ipu_csi_clk_mode {
176 IPU_CSI_CLK_MODE_GATED_CLK,
177 IPU_CSI_CLK_MODE_NONGATED_CLK,
178 IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
179 IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
180 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
181 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
182 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
183 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
184};
185
186static inline u32 ipu_csi_read(struct ipu_csi *csi, unsigned offset)
187{
188 return readl(csi->base + offset);
189}
190
191static inline void ipu_csi_write(struct ipu_csi *csi, u32 value,
192 unsigned offset)
193{
194 writel(value, csi->base + offset);
195}
196
197/*
198 * Set mclk division ratio for generating test mode mclk. Only used
199 * for test generator.
200 */
201static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk,
202 u32 ipu_clk)
203{
204 u32 temp;
205 u32 div_ratio;
206
207 div_ratio = (ipu_clk / pixel_clk) - 1;
208
209 if (div_ratio > 0xFF || div_ratio < 0) {
210 dev_err(csi->ipu->dev,
211 "value of pixel_clk extends normal range\n");
212 return -EINVAL;
213 }
214
215 temp = ipu_csi_read(csi, CSI_SENS_CONF);
216 temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
217 ipu_csi_write(csi, temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
218 CSI_SENS_CONF);
219
220 return 0;
221}
222
223/*
224 * Find the CSI data format and data width for the given V4L2 media
225 * bus pixel format code.
226 */
227static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code)
228{
229 switch (mbus_code) {
230 case V4L2_MBUS_FMT_BGR565_2X8_BE:
231 case V4L2_MBUS_FMT_BGR565_2X8_LE:
232 case V4L2_MBUS_FMT_RGB565_2X8_BE:
233 case V4L2_MBUS_FMT_RGB565_2X8_LE:
234 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
235 cfg->mipi_dt = MIPI_DT_RGB565;
236 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
237 break;
238 case V4L2_MBUS_FMT_RGB444_2X8_PADHI_BE:
239 case V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE:
240 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB444;
241 cfg->mipi_dt = MIPI_DT_RGB444;
242 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
243 break;
244 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE:
245 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
246 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
247 cfg->mipi_dt = MIPI_DT_RGB555;
248 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
249 break;
250 case V4L2_MBUS_FMT_UYVY8_2X8:
251 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
252 cfg->mipi_dt = MIPI_DT_YUV422;
253 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
254 break;
255 case V4L2_MBUS_FMT_YUYV8_2X8:
256 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
257 cfg->mipi_dt = MIPI_DT_YUV422;
258 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
259 break;
260 case V4L2_MBUS_FMT_UYVY8_1X16:
261 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
262 cfg->mipi_dt = MIPI_DT_YUV422;
263 cfg->data_width = IPU_CSI_DATA_WIDTH_16;
264 break;
265 case V4L2_MBUS_FMT_YUYV8_1X16:
266 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
267 cfg->mipi_dt = MIPI_DT_YUV422;
268 cfg->data_width = IPU_CSI_DATA_WIDTH_16;
269 break;
270 case V4L2_MBUS_FMT_SBGGR8_1X8:
271 case V4L2_MBUS_FMT_SGBRG8_1X8:
272 case V4L2_MBUS_FMT_SGRBG8_1X8:
273 case V4L2_MBUS_FMT_SRGGB8_1X8:
274 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
275 cfg->mipi_dt = MIPI_DT_RAW8;
276 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
277 break;
278 case V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8:
279 case V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8:
280 case V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8:
281 case V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8:
282 case V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE:
283 case V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE:
284 case V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE:
285 case V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE:
286 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
287 cfg->mipi_dt = MIPI_DT_RAW10;
288 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
289 break;
290 case V4L2_MBUS_FMT_SBGGR10_1X10:
291 case V4L2_MBUS_FMT_SGBRG10_1X10:
292 case V4L2_MBUS_FMT_SGRBG10_1X10:
293 case V4L2_MBUS_FMT_SRGGB10_1X10:
294 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
295 cfg->mipi_dt = MIPI_DT_RAW10;
296 cfg->data_width = IPU_CSI_DATA_WIDTH_10;
297 break;
298 case V4L2_MBUS_FMT_SBGGR12_1X12:
299 case V4L2_MBUS_FMT_SGBRG12_1X12:
300 case V4L2_MBUS_FMT_SGRBG12_1X12:
301 case V4L2_MBUS_FMT_SRGGB12_1X12:
302 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
303 cfg->mipi_dt = MIPI_DT_RAW12;
304 cfg->data_width = IPU_CSI_DATA_WIDTH_12;
305 break;
306 case V4L2_MBUS_FMT_JPEG_1X8:
307 /* TODO */
308 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_JPEG;
309 cfg->mipi_dt = MIPI_DT_RAW8;
310 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
311 break;
312 default:
313 return -EINVAL;
314 }
315
316 return 0;
317}
318
319/*
320 * Fill a CSI bus config struct from mbus_config and mbus_framefmt.
321 */
322static void fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg,
323 struct v4l2_mbus_config *mbus_cfg,
324 struct v4l2_mbus_framefmt *mbus_fmt)
325{
326 memset(csicfg, 0, sizeof(*csicfg));
327
328 mbus_code_to_bus_cfg(csicfg, mbus_fmt->code);
329
330 switch (mbus_cfg->type) {
331 case V4L2_MBUS_PARALLEL:
332 csicfg->ext_vsync = 1;
333 csicfg->vsync_pol = (mbus_cfg->flags &
334 V4L2_MBUS_VSYNC_ACTIVE_LOW) ? 1 : 0;
335 csicfg->hsync_pol = (mbus_cfg->flags &
336 V4L2_MBUS_HSYNC_ACTIVE_LOW) ? 1 : 0;
337 csicfg->pixclk_pol = (mbus_cfg->flags &
338 V4L2_MBUS_PCLK_SAMPLE_FALLING) ? 1 : 0;
339 csicfg->clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
340 break;
341 case V4L2_MBUS_BT656:
342 csicfg->ext_vsync = 0;
343 if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field))
344 csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
345 else
346 csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
347 break;
348 case V4L2_MBUS_CSI2:
349 /*
350 * MIPI CSI-2 requires non gated clock mode, all other
351 * parameters are not applicable for MIPI CSI-2 bus.
352 */
353 csicfg->clk_mode = IPU_CSI_CLK_MODE_NONGATED_CLK;
354 break;
355 default:
356 /* will never get here, keep compiler quiet */
357 break;
358 }
359}
360
361int ipu_csi_init_interface(struct ipu_csi *csi,
362 struct v4l2_mbus_config *mbus_cfg,
363 struct v4l2_mbus_framefmt *mbus_fmt)
364{
365 struct ipu_csi_bus_config cfg;
366 unsigned long flags;
367 u32 data = 0;
368
369 fill_csi_bus_cfg(&cfg, mbus_cfg, mbus_fmt);
370
371 /* Set the CSI_SENS_CONF register remaining fields */
372 data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
373 cfg.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
374 cfg.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
375 cfg.vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
376 cfg.hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
377 cfg.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
378 cfg.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
379 cfg.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
380 cfg.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
381 cfg.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
382 cfg.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
383
384 spin_lock_irqsave(&csi->lock, flags);
385
386 ipu_csi_write(csi, data, CSI_SENS_CONF);
387
388 /* Setup sensor frame size */
389 ipu_csi_write(csi,
390 (mbus_fmt->width - 1) | ((mbus_fmt->height - 1) << 16),
391 CSI_SENS_FRM_SIZE);
392
393 /* Set CCIR registers */
394
395 switch (cfg.clk_mode) {
396 case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
397 ipu_csi_write(csi, 0x40030, CSI_CCIR_CODE_1);
398 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
399 break;
400 case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
401 if (mbus_fmt->width == 720 && mbus_fmt->height == 576) {
402 /*
403 * PAL case
404 *
405 * Field0BlankEnd = 0x6, Field0BlankStart = 0x2,
406 * Field0ActiveEnd = 0x4, Field0ActiveStart = 0
407 * Field1BlankEnd = 0x7, Field1BlankStart = 0x3,
408 * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1
409 */
410 ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN,
411 CSI_CCIR_CODE_1);
412 ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2);
413 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
414
415 } else if (mbus_fmt->width == 720 && mbus_fmt->height == 480) {
416 /*
417 * NTSC case
418 *
419 * Field0BlankEnd = 0x7, Field0BlankStart = 0x3,
420 * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1
421 * Field1BlankEnd = 0x6, Field1BlankStart = 0x2,
422 * Field1ActiveEnd = 0x4, Field1ActiveStart = 0
423 */
424 ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
425 CSI_CCIR_CODE_1);
426 ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
427 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
428 } else {
429 dev_err(csi->ipu->dev,
430 "Unsupported CCIR656 interlaced video mode\n");
431 spin_unlock_irqrestore(&csi->lock, flags);
432 return -EINVAL;
433 }
434 break;
435 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
436 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
437 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
438 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
439 ipu_csi_write(csi, 0x40030 | CSI_CCIR_ERR_DET_EN,
440 CSI_CCIR_CODE_1);
441 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
442 break;
443 case IPU_CSI_CLK_MODE_GATED_CLK:
444 case IPU_CSI_CLK_MODE_NONGATED_CLK:
445 ipu_csi_write(csi, 0, CSI_CCIR_CODE_1);
446 break;
447 }
448
449 dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
450 ipu_csi_read(csi, CSI_SENS_CONF));
451 dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
452 ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
453
454 spin_unlock_irqrestore(&csi->lock, flags);
455
456 return 0;
457}
458EXPORT_SYMBOL_GPL(ipu_csi_init_interface);
459
460bool ipu_csi_is_interlaced(struct ipu_csi *csi)
461{
462 unsigned long flags;
463 u32 sensor_protocol;
464
465 spin_lock_irqsave(&csi->lock, flags);
466 sensor_protocol =
467 (ipu_csi_read(csi, CSI_SENS_CONF) &
468 CSI_SENS_CONF_SENS_PRTCL_MASK) >>
469 CSI_SENS_CONF_SENS_PRTCL_SHIFT;
470 spin_unlock_irqrestore(&csi->lock, flags);
471
472 switch (sensor_protocol) {
473 case IPU_CSI_CLK_MODE_GATED_CLK:
474 case IPU_CSI_CLK_MODE_NONGATED_CLK:
475 case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
476 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
477 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
478 return false;
479 case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
480 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
481 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
482 return true;
483 default:
484 dev_err(csi->ipu->dev,
485 "CSI %d sensor protocol unsupported\n", csi->id);
486 return false;
487 }
488}
489EXPORT_SYMBOL_GPL(ipu_csi_is_interlaced);
490
491void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w)
492{
493 unsigned long flags;
494 u32 reg;
495
496 spin_lock_irqsave(&csi->lock, flags);
497
498 reg = ipu_csi_read(csi, CSI_ACT_FRM_SIZE);
499 w->width = (reg & 0xFFFF) + 1;
500 w->height = (reg >> 16 & 0xFFFF) + 1;
501
502 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
503 w->left = (reg & CSI_HSC_MASK) >> CSI_HSC_SHIFT;
504 w->top = (reg & CSI_VSC_MASK) >> CSI_VSC_SHIFT;
505
506 spin_unlock_irqrestore(&csi->lock, flags);
507}
508EXPORT_SYMBOL_GPL(ipu_csi_get_window);
509
510void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w)
511{
512 unsigned long flags;
513 u32 reg;
514
515 spin_lock_irqsave(&csi->lock, flags);
516
517 ipu_csi_write(csi, (w->width - 1) | ((w->height - 1) << 16),
518 CSI_ACT_FRM_SIZE);
519
520 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
521 reg &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
522 reg |= ((w->top << CSI_VSC_SHIFT) | (w->left << CSI_HSC_SHIFT));
523 ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
524
525 spin_unlock_irqrestore(&csi->lock, flags);
526}
527EXPORT_SYMBOL_GPL(ipu_csi_set_window);
528
529void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
530 u32 r_value, u32 g_value, u32 b_value,
531 u32 pix_clk)
532{
533 unsigned long flags;
534 u32 ipu_clk = clk_get_rate(csi->clk_ipu);
535 u32 temp;
536
537 spin_lock_irqsave(&csi->lock, flags);
538
539 temp = ipu_csi_read(csi, CSI_TST_CTRL);
540
541 if (active == false) {
542 temp &= ~CSI_TEST_GEN_MODE_EN;
543 ipu_csi_write(csi, temp, CSI_TST_CTRL);
544 } else {
545 /* Set sensb_mclk div_ratio */
546 ipu_csi_set_testgen_mclk(csi, pix_clk, ipu_clk);
547
548 temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
549 CSI_TEST_GEN_B_MASK);
550 temp |= CSI_TEST_GEN_MODE_EN;
551 temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
552 (g_value << CSI_TEST_GEN_G_SHIFT) |
553 (b_value << CSI_TEST_GEN_B_SHIFT);
554 ipu_csi_write(csi, temp, CSI_TST_CTRL);
555 }
556
557 spin_unlock_irqrestore(&csi->lock, flags);
558}
559EXPORT_SYMBOL_GPL(ipu_csi_set_test_generator);
560
561int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
562 struct v4l2_mbus_framefmt *mbus_fmt)
563{
564 struct ipu_csi_bus_config cfg;
565 unsigned long flags;
566 u32 temp;
567
568 if (vc > 3)
569 return -EINVAL;
570
571 mbus_code_to_bus_cfg(&cfg, mbus_fmt->code);
572
573 spin_lock_irqsave(&csi->lock, flags);
574
575 temp = ipu_csi_read(csi, CSI_MIPI_DI);
576 temp &= ~(0xff << (vc * 8));
577 temp |= (cfg.mipi_dt << (vc * 8));
578 ipu_csi_write(csi, temp, CSI_MIPI_DI);
579
580 spin_unlock_irqrestore(&csi->lock, flags);
581
582 return 0;
583}
584EXPORT_SYMBOL_GPL(ipu_csi_set_mipi_datatype);
585
586int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
587 u32 max_ratio, u32 id)
588{
589 unsigned long flags;
590 u32 temp;
591
592 if (max_ratio > 5 || id > 3)
593 return -EINVAL;
594
595 spin_lock_irqsave(&csi->lock, flags);
596
597 temp = ipu_csi_read(csi, CSI_SKIP);
598 temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
599 CSI_SKIP_SMFC_MASK);
600 temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
601 (id << CSI_ID_2_SKIP_SHIFT) |
602 (skip << CSI_SKIP_SMFC_SHIFT);
603 ipu_csi_write(csi, temp, CSI_SKIP);
604
605 spin_unlock_irqrestore(&csi->lock, flags);
606
607 return 0;
608}
609EXPORT_SYMBOL_GPL(ipu_csi_set_skip_smfc);
610
611int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest)
612{
613 unsigned long flags;
614 u32 csi_sens_conf, dest;
615
616 if (csi_dest == IPU_CSI_DEST_IDMAC)
617 dest = CSI_DATA_DEST_IDMAC;
618 else
619 dest = CSI_DATA_DEST_IC; /* IC or VDIC */
620
621 spin_lock_irqsave(&csi->lock, flags);
622
623 csi_sens_conf = ipu_csi_read(csi, CSI_SENS_CONF);
624 csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
625 csi_sens_conf |= (dest << CSI_SENS_CONF_DATA_DEST_SHIFT);
626 ipu_csi_write(csi, csi_sens_conf, CSI_SENS_CONF);
627
628 spin_unlock_irqrestore(&csi->lock, flags);
629
630 return 0;
631}
632EXPORT_SYMBOL_GPL(ipu_csi_set_dest);
633
634int ipu_csi_enable(struct ipu_csi *csi)
635{
636 ipu_module_enable(csi->ipu, csi->module);
637
638 return 0;
639}
640EXPORT_SYMBOL_GPL(ipu_csi_enable);
641
642int ipu_csi_disable(struct ipu_csi *csi)
643{
644 ipu_module_disable(csi->ipu, csi->module);
645
646 return 0;
647}
648EXPORT_SYMBOL_GPL(ipu_csi_disable);
649
650struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id)
651{
652 unsigned long flags;
653 struct ipu_csi *csi, *ret;
654
655 if (id > 1)
656 return ERR_PTR(-EINVAL);
657
658 csi = ipu->csi_priv[id];
659 ret = csi;
660
661 spin_lock_irqsave(&csi->lock, flags);
662
663 if (csi->inuse) {
664 ret = ERR_PTR(-EBUSY);
665 goto unlock;
666 }
667
668 csi->inuse = true;
669unlock:
670 spin_unlock_irqrestore(&csi->lock, flags);
671 return ret;
672}
673EXPORT_SYMBOL_GPL(ipu_csi_get);
674
675void ipu_csi_put(struct ipu_csi *csi)
676{
677 unsigned long flags;
678
679 spin_lock_irqsave(&csi->lock, flags);
680 csi->inuse = false;
681 spin_unlock_irqrestore(&csi->lock, flags);
682}
683EXPORT_SYMBOL_GPL(ipu_csi_put);
684
685int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
686 unsigned long base, u32 module, struct clk *clk_ipu)
687{
688 struct ipu_csi *csi;
689
690 if (id > 1)
691 return -ENODEV;
692
693 csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL);
694 if (!csi)
695 return -ENOMEM;
696
697 ipu->csi_priv[id] = csi;
698
699 spin_lock_init(&csi->lock);
700 csi->module = module;
701 csi->id = id;
702 csi->clk_ipu = clk_ipu;
703 csi->base = devm_ioremap(dev, base, PAGE_SIZE);
704 if (!csi->base)
705 return -ENOMEM;
706
707 dev_dbg(dev, "CSI%d base: 0x%08lx remapped to %p\n",
708 id, base, csi->base);
709 csi->ipu = ipu;
710
711 return 0;
712}
713
714void ipu_csi_exit(struct ipu_soc *ipu, int id)
715{
716}
717
718void ipu_csi_dump(struct ipu_csi *csi)
719{
720 dev_dbg(csi->ipu->dev, "CSI_SENS_CONF: %08x\n",
721 ipu_csi_read(csi, CSI_SENS_CONF));
722 dev_dbg(csi->ipu->dev, "CSI_SENS_FRM_SIZE: %08x\n",
723 ipu_csi_read(csi, CSI_SENS_FRM_SIZE));
724 dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE: %08x\n",
725 ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
726 dev_dbg(csi->ipu->dev, "CSI_OUT_FRM_CTRL: %08x\n",
727 ipu_csi_read(csi, CSI_OUT_FRM_CTRL));
728 dev_dbg(csi->ipu->dev, "CSI_TST_CTRL: %08x\n",
729 ipu_csi_read(csi, CSI_TST_CTRL));
730 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_1: %08x\n",
731 ipu_csi_read(csi, CSI_CCIR_CODE_1));
732 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_2: %08x\n",
733 ipu_csi_read(csi, CSI_CCIR_CODE_2));
734 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_3: %08x\n",
735 ipu_csi_read(csi, CSI_CCIR_CODE_3));
736 dev_dbg(csi->ipu->dev, "CSI_MIPI_DI: %08x\n",
737 ipu_csi_read(csi, CSI_MIPI_DI));
738 dev_dbg(csi->ipu->dev, "CSI_SKIP: %08x\n",
739 ipu_csi_read(csi, CSI_SKIP));
740}
741EXPORT_SYMBOL_GPL(ipu_csi_dump);
diff --git a/drivers/gpu/ipu-v3/ipu-prv.h b/drivers/gpu/ipu-v3/ipu-prv.h
index 1a5c55c05fe8..9b274f1259e1 100644
--- a/drivers/gpu/ipu-v3/ipu-prv.h
+++ b/drivers/gpu/ipu-v3/ipu-prv.h
@@ -157,6 +157,7 @@ struct ipuv3_channel {
157}; 157};
158 158
159struct ipu_cpmem; 159struct ipu_cpmem;
160struct ipu_csi;
160struct ipu_dc_priv; 161struct ipu_dc_priv;
161struct ipu_dmfc_priv; 162struct ipu_dmfc_priv;
162struct ipu_di; 163struct ipu_di;
@@ -189,6 +190,7 @@ struct ipu_soc {
189 struct ipu_dp_priv *dp_priv; 190 struct ipu_dp_priv *dp_priv;
190 struct ipu_dmfc_priv *dmfc_priv; 191 struct ipu_dmfc_priv *dmfc_priv;
191 struct ipu_di *di_priv[2]; 192 struct ipu_di *di_priv[2];
193 struct ipu_csi *csi_priv[2];
192 struct ipu_smfc_priv *smfc_priv; 194 struct ipu_smfc_priv *smfc_priv;
193}; 195};
194 196
@@ -211,6 +213,10 @@ int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
211bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno); 213bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
212int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms); 214int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms);
213 215
216int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
217 unsigned long base, u32 module, struct clk *clk_ipu);
218void ipu_csi_exit(struct ipu_soc *ipu, int id);
219
214int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id, 220int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
215 unsigned long base, u32 module, struct clk *ipu_clk); 221 unsigned long base, u32 module, struct clk *ipu_clk);
216void ipu_di_exit(struct ipu_soc *ipu, int id); 222void ipu_di_exit(struct ipu_soc *ipu, int id);
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index f80fe13b0d4d..6d254275192b 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -16,6 +16,7 @@
16#include <linux/videodev2.h> 16#include <linux/videodev2.h>
17#include <linux/bitmap.h> 17#include <linux/bitmap.h>
18#include <linux/fb.h> 18#include <linux/fb.h>
19#include <media/v4l2-mediabus.h>
19 20
20struct ipu_soc; 21struct ipu_soc;
21 22
@@ -61,6 +62,15 @@ struct ipu_di_signal_cfg {
61 u8 vsync_pin; 62 u8 vsync_pin;
62}; 63};
63 64
65/*
66 * Enumeration of CSI destinations
67 */
68enum ipu_csi_dest {
69 IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
70 IPU_CSI_DEST_IC, /* to Image Converter */
71 IPU_CSI_DEST_VDIC, /* to VDIC */
72};
73
64enum ipu_color_space { 74enum ipu_color_space {
65 IPUV3_COLORSPACE_RGB, 75 IPUV3_COLORSPACE_RGB,
66 IPUV3_COLORSPACE_YUV, 76 IPUV3_COLORSPACE_YUV,
@@ -211,8 +221,26 @@ int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
211/* 221/*
212 * IPU CMOS Sensor Interface (csi) functions 222 * IPU CMOS Sensor Interface (csi) functions
213 */ 223 */
214int ipu_csi_enable(struct ipu_soc *ipu, int csi); 224struct ipu_csi;
215int ipu_csi_disable(struct ipu_soc *ipu, int csi); 225int ipu_csi_init_interface(struct ipu_csi *csi,
226 struct v4l2_mbus_config *mbus_cfg,
227 struct v4l2_mbus_framefmt *mbus_fmt);
228bool ipu_csi_is_interlaced(struct ipu_csi *csi);
229void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
230void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
231void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
232 u32 r_value, u32 g_value, u32 b_value,
233 u32 pix_clk);
234int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
235 struct v4l2_mbus_framefmt *mbus_fmt);
236int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
237 u32 max_ratio, u32 id);
238int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
239int ipu_csi_enable(struct ipu_csi *csi);
240int ipu_csi_disable(struct ipu_csi *csi);
241struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
242void ipu_csi_put(struct ipu_csi *csi);
243void ipu_csi_dump(struct ipu_csi *csi);
216 244
217/* 245/*
218 * IPU Sensor Multiple FIFO Controller (SMFC) functions 246 * IPU Sensor Multiple FIFO Controller (SMFC) functions
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 05:19:46 -0500