diff options
| author | Thomas Renninger <trenn@suse.de> | 2012-01-25 18:09:11 -0500 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2012-01-26 19:49:06 -0500 |
| commit | 2f1e097e24defe64a86535b53768f5c8ab0368d1 (patch) | |
| tree | 5cd1f24fee1bc44f665983c574ddca339b2e18e0 | |
| parent | 9b38096fde5f9b93c3657911c3be7892cc155cbd (diff) | |
X86: Introduce HW-Pstate scattered cpuid feature
It is rather similar to CPB (boot capability) feature
and exists since fam10h (can be looked up in AMD's BKDG).
The feature is needed for powernow-k8 to cleanup init functions and to
provide proper autoloading matching with the new x86cpu modalias
feature.
Cc: Kay Sievers <kay.sievers@vrfy.org>
Cc: Dave Jones <davej@redhat.com>
Cc: Borislav Petkov <bp@amd64.org>
Signed-off-by: Thomas Renninger <trenn@suse.de>
Acked-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| -rw-r--r-- | arch/x86/include/asm/cpufeature.h | 1 | ||||
| -rw-r--r-- | arch/x86/kernel/cpu/scattered.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 17c5d4bdee5e..67b0910ebbb8 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h | |||
| @@ -176,6 +176,7 @@ | |||
| 176 | #define X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */ | 176 | #define X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */ |
| 177 | #define X86_FEATURE_PTS (7*32+ 6) /* Intel Package Thermal Status */ | 177 | #define X86_FEATURE_PTS (7*32+ 6) /* Intel Package Thermal Status */ |
| 178 | #define X86_FEATURE_DTS (7*32+ 7) /* Digital Thermal Sensor */ | 178 | #define X86_FEATURE_DTS (7*32+ 7) /* Digital Thermal Sensor */ |
| 179 | #define X86_FEATURE_HW_PSTATE (7*32+ 8) /* AMD HW-PState */ | ||
| 179 | 180 | ||
| 180 | /* Virtualization flags: Linux defined, word 8 */ | 181 | /* Virtualization flags: Linux defined, word 8 */ |
| 181 | #define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ | 182 | #define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ |
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index c7f64e6f537a..addf9e82a7f2 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c | |||
| @@ -40,6 +40,7 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c) | |||
| 40 | { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 }, | 40 | { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 }, |
| 41 | { X86_FEATURE_XSAVEOPT, CR_EAX, 0, 0x0000000d, 1 }, | 41 | { X86_FEATURE_XSAVEOPT, CR_EAX, 0, 0x0000000d, 1 }, |
| 42 | { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 }, | 42 | { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 }, |
| 43 | { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 }, | ||
| 43 | { X86_FEATURE_NPT, CR_EDX, 0, 0x8000000a, 0 }, | 44 | { X86_FEATURE_NPT, CR_EDX, 0, 0x8000000a, 0 }, |
| 44 | { X86_FEATURE_LBRV, CR_EDX, 1, 0x8000000a, 0 }, | 45 | { X86_FEATURE_LBRV, CR_EDX, 1, 0x8000000a, 0 }, |
| 45 | { X86_FEATURE_SVML, CR_EDX, 2, 0x8000000a, 0 }, | 46 | { X86_FEATURE_SVML, CR_EDX, 2, 0x8000000a, 0 }, |