diff options
author | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2014-01-24 17:33:16 -0500 |
---|---|---|
committer | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2014-02-25 15:16:14 -0500 |
commit | 2c4b229bafcfb0bac1ae3489c2e541bddfba8455 (patch) | |
tree | 2b8808b9a4f70de297d0df8940db95ab3b70eb7d | |
parent | 00202b013ef2e588d148a6a9acb871f7035a5944 (diff) |
pinctrl: mvebu: dove: use remapped mpp4 register
Now that we have an ioremapped mpp4 register, get rid of hardcoded
physical addresses. While at it, also remove DOVE_ prefix from those
macros.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r-- | drivers/pinctrl/mvebu/pinctrl-dove.c | 53 |
1 files changed, 27 insertions, 26 deletions
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c index 902c18f11b94..d48db53957e0 100644 --- a/drivers/pinctrl/mvebu/pinctrl-dove.c +++ b/drivers/pinctrl/mvebu/pinctrl-dove.c | |||
@@ -46,18 +46,19 @@ | |||
46 | #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) | 46 | #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) |
47 | #define DOVE_NAND_GPIO_EN BIT(0) | 47 | #define DOVE_NAND_GPIO_EN BIT(0) |
48 | #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) | 48 | #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) |
49 | #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) | ||
50 | #define DOVE_SPI_GPIO_SEL BIT(5) | ||
51 | #define DOVE_UART1_GPIO_SEL BIT(4) | ||
52 | #define DOVE_AU1_GPIO_SEL BIT(3) | ||
53 | #define DOVE_CAM_GPIO_SEL BIT(2) | ||
54 | #define DOVE_SD1_GPIO_SEL BIT(1) | ||
55 | #define DOVE_SD0_GPIO_SEL BIT(0) | ||
56 | 49 | ||
57 | /* MPP Base registers */ | 50 | /* MPP Base registers */ |
58 | #define PMU_MPP_GENERAL_CTRL 0x10 | 51 | #define PMU_MPP_GENERAL_CTRL 0x10 |
59 | #define AU0_AC97_SEL BIT(16) | 52 | #define AU0_AC97_SEL BIT(16) |
60 | 53 | ||
54 | /* MPP Control 4 register */ | ||
55 | #define SPI_GPIO_SEL BIT(5) | ||
56 | #define UART1_GPIO_SEL BIT(4) | ||
57 | #define AU1_GPIO_SEL BIT(3) | ||
58 | #define CAM_GPIO_SEL BIT(2) | ||
59 | #define SD1_GPIO_SEL BIT(1) | ||
60 | #define SD0_GPIO_SEL BIT(0) | ||
61 | |||
61 | #define CONFIG_PMU BIT(4) | 62 | #define CONFIG_PMU BIT(4) |
62 | 63 | ||
63 | static void __iomem *mpp_base; | 64 | static void __iomem *mpp_base; |
@@ -115,24 +116,24 @@ static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config) | |||
115 | 116 | ||
116 | static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) | 117 | static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) |
117 | { | 118 | { |
118 | unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); | 119 | unsigned long mpp4 = readl(mpp4_base); |
119 | unsigned long mask; | 120 | unsigned long mask; |
120 | 121 | ||
121 | switch (pid) { | 122 | switch (pid) { |
122 | case 24: /* mpp_camera */ | 123 | case 24: /* mpp_camera */ |
123 | mask = DOVE_CAM_GPIO_SEL; | 124 | mask = CAM_GPIO_SEL; |
124 | break; | 125 | break; |
125 | case 40: /* mpp_sdio0 */ | 126 | case 40: /* mpp_sdio0 */ |
126 | mask = DOVE_SD0_GPIO_SEL; | 127 | mask = SD0_GPIO_SEL; |
127 | break; | 128 | break; |
128 | case 46: /* mpp_sdio1 */ | 129 | case 46: /* mpp_sdio1 */ |
129 | mask = DOVE_SD1_GPIO_SEL; | 130 | mask = SD1_GPIO_SEL; |
130 | break; | 131 | break; |
131 | case 58: /* mpp_spi0 */ | 132 | case 58: /* mpp_spi0 */ |
132 | mask = DOVE_SPI_GPIO_SEL; | 133 | mask = SPI_GPIO_SEL; |
133 | break; | 134 | break; |
134 | case 62: /* mpp_uart1 */ | 135 | case 62: /* mpp_uart1 */ |
135 | mask = DOVE_UART1_GPIO_SEL; | 136 | mask = UART1_GPIO_SEL; |
136 | break; | 137 | break; |
137 | default: | 138 | default: |
138 | return -EINVAL; | 139 | return -EINVAL; |
@@ -145,24 +146,24 @@ static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) | |||
145 | 146 | ||
146 | static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) | 147 | static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) |
147 | { | 148 | { |
148 | unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); | 149 | unsigned long mpp4 = readl(mpp4_base); |
149 | unsigned long mask; | 150 | unsigned long mask; |
150 | 151 | ||
151 | switch (pid) { | 152 | switch (pid) { |
152 | case 24: /* mpp_camera */ | 153 | case 24: /* mpp_camera */ |
153 | mask = DOVE_CAM_GPIO_SEL; | 154 | mask = CAM_GPIO_SEL; |
154 | break; | 155 | break; |
155 | case 40: /* mpp_sdio0 */ | 156 | case 40: /* mpp_sdio0 */ |
156 | mask = DOVE_SD0_GPIO_SEL; | 157 | mask = SD0_GPIO_SEL; |
157 | break; | 158 | break; |
158 | case 46: /* mpp_sdio1 */ | 159 | case 46: /* mpp_sdio1 */ |
159 | mask = DOVE_SD1_GPIO_SEL; | 160 | mask = SD1_GPIO_SEL; |
160 | break; | 161 | break; |
161 | case 58: /* mpp_spi0 */ | 162 | case 58: /* mpp_spi0 */ |
162 | mask = DOVE_SPI_GPIO_SEL; | 163 | mask = SPI_GPIO_SEL; |
163 | break; | 164 | break; |
164 | case 62: /* mpp_uart1 */ | 165 | case 62: /* mpp_uart1 */ |
165 | mask = DOVE_UART1_GPIO_SEL; | 166 | mask = UART1_GPIO_SEL; |
166 | break; | 167 | break; |
167 | default: | 168 | default: |
168 | return -EINVAL; | 169 | return -EINVAL; |
@@ -172,7 +173,7 @@ static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) | |||
172 | if (config) | 173 | if (config) |
173 | mpp4 |= mask; | 174 | mpp4 |= mask; |
174 | 175 | ||
175 | writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); | 176 | writel(mpp4, mpp4_base); |
176 | 177 | ||
177 | return 0; | 178 | return 0; |
178 | } | 179 | } |
@@ -222,13 +223,13 @@ static int dove_audio0_ctrl_set(unsigned pid, unsigned long config) | |||
222 | 223 | ||
223 | static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) | 224 | static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) |
224 | { | 225 | { |
225 | unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); | 226 | unsigned int mpp4 = readl(mpp4_base); |
226 | unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); | 227 | unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); |
227 | unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); | 228 | unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); |
228 | unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); | 229 | unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); |
229 | 230 | ||
230 | *config = 0; | 231 | *config = 0; |
231 | if (mpp4 & DOVE_AU1_GPIO_SEL) | 232 | if (mpp4 & AU1_GPIO_SEL) |
232 | *config |= BIT(3); | 233 | *config |= BIT(3); |
233 | if (sspc1 & DOVE_SSP_ON_AU1) | 234 | if (sspc1 & DOVE_SSP_ON_AU1) |
234 | *config |= BIT(2); | 235 | *config |= BIT(2); |
@@ -248,7 +249,7 @@ static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) | |||
248 | 249 | ||
249 | static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) | 250 | static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) |
250 | { | 251 | { |
251 | unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); | 252 | unsigned int mpp4 = readl(mpp4_base); |
252 | unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); | 253 | unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); |
253 | unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); | 254 | unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); |
254 | unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); | 255 | unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); |
@@ -259,7 +260,7 @@ static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) | |||
259 | gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO; | 260 | gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO; |
260 | gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN; | 261 | gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN; |
261 | sspc1 &= ~DOVE_SSP_ON_AU1; | 262 | sspc1 &= ~DOVE_SSP_ON_AU1; |
262 | mpp4 &= ~DOVE_AU1_GPIO_SEL; | 263 | mpp4 &= ~AU1_GPIO_SEL; |
263 | 264 | ||
264 | if (config & BIT(0)) | 265 | if (config & BIT(0)) |
265 | gcfg2 |= DOVE_TWSI_OPTION3_GPIO; | 266 | gcfg2 |= DOVE_TWSI_OPTION3_GPIO; |
@@ -268,9 +269,9 @@ static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) | |||
268 | if (config & BIT(2)) | 269 | if (config & BIT(2)) |
269 | sspc1 |= DOVE_SSP_ON_AU1; | 270 | sspc1 |= DOVE_SSP_ON_AU1; |
270 | if (config & BIT(3)) | 271 | if (config & BIT(3)) |
271 | mpp4 |= DOVE_AU1_GPIO_SEL; | 272 | mpp4 |= AU1_GPIO_SEL; |
272 | 273 | ||
273 | writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); | 274 | writel(mpp4, mpp4_base); |
274 | writel(sspc1, DOVE_SSP_CTRL_STATUS_1); | 275 | writel(sspc1, DOVE_SSP_CTRL_STATUS_1); |
275 | writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); | 276 | writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); |
276 | writel(gcfg2, DOVE_GLOBAL_CONFIG_2); | 277 | writel(gcfg2, DOVE_GLOBAL_CONFIG_2); |