ARM: 8215/1: vfp: Silence mvfr0 variable unused warning

Stephen Rothwell reports that commit 3f4c9f8f0a20 ("ARM: 8197/1:
vfp: Fix VFPv3 hwcap detection on CPUID based cpus") introduced a
variable unused warning.

arch/arm/vfp/vfpmodule.c: In function 'vfp_init':
arch/arm/vfp/vfpmodule.c:725:6: warning: unused variable 'mvfr0'
[-Wunused-variable]
  u32 mvfr0;

Silence this warning by using IS_ENABLED instead of ifdefs.

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 22 insertions, 23 deletions

diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 5002d002f6e3..f6e4d56eda00 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -722,7 +722,6 @@ static int __init vfp_init(void)
 {
         unsigned int vfpsid;
         unsigned int cpu_arch = cpu_architecture();
-        u32 mvfr0;
 
         if (cpu_arch >= CPU_ARCH_ARMv6)
                 on_each_cpu(vfp_enable, NULL, 1);
@@ -752,30 +751,30 @@ static int __init vfp_init(void)
                  * precision floating point operations. Only check
                  * for NEON if the hardware has the MVFR registers.
                  */
-#ifdef CONFIG_NEON
-                if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
+                if (IS_ENABLED(CONFIG_NEON) &&
+                   (fmrx(MVFR1) & 0x000fff00) == 0x00011100)
                         elf_hwcap |= HWCAP_NEON;
-#endif
-#ifdef CONFIG_VFPv3
-                mvfr0 = fmrx(MVFR0);
-                if (((mvfr0 & MVFR0_DP_MASK) >> MVFR0_DP_BIT) == 0x2 ||
-                    ((mvfr0 & MVFR0_SP_MASK) >> MVFR0_SP_BIT) == 0x2) {
-                        elf_hwcap |= HWCAP_VFPv3;
-                        /*
-                         * Check for VFPv3 D16 and VFPv4 D16.  CPUs in
-                         * this configuration only have 16 x 64bit
-                         * registers.
-                         */
-                        if ((mvfr0 & MVFR0_A_SIMD_MASK) == 1)
-                                /* also v4-D16 */
-                                elf_hwcap |= HWCAP_VFPv3D16;
-                        else
-                                elf_hwcap |= HWCAP_VFPD32;
-                }
 
-                if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000)
-                        elf_hwcap |= HWCAP_VFPv4;
-#endif
+                if (IS_ENABLED(CONFIG_VFPv3)) {
+                        u32 mvfr0 = fmrx(MVFR0);
+                        if (((mvfr0 & MVFR0_DP_MASK) >> MVFR0_DP_BIT) == 0x2 ||
+                            ((mvfr0 & MVFR0_SP_MASK) >> MVFR0_SP_BIT) == 0x2) {
+                                elf_hwcap |= HWCAP_VFPv3;
+                                /*
+                                 * Check for VFPv3 D16 and VFPv4 D16.  CPUs in
+                                 * this configuration only have 16 x 64bit
+                                 * registers.
+                                 */
+                                if ((mvfr0 & MVFR0_A_SIMD_MASK) == 1)
+                                        /* also v4-D16 */
+                                        elf_hwcap |= HWCAP_VFPv3D16;
+                                else
+                                        elf_hwcap |= HWCAP_VFPD32;
+                        }
+
+                        if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000)
+                                elf_hwcap |= HWCAP_VFPv4;
+                }
         /* Extract the architecture version on pre-cpuid scheme */
         } else {
                 if (vfpsid & FPSID_NODOUBLE) {