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authorGavin Shan <gwshan@linux.vnet.ibm.com>2014-06-19 03:22:45 -0400
committerBjorn Helgaas <bhelgaas@google.com>2014-07-03 18:45:04 -0400
commit21dd5a43d00ca513c6a4a31fa86bbe608f68ed49 (patch)
tree9b392214633e8541344a8fbd9ced4408af8ebe78
parent9e33002fd1791bcab626b19301670484c1cb6d50 (diff)
powerpc/pci: Remove duplicate logic
Since the logic to reset PCI secondary bus by PCI config register PCI_BRIDGE_CTL_BUS_RESET is included in pci_reset_secondary_bus(), we needn't implement another one. Remove the duplicate implementation and call pci_reset_secondary_bus(). Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--arch/powerpc/kernel/pci-common.c11
1 files changed, 1 insertions, 10 deletions
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index b49c72fd7f16..b2814e23e1ed 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -123,21 +123,12 @@ resource_size_t pcibios_window_alignment(struct pci_bus *bus,
123 123
124void pcibios_reset_secondary_bus(struct pci_dev *dev) 124void pcibios_reset_secondary_bus(struct pci_dev *dev)
125{ 125{
126 u16 ctrl;
127
128 if (ppc_md.pcibios_reset_secondary_bus) { 126 if (ppc_md.pcibios_reset_secondary_bus) {
129 ppc_md.pcibios_reset_secondary_bus(dev); 127 ppc_md.pcibios_reset_secondary_bus(dev);
130 return; 128 return;
131 } 129 }
132 130
133 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); 131 pci_reset_secondary_bus(dev);
134 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
135 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
136 msleep(2);
137
138 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
139 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
140 ssleep(1);
141} 132}
142 133
143static resource_size_t pcibios_io_size(const struct pci_controller *hose) 134static resource_size_t pcibios_io_size(const struct pci_controller *hose)