diff options
author | Loc Ho <lho@apm.com> | 2014-03-14 19:53:19 -0400 |
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committer | Tejun Heo <tj@kernel.org> | 2014-03-17 15:54:40 -0400 |
commit | 1ccaead5f5a66162fafd1ce1e6282df04e181d0a (patch) | |
tree | 3002ea5b2d91f2e73aa06da027b520bf3075fb24 | |
parent | 71b70ee9350f239ea021bbb737771ebd5d02c020 (diff) |
Documentation: Add documentation for the APM X-Gene SoC SATA host controller DTS binding
This patch adds documentation for the APM X-Gene SoC SATA host controller DTS
binding.
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Tuan Phan <tphan@apm.com>
Signed-off-by: Suman Tripathi <stripathi@apm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Tejun Heo <tj@kernel.org>
-rw-r--r-- | Documentation/devicetree/bindings/ata/apm-xgene.txt | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt b/Documentation/devicetree/bindings/ata/apm-xgene.txt new file mode 100644 index 000000000000..7bcfbf59810e --- /dev/null +++ b/Documentation/devicetree/bindings/ata/apm-xgene.txt | |||
@@ -0,0 +1,76 @@ | |||
1 | * APM X-Gene 6.0 Gb/s SATA host controller nodes | ||
2 | |||
3 | SATA host controller nodes are defined to describe on-chip Serial ATA | ||
4 | controllers. Each SATA controller (pair of ports) have its own node. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : Shall contain: | ||
8 | * "apm,xgene-ahci" | ||
9 | - reg : First memory resource shall be the AHCI memory | ||
10 | resource. | ||
11 | Second memory resource shall be the host controller | ||
12 | core memory resource. | ||
13 | Third memory resource shall be the host controller | ||
14 | diagnostic memory resource. | ||
15 | 4th memory resource shall be the host controller | ||
16 | AXI memory resource. | ||
17 | 5th optional memory resource shall be the host | ||
18 | controller MUX memory resource if required. | ||
19 | - interrupts : Interrupt-specifier for SATA host controller IRQ. | ||
20 | - clocks : Reference to the clock entry. | ||
21 | - phys : A list of phandles + phy-specifiers, one for each | ||
22 | entry in phy-names. | ||
23 | - phy-names : Should contain: | ||
24 | * "sata-phy" for the SATA 6.0Gbps PHY | ||
25 | |||
26 | Optional properties: | ||
27 | - status : Shall be "ok" if enabled or "disabled" if disabled. | ||
28 | Default is "ok". | ||
29 | |||
30 | Example: | ||
31 | sataclk: sataclk { | ||
32 | compatible = "fixed-clock"; | ||
33 | #clock-cells = <1>; | ||
34 | clock-frequency = <100000000>; | ||
35 | clock-output-names = "sataclk"; | ||
36 | }; | ||
37 | |||
38 | phy2: phy@1f22a000 { | ||
39 | compatible = "apm,xgene-phy"; | ||
40 | reg = <0x0 0x1f22a000 0x0 0x100>; | ||
41 | #phy-cells = <1>; | ||
42 | }; | ||
43 | |||
44 | phy3: phy@1f23a000 { | ||
45 | compatible = "apm,xgene-phy"; | ||
46 | reg = <0x0 0x1f23a000 0x0 0x100>; | ||
47 | #phy-cells = <1>; | ||
48 | }; | ||
49 | |||
50 | sata2: sata@1a400000 { | ||
51 | compatible = "apm,xgene-ahci"; | ||
52 | reg = <0x0 0x1a400000 0x0 0x1000>, | ||
53 | <0x0 0x1f220000 0x0 0x1000>, | ||
54 | <0x0 0x1f22d000 0x0 0x1000>, | ||
55 | <0x0 0x1f22e000 0x0 0x1000>, | ||
56 | <0x0 0x1f227000 0x0 0x1000>; | ||
57 | interrupts = <0x0 0x87 0x4>; | ||
58 | status = "ok"; | ||
59 | clocks = <&sataclk 0>; | ||
60 | phys = <&phy2 0>; | ||
61 | phy-names = "sata-phy"; | ||
62 | }; | ||
63 | |||
64 | sata3: sata@1a800000 { | ||
65 | compatible = "apm,xgene-ahci-pcie"; | ||
66 | reg = <0x0 0x1a800000 0x0 0x1000>, | ||
67 | <0x0 0x1f230000 0x0 0x1000>, | ||
68 | <0x0 0x1f23d000 0x0 0x1000>, | ||
69 | <0x0 0x1f23e000 0x0 0x1000>, | ||
70 | <0x0 0x1f237000 0x0 0x1000>; | ||
71 | interrupts = <0x0 0x88 0x4>; | ||
72 | status = "ok"; | ||
73 | clocks = <&sataclk 0>; | ||
74 | phys = <&phy3 0>; | ||
75 | phy-names = "sata-phy"; | ||
76 | }; | ||