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authorArnd Bergmann <arnd@arndb.de>2014-07-28 08:16:24 -0400
committerArnd Bergmann <arnd@arndb.de>2014-07-28 08:16:24 -0400
commit1c607f0af075f676d3e138e94d46ba44e15c0f5f (patch)
tree2f7ff067e335c9aa60acdbc0df4b74f318cc5b8a
parentb99cfa66e118ef5535f18228a373a6e2d8fa4275 (diff)
parent08567053f5cc4255ab53b75277b6102a3202bd75 (diff)
Merge tag 'v3.17-rockchip-rk3xxx-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Merge "ARM: dts: changes for existing rockchip boards" from Heiko Stuebner: Collected changes for existing Rockchip boards - convert to new clock driver - bring structure in line with recent rk3288 comments (no soc-nodes, using phandles when adding changes, sorted by address) - i2c, board-pmic and pwm nodes nodes - sd card slot and ir receiver on radxa rock * tag 'v3.17-rockchip-rk3xxx-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rk3188-radxarock: add GPIO IR receiver node ARM: dts: rockchip: add pwm nodes ARM: dts: rockchip: add both clocks to uart nodes ARM: dts: rk3188-radxarock: enable sd-card slot ARM: dts: add i2c and regulator nodes to rk3188-radxarock ARM: dts: rockchip: add tps65910 regulator for bqcurie2 ARM: dts: add rk3066 and rk3188 i2c device nodes and pinctrl settings ARM: dts: rockchip: oder nodes by register address ARM: dts: rockchip: remove address from pinctrl nodes ARM: dts: uses handles to reference nodes for changes ARM: dts: rockchip: add handles for shared nodes that don't have one yet ARM: dts: rockchip: remove soc subnodes arm: dts: rockchip: remove obsolete clock gate definitions ARM: dts: rockchip: move oscillator input clock into main dtsi ARM: dts: rockchip: add cru nodes and update device clocks to use it Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm/boot/dts/rk3066a-bqcurie2.dts210
-rw-r--r--arch/arm/boot/dts/rk3066a-clocks.dtsi299
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi515
-rw-r--r--arch/arm/boot/dts/rk3188-clocks.dtsi289
-rw-r--r--arch/arm/boot/dts/rk3188-radxarock.dts216
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi442
-rw-r--r--arch/arm/boot/dts/rk3xxx.dtsi348
7 files changed, 1176 insertions, 1143 deletions
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index afb327322a4a..8b479f767561 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -24,87 +24,167 @@
24 reg = <0x60000000 0x40000000>; 24 reg = <0x60000000 0x40000000>;
25 }; 25 };
26 26
27 soc { 27 vcc_sd0: fixed-regulator {
28 uart0: serial@10124000 { 28 compatible = "regulator-fixed";
29 status = "okay"; 29 regulator-name = "sdmmc-supply";
30 }; 30 regulator-min-microvolt = <3000000>;
31 regulator-max-microvolt = <3000000>;
32 gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
33 startup-delay-us = <100000>;
34 vin-supply = <&vcc_io>;
35 };
31 36
32 uart1: serial@10126000 { 37 gpio-keys {
33 status = "okay"; 38 compatible = "gpio-keys";
39 #address-cells = <1>;
40 #size-cells = <0>;
41 autorepeat;
42
43 button@0 {
44 gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
45 linux,code = <116>;
46 label = "GPIO Key Power";
47 linux,input-type = <1>;
48 gpio-key,wakeup = <1>;
49 debounce-interval = <100>;
34 }; 50 };
35 51 button@1 {
36 uart2: serial@20064000 { 52 gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
37 pinctrl-names = "default"; 53 linux,code = <104>;
38 pinctrl-0 = <&uart2_xfer>; 54 label = "GPIO Key Vol-";
39 status = "okay"; 55 linux,input-type = <1>;
56 gpio-key,wakeup = <0>;
57 debounce-interval = <100>;
40 }; 58 };
59 /* VOL+ comes somehow thru the ADC */
60 };
61};
41 62
42 uart3: serial@20068000 { 63&i2c1 {
43 status = "okay"; 64 status = "okay";
44 }; 65 clock-frequency = <400000>;
45 66
46 vcc_sd0: fixed-regulator { 67 tps: tps@2d {
47 compatible = "regulator-fixed"; 68 reg = <0x2d>;
48 regulator-name = "sdmmc-supply";
49 regulator-min-microvolt = <3000000>;
50 regulator-max-microvolt = <3000000>;
51 gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
52 startup-delay-us = <100000>;
53 };
54 69
55 dwmmc@10214000 { /* sdmmc */ 70 interrupt-parent = <&gpio6>;
56 num-slots = <1>; 71 interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
57 status = "okay";
58 72
59 pinctrl-names = "default"; 73 vcc5-supply = <&vcc_io>;
60 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; 74 vcc6-supply = <&vcc_io>;
61 vmmc-supply = <&vcc_sd0>;
62 75
63 slot@0 { 76 regulators {
64 reg = <0>; 77 vcc_rtc: regulator@0 {
65 bus-width = <4>; 78 regulator-name = "vcc_rtc";
66 disable-wp; 79 regulator-always-on;
67 }; 80 };
68 };
69 81
70 dwmmc@10218000 { /* wifi */ 82 vcc_io: regulator@1 {
71 num-slots = <1>; 83 regulator-name = "vcc_io";
72 status = "okay"; 84 regulator-always-on;
73 non-removable; 85 };
74 86
75 pinctrl-names = "default"; 87 vdd_arm: regulator@2 {
76 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; 88 regulator-name = "vdd_arm";
89 regulator-min-microvolt = <600000>;
90 regulator-max-microvolt = <1500000>;
91 regulator-boot-on;
92 regulator-always-on;
93 };
77 94
78 slot@0 { 95 vcc_ddr: regulator@3 {
79 reg = <0>; 96 regulator-name = "vcc_ddr";
80 bus-width = <4>; 97 regulator-min-microvolt = <600000>;
81 disable-wp; 98 regulator-max-microvolt = <1500000>;
99 regulator-boot-on;
100 regulator-always-on;
101 };
102
103 vcc18_cif: regulator@5 {
104 regulator-name = "vcc18_cif";
105 regulator-always-on;
106 };
107
108 vdd_11: regulator@6 {
109 regulator-name = "vdd_11";
110 regulator-always-on;
111 };
112
113 vcc_25: regulator@7 {
114 regulator-name = "vcc_25";
115 regulator-always-on;
116 };
117
118 vcc_18: regulator@8 {
119 regulator-name = "vcc_18";
120 regulator-always-on;
121 };
122
123 vcc25_hdmi: regulator@9 {
124 regulator-name = "vcc25_hdmi";
125 regulator-always-on;
82 }; 126 };
83 };
84 127
85 gpio-keys { 128 vcca_33: regulator@10 {
86 compatible = "gpio-keys"; 129 regulator-name = "vcca_33";
87 #address-cells = <1>; 130 regulator-always-on;
88 #size-cells = <0>;
89 autorepeat;
90
91 button@0 {
92 gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
93 linux,code = <116>;
94 label = "GPIO Key Power";
95 linux,input-type = <1>;
96 gpio-key,wakeup = <1>;
97 debounce-interval = <100>;
98 }; 131 };
99 button@1 { 132
100 gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ 133 vcc_tp: regulator@11 {
101 linux,code = <104>; 134 regulator-name = "vcc_tp";
102 label = "GPIO Key Vol-"; 135 regulator-always-on;
103 linux,input-type = <1>; 136 };
104 gpio-key,wakeup = <0>; 137
105 debounce-interval = <100>; 138 vcc28_cif: regulator@12 {
139 regulator-name = "vcc28_cif";
140 regulator-always-on;
106 }; 141 };
107 /* VOL+ comes somehow thru the ADC */
108 }; 142 };
109 }; 143 };
110}; 144};
145
146/* must be included after &tps gets defined */
147#include "tps65910.dtsi"
148
149&mmc0 { /* sdmmc */
150 num-slots = <1>;
151 status = "okay";
152 vmmc-supply = <&vcc_sd0>;
153
154 slot@0 {
155 reg = <0>;
156 bus-width = <4>;
157 disable-wp;
158 };
159};
160
161&mmc1 { /* wifi */
162 num-slots = <1>;
163 status = "okay";
164 non-removable;
165
166 pinctrl-names = "default";
167 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
168
169 slot@0 {
170 reg = <0>;
171 bus-width = <4>;
172 disable-wp;
173 };
174};
175
176&uart0 {
177 status = "okay";
178};
179
180&uart1 {
181 status = "okay";
182};
183
184&uart2 {
185 status = "okay";
186};
187
188&uart3 {
189 status = "okay";
190};
diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi
deleted file mode 100644
index 6e307fc4c451..000000000000
--- a/arch/arm/boot/dts/rk3066a-clocks.dtsi
+++ /dev/null
@@ -1,299 +0,0 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/ {
17 clocks {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 ranges;
21
22 /*
23 * This is a dummy clock, to be used as placeholder on
24 * other mux clocks when a specific parent clock is not
25 * yet implemented. It should be dropped when the driver
26 * is complete.
27 */
28 dummy: dummy {
29 compatible = "fixed-clock";
30 clock-frequency = <0>;
31 #clock-cells = <0>;
32 };
33
34 xin24m: xin24m {
35 compatible = "fixed-clock";
36 clock-frequency = <24000000>;
37 #clock-cells = <0>;
38 };
39
40 dummy48m: dummy48m {
41 compatible = "fixed-clock";
42 clock-frequency = <48000000>;
43 #clock-cells = <0>;
44 };
45
46 dummy150m: dummy150m {
47 compatible = "fixed-clock";
48 clock-frequency = <150000000>;
49 #clock-cells = <0>;
50 };
51
52 clk_gates0: gate-clk@200000d0 {
53 compatible = "rockchip,rk2928-gate-clk";
54 reg = <0x200000d0 0x4>;
55 clocks = <&dummy>, <&dummy>,
56 <&dummy>, <&dummy>,
57 <&dummy>, <&dummy>,
58 <&dummy>, <&dummy>,
59 <&dummy>, <&dummy>,
60 <&dummy>, <&dummy>,
61 <&dummy>, <&dummy>,
62 <&dummy>, <&dummy>;
63
64 clock-output-names =
65 "gate_core_periph", "gate_cpu_gpll",
66 "gate_ddrphy", "gate_aclk_cpu",
67 "gate_hclk_cpu", "gate_pclk_cpu",
68 "gate_atclk_cpu", "gate_i2s0",
69 "gate_i2s0_frac", "gate_i2s1",
70 "gate_i2s1_frac", "gate_i2s2",
71 "gate_i2s2_frac", "gate_spdif",
72 "gate_spdif_frac", "gate_testclk";
73
74 #clock-cells = <1>;
75 };
76
77 clk_gates1: gate-clk@200000d4 {
78 compatible = "rockchip,rk2928-gate-clk";
79 reg = <0x200000d4 0x4>;
80 clocks = <&xin24m>, <&xin24m>,
81 <&xin24m>, <&dummy>,
82 <&dummy>, <&xin24m>,
83 <&xin24m>, <&dummy>,
84 <&xin24m>, <&dummy>,
85 <&xin24m>, <&dummy>,
86 <&xin24m>, <&dummy>,
87 <&xin24m>, <&dummy>;
88
89 clock-output-names =
90 "gate_timer0", "gate_timer1",
91 "gate_timer2", "gate_jtag",
92 "gate_aclk_lcdc1_src", "gate_otgphy0",
93 "gate_otgphy1", "gate_ddr_gpll",
94 "gate_uart0", "gate_frac_uart0",
95 "gate_uart1", "gate_frac_uart1",
96 "gate_uart2", "gate_frac_uart2",
97 "gate_uart3", "gate_frac_uart3";
98
99 #clock-cells = <1>;
100 };
101
102 clk_gates2: gate-clk@200000d8 {
103 compatible = "rockchip,rk2928-gate-clk";
104 reg = <0x200000d8 0x4>;
105 clocks = <&clk_gates2 1>, <&dummy>,
106 <&dummy>, <&dummy>,
107 <&dummy>, <&dummy>,
108 <&clk_gates2 3>, <&dummy>,
109 <&dummy>, <&dummy>,
110 <&dummy>, <&dummy48m>,
111 <&dummy>, <&dummy48m>,
112 <&dummy>, <&dummy>;
113
114 clock-output-names =
115 "gate_periph_src", "gate_aclk_periph",
116 "gate_hclk_periph", "gate_pclk_periph",
117 "gate_smc", "gate_mac",
118 "gate_hsadc", "gate_hsadc_frac",
119 "gate_saradc", "gate_spi0",
120 "gate_spi1", "gate_mmc0",
121 "gate_mac_lbtest", "gate_mmc1",
122 "gate_emmc", "gate_tsadc";
123
124 #clock-cells = <1>;
125 };
126
127 clk_gates3: gate-clk@200000dc {
128 compatible = "rockchip,rk2928-gate-clk";
129 reg = <0x200000dc 0x4>;
130 clocks = <&dummy>, <&dummy>,
131 <&dummy>, <&dummy>,
132 <&dummy>, <&dummy>,
133 <&dummy>, <&dummy>,
134 <&dummy>, <&dummy>,
135 <&dummy>, <&dummy>,
136 <&dummy>, <&dummy>,
137 <&dummy>, <&dummy>;
138
139 clock-output-names =
140 "gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
141 "gate_dclk_lcdc1", "gate_pclkin_cif0",
142 "gate_pclkin_cif1", "reserved",
143 "reserved", "gate_cif0_out",
144 "gate_cif1_out", "gate_aclk_vepu",
145 "gate_hclk_vepu", "gate_aclk_vdpu",
146 "gate_hclk_vdpu", "gate_gpu_src",
147 "reserved", "gate_xin27m";
148
149 #clock-cells = <1>;
150 };
151
152 clk_gates4: gate-clk@200000e0 {
153 compatible = "rockchip,rk2928-gate-clk";
154 reg = <0x200000e0 0x4>;
155 clocks = <&clk_gates2 2>, <&clk_gates2 3>,
156 <&clk_gates2 1>, <&clk_gates2 1>,
157 <&clk_gates2 1>, <&clk_gates2 2>,
158 <&clk_gates2 2>, <&clk_gates2 2>,
159 <&clk_gates0 4>, <&clk_gates0 4>,
160 <&clk_gates0 3>, <&clk_gates0 3>,
161 <&clk_gates0 3>, <&clk_gates2 3>,
162 <&clk_gates0 4>;
163
164 clock-output-names =
165 "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
166 "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
167 "gate_aclk_pei_niu", "gate_hclk_usb_peri",
168 "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
169 "gate_hclk_cpubus", "gate_hclk_ahb2apb",
170 "gate_aclk_strc_sys", "gate_aclk_l2mem_con",
171 "gate_aclk_intmem", "gate_pclk_tsadc",
172 "gate_hclk_hdmi";
173
174 #clock-cells = <1>;
175 };
176
177 clk_gates5: gate-clk@200000e4 {
178 compatible = "rockchip,rk2928-gate-clk";
179 reg = <0x200000e4 0x4>;
180 clocks = <&clk_gates0 3>, <&clk_gates2 1>,
181 <&clk_gates0 5>, <&clk_gates0 5>,
182 <&clk_gates0 5>, <&clk_gates0 5>,
183 <&clk_gates0 4>, <&clk_gates0 5>,
184 <&clk_gates2 1>, <&clk_gates2 2>,
185 <&clk_gates2 2>, <&clk_gates2 2>,
186 <&clk_gates2 2>, <&clk_gates4 5>,
187 <&clk_gates4 5>, <&dummy>;
188
189 clock-output-names =
190 "gate_aclk_dmac1", "gate_aclk_dmac2",
191 "gate_pclk_efuse", "gate_pclk_tzpc",
192 "gate_pclk_grf", "gate_pclk_pmu",
193 "gate_hclk_rom", "gate_pclk_ddrupctl",
194 "gate_aclk_smc", "gate_hclk_nandc",
195 "gate_hclk_mmc0", "gate_hclk_mmc1",
196 "gate_hclk_emmc", "gate_hclk_otg0",
197 "gate_hclk_otg1", "gate_aclk_gpu";
198
199 #clock-cells = <1>;
200 };
201
202 clk_gates6: gate-clk@200000e8 {
203 compatible = "rockchip,rk2928-gate-clk";
204 reg = <0x200000e8 0x4>;
205 clocks = <&clk_gates3 0>, <&clk_gates0 4>,
206 <&clk_gates0 4>, <&clk_gates1 4>,
207 <&clk_gates0 4>, <&clk_gates3 0>,
208 <&clk_gates0 4>, <&clk_gates1 4>,
209 <&clk_gates3 0>, <&clk_gates0 4>,
210 <&clk_gates0 4>, <&clk_gates1 4>,
211 <&clk_gates0 4>, <&clk_gates3 0>,
212 <&dummy>, <&dummy>;
213
214 clock-output-names =
215 "gate_aclk_lcdc0", "gate_hclk_lcdc0",
216 "gate_hclk_lcdc1", "gate_aclk_lcdc1",
217 "gate_hclk_cif0", "gate_aclk_cif0",
218 "gate_hclk_cif1", "gate_aclk_cif1",
219 "gate_aclk_ipp", "gate_hclk_ipp",
220 "gate_hclk_rga", "gate_aclk_rga",
221 "gate_hclk_vio_bus", "gate_aclk_vio0",
222 "gate_aclk_vcodec", "gate_shclk_vio_h2h";
223
224 #clock-cells = <1>;
225 };
226
227 clk_gates7: gate-clk@200000ec {
228 compatible = "rockchip,rk2928-gate-clk";
229 reg = <0x200000ec 0x4>;
230 clocks = <&clk_gates2 2>, <&clk_gates0 4>,
231 <&clk_gates0 4>, <&clk_gates0 4>,
232 <&clk_gates0 4>, <&clk_gates2 2>,
233 <&clk_gates2 2>, <&clk_gates0 5>,
234 <&clk_gates0 5>, <&clk_gates0 5>,
235 <&clk_gates0 5>, <&clk_gates2 3>,
236 <&clk_gates2 3>, <&clk_gates2 3>,
237 <&clk_gates2 3>, <&clk_gates2 3>;
238
239 clock-output-names =
240 "gate_hclk_emac", "gate_hclk_spdif",
241 "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch",
242 "gate_hclk_i2s_8ch", "gate_hclk_hsadc",
243 "gate_hclk_pidf", "gate_pclk_timer0",
244 "gate_pclk_timer1", "gate_pclk_timer2",
245 "gate_pclk_pwm01", "gate_pclk_pwm23",
246 "gate_pclk_spi0", "gate_pclk_spi1",
247 "gate_pclk_saradc", "gate_pclk_wdt";
248
249 #clock-cells = <1>;
250 };
251
252 clk_gates8: gate-clk@200000f0 {
253 compatible = "rockchip,rk2928-gate-clk";
254 reg = <0x200000f0 0x4>;
255 clocks = <&clk_gates0 5>, <&clk_gates0 5>,
256 <&clk_gates2 3>, <&clk_gates2 3>,
257 <&clk_gates0 5>, <&clk_gates0 5>,
258 <&clk_gates2 3>, <&clk_gates2 3>,
259 <&clk_gates2 3>, <&clk_gates0 5>,
260 <&clk_gates0 5>, <&clk_gates0 5>,
261 <&clk_gates2 3>, <&clk_gates2 3>,
262 <&dummy>, <&clk_gates0 5>;
263
264 clock-output-names =
265 "gate_pclk_uart0", "gate_pclk_uart1",
266 "gate_pclk_uart2", "gate_pclk_uart3",
267 "gate_pclk_i2c0", "gate_pclk_i2c1",
268 "gate_pclk_i2c2", "gate_pclk_i2c3",
269 "gate_pclk_i2c4", "gate_pclk_gpio0",
270 "gate_pclk_gpio1", "gate_pclk_gpio2",
271 "gate_pclk_gpio3", "gate_pclk_gpio4",
272 "reserved", "gate_pclk_gpio6";
273
274 #clock-cells = <1>;
275 };
276
277 clk_gates9: gate-clk@200000f4 {
278 compatible = "rockchip,rk2928-gate-clk";
279 reg = <0x200000f4 0x4>;
280 clocks = <&dummy>, <&clk_gates0 5>,
281 <&dummy>, <&dummy>,
282 <&dummy>, <&clk_gates1 4>,
283 <&clk_gates0 5>, <&dummy>,
284 <&dummy>, <&dummy>,
285 <&dummy>;
286
287 clock-output-names =
288 "gate_clk_core_dbg", "gate_pclk_dbg",
289 "gate_clk_trace", "gate_atclk",
290 "gate_clk_l2c", "gate_aclk_vio1",
291 "gate_pclk_publ", "gate_aclk_intmem0",
292 "gate_aclk_intmem1", "gate_aclk_intmem2",
293 "gate_aclk_intmem3";
294
295 #clock-cells = <1>;
296 };
297 };
298
299};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 4387cfd420ba..9c34da4d8aad 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -15,8 +15,8 @@
15 15
16#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/pinctrl/rockchip.h> 17#include <dt-bindings/pinctrl/rockchip.h>
18#include <dt-bindings/clock/rk3066a-cru.h>
18#include "rk3xxx.dtsi" 19#include "rk3xxx.dtsi"
19#include "rk3066a-clocks.dtsi"
20 20
21/ { 21/ {
22 compatible = "rockchip,rk3066a"; 22 compatible = "rockchip,rk3066a";
@@ -40,247 +40,388 @@
40 }; 40 };
41 }; 41 };
42 42
43 soc { 43 sram: sram@10080000 {
44 timer@20038000 { 44 compatible = "mmio-sram";
45 compatible = "snps,dw-apb-timer-osc"; 45 reg = <0x10080000 0x10000>;
46 reg = <0x20038000 0x100>; 46 #address-cells = <1>;
47 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 47 #size-cells = <1>;
48 clocks = <&clk_gates1 0>, <&clk_gates7 7>; 48 ranges = <0 0x10080000 0x10000>;
49 clock-names = "timer", "pclk"; 49
50 smp-sram@0 {
51 compatible = "rockchip,rk3066-smp-sram";
52 reg = <0x0 0x50>;
53 };
54 };
55
56 cru: clock-controller@20000000 {
57 compatible = "rockchip,rk3066a-cru";
58 reg = <0x20000000 0x1000>;
59 rockchip,grf = <&grf>;
60
61 #clock-cells = <1>;
62 #reset-cells = <1>;
63 };
64
65 timer@2000e000 {
66 compatible = "snps,dw-apb-timer-osc";
67 reg = <0x2000e000 0x100>;
68 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
69 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
70 clock-names = "timer", "pclk";
71 };
72
73 timer@20038000 {
74 compatible = "snps,dw-apb-timer-osc";
75 reg = <0x20038000 0x100>;
76 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
78 clock-names = "timer", "pclk";
79 };
80
81 timer@2003a000 {
82 compatible = "snps,dw-apb-timer-osc";
83 reg = <0x2003a000 0x100>;
84 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
86 clock-names = "timer", "pclk";
87 };
88
89 pinctrl: pinctrl {
90 compatible = "rockchip,rk3066a-pinctrl";
91 rockchip,grf = <&grf>;
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges;
95
96 gpio0: gpio0@20034000 {
97 compatible = "rockchip,gpio-bank";
98 reg = <0x20034000 0x100>;
99 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&cru PCLK_GPIO0>;
101
102 gpio-controller;
103 #gpio-cells = <2>;
104
105 interrupt-controller;
106 #interrupt-cells = <2>;
50 }; 107 };
51 108
52 timer@2003a000 { 109 gpio1: gpio1@2003c000 {
53 compatible = "snps,dw-apb-timer-osc"; 110 compatible = "rockchip,gpio-bank";
54 reg = <0x2003a000 0x100>; 111 reg = <0x2003c000 0x100>;
55 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 112 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&clk_gates1 1>, <&clk_gates7 8>; 113 clocks = <&cru PCLK_GPIO1>;
57 clock-names = "timer", "pclk"; 114
115 gpio-controller;
116 #gpio-cells = <2>;
117
118 interrupt-controller;
119 #interrupt-cells = <2>;
58 }; 120 };
59 121
60 timer@2000e000 { 122 gpio2: gpio2@2003e000 {
61 compatible = "snps,dw-apb-timer-osc"; 123 compatible = "rockchip,gpio-bank";
62 reg = <0x2000e000 0x100>; 124 reg = <0x2003e000 0x100>;
63 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 125 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
64 clocks = <&clk_gates1 2>, <&clk_gates7 9>; 126 clocks = <&cru PCLK_GPIO2>;
65 clock-names = "timer", "pclk"; 127
128 gpio-controller;
129 #gpio-cells = <2>;
130
131 interrupt-controller;
132 #interrupt-cells = <2>;
66 }; 133 };
67 134
68 sram: sram@10080000 { 135 gpio3: gpio3@20080000 {
69 compatible = "mmio-sram"; 136 compatible = "rockchip,gpio-bank";
70 reg = <0x10080000 0x10000>; 137 reg = <0x20080000 0x100>;
71 #address-cells = <1>; 138 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
72 #size-cells = <1>; 139 clocks = <&cru PCLK_GPIO3>;
73 ranges = <0 0x10080000 0x10000>;
74 140
75 smp-sram@0 { 141 gpio-controller;
76 compatible = "rockchip,rk3066-smp-sram"; 142 #gpio-cells = <2>;
77 reg = <0x0 0x50>; 143
78 }; 144 interrupt-controller;
145 #interrupt-cells = <2>;
79 }; 146 };
80 147
81 pinctrl@20008000 { 148 gpio4: gpio4@20084000 {
82 compatible = "rockchip,rk3066a-pinctrl"; 149 compatible = "rockchip,gpio-bank";
83 rockchip,grf = <&grf>; 150 reg = <0x20084000 0x100>;
84 #address-cells = <1>; 151 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
85 #size-cells = <1>; 152 clocks = <&cru PCLK_GPIO4>;
86 ranges;
87 153
88 gpio0: gpio0@20034000 { 154 gpio-controller;
89 compatible = "rockchip,gpio-bank"; 155 #gpio-cells = <2>;
90 reg = <0x20034000 0x100>;
91 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&clk_gates8 9>;
93 156
94 gpio-controller; 157 interrupt-controller;
95 #gpio-cells = <2>; 158 #interrupt-cells = <2>;
159 };
160
161 gpio6: gpio6@2000a000 {
162 compatible = "rockchip,gpio-bank";
163 reg = <0x2000a000 0x100>;
164 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&cru PCLK_GPIO6>;
166
167 gpio-controller;
168 #gpio-cells = <2>;
169
170 interrupt-controller;
171 #interrupt-cells = <2>;
172 };
173
174 pcfg_pull_default: pcfg_pull_default {
175 bias-pull-pin-default;
176 };
177
178 pcfg_pull_none: pcfg_pull_none {
179 bias-disable;
180 };
96 181
97 interrupt-controller; 182 i2c0 {
98 #interrupt-cells = <2>; 183 i2c0_xfer: i2c0-xfer {
184 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
185 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
99 }; 186 };
187 };
100 188
101 gpio1: gpio1@2003c000 { 189 i2c1 {
102 compatible = "rockchip,gpio-bank"; 190 i2c1_xfer: i2c1-xfer {
103 reg = <0x2003c000 0x100>; 191 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
104 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 192 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
105 clocks = <&clk_gates8 10>; 193 };
194 };
106 195
107 gpio-controller; 196 i2c2 {
108 #gpio-cells = <2>; 197 i2c2_xfer: i2c2-xfer {
198 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
199 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
200 };
201 };
109 202
110 interrupt-controller; 203 i2c3 {
111 #interrupt-cells = <2>; 204 i2c3_xfer: i2c3-xfer {
205 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
206 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
112 }; 207 };
208 };
113 209
114 gpio2: gpio2@2003e000 { 210 i2c4 {
115 compatible = "rockchip,gpio-bank"; 211 i2c4_xfer: i2c4-xfer {
116 reg = <0x2003e000 0x100>; 212 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
117 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 213 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
118 clocks = <&clk_gates8 11>; 214 };
215 };
119 216
120 gpio-controller; 217 pwm0 {
121 #gpio-cells = <2>; 218 pwm0_out: pwm0-out {
219 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
220 };
221 };
122 222
123 interrupt-controller; 223 pwm1 {
124 #interrupt-cells = <2>; 224 pwm1_out: pwm1-out {
225 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
125 }; 226 };
227 };
126 228
127 gpio3: gpio3@20080000 { 229 pwm2 {
128 compatible = "rockchip,gpio-bank"; 230 pwm2_out: pwm2-out {
129 reg = <0x20080000 0x100>; 231 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
130 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 232 };
131 clocks = <&clk_gates8 12>; 233 };
132 234
133 gpio-controller; 235 pwm3 {
134 #gpio-cells = <2>; 236 pwm3_out: pwm3-out {
237 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
238 };
239 };
135 240
136 interrupt-controller; 241 uart0 {
137 #interrupt-cells = <2>; 242 uart0_xfer: uart0-xfer {
243 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
244 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
138 }; 245 };
139 246
140 gpio4: gpio4@20084000 { 247 uart0_cts: uart0-cts {
141 compatible = "rockchip,gpio-bank"; 248 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
142 reg = <0x20084000 0x100>; 249 };
143 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 250
144 clocks = <&clk_gates8 13>; 251 uart0_rts: uart0-rts {
252 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
253 };
254 };
145 255
146 gpio-controller; 256 uart1 {
147 #gpio-cells = <2>; 257 uart1_xfer: uart1-xfer {
258 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
259 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
260 };
148 261
149 interrupt-controller; 262 uart1_cts: uart1-cts {
150 #interrupt-cells = <2>; 263 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
151 }; 264 };
152 265
153 gpio6: gpio6@2000a000 { 266 uart1_rts: uart1-rts {
154 compatible = "rockchip,gpio-bank"; 267 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
155 reg = <0x2000a000 0x100>; 268 };
156 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 269 };
157 clocks = <&clk_gates8 15>;
158 270
159 gpio-controller; 271 uart2 {
160 #gpio-cells = <2>; 272 uart2_xfer: uart2-xfer {
273 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
274 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
275 };
276 /* no rts / cts for uart2 */
277 };
161 278
162 interrupt-controller; 279 uart3 {
163 #interrupt-cells = <2>; 280 uart3_xfer: uart3-xfer {
281 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
282 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
164 }; 283 };
165 284
166 pcfg_pull_default: pcfg_pull_default { 285 uart3_cts: uart3-cts {
167 bias-pull-pin-default; 286 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
168 }; 287 };
169 288
170 pcfg_pull_none: pcfg_pull_none { 289 uart3_rts: uart3-rts {
171 bias-disable; 290 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
172 }; 291 };
292 };
173 293
174 uart0 { 294 sd0 {
175 uart0_xfer: uart0-xfer { 295 sd0_clk: sd0-clk {
176 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, 296 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
177 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>; 297 };
178 };
179 298
180 uart0_cts: uart0-cts { 299 sd0_cmd: sd0-cmd {
181 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>; 300 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
182 }; 301 };
183 302
184 uart0_rts: uart0-rts { 303 sd0_cd: sd0-cd {
185 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>; 304 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
186 };
187 }; 305 };
188 306
189 uart1 { 307 sd0_wp: sd0-wp {
190 uart1_xfer: uart1-xfer { 308 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
191 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>, 309 };
192 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
193 };
194 310
195 uart1_cts: uart1-cts { 311 sd0_bus1: sd0-bus-width1 {
196 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>; 312 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
197 }; 313 };
198 314
199 uart1_rts: uart1-rts { 315 sd0_bus4: sd0-bus-width4 {
200 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>; 316 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
201 }; 317 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
318 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
319 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
202 }; 320 };
321 };
203 322
204 uart2 { 323 sd1 {
205 uart2_xfer: uart2-xfer { 324 sd1_clk: sd1-clk {
206 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>, 325 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
207 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
208 };
209 /* no rts / cts for uart2 */
210 }; 326 };
211 327
212 uart3 { 328 sd1_cmd: sd1-cmd {
213 uart3_xfer: uart3-xfer { 329 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
214 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>, 330 };
215 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
216 };
217 331
218 uart3_cts: uart3-cts { 332 sd1_cd: sd1-cd {
219 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>; 333 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
220 }; 334 };
221 335
222 uart3_rts: uart3-rts { 336 sd1_wp: sd1-wp {
223 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>; 337 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
224 };
225 }; 338 };
226 339
227 sd0 { 340 sd1_bus1: sd1-bus-width1 {
228 sd0_clk: sd0-clk { 341 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
229 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
230 };
231
232 sd0_cmd: sd0-cmd {
233 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
234 };
235
236 sd0_cd: sd0-cd {
237 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
238 };
239
240 sd0_wp: sd0-wp {
241 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
242 };
243
244 sd0_bus1: sd0-bus-width1 {
245 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
246 };
247
248 sd0_bus4: sd0-bus-width4 {
249 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
250 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
251 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
252 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
253 };
254 }; 342 };
255 343
256 sd1 { 344 sd1_bus4: sd1-bus-width4 {
257 sd1_clk: sd1-clk { 345 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
258 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>; 346 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
259 }; 347 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
260 348 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
261 sd1_cmd: sd1-cmd {
262 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
263 };
264
265 sd1_cd: sd1-cd {
266 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
267 };
268
269 sd1_wp: sd1-wp {
270 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
271 };
272
273 sd1_bus1: sd1-bus-width1 {
274 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
275 };
276
277 sd1_bus4: sd1-bus-width4 {
278 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
279 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
280 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
281 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
282 };
283 }; 349 };
284 }; 350 };
285 }; 351 };
286}; 352};
353
354&i2c0 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c0_xfer>;
357};
358
359&i2c1 {
360 pinctrl-names = "default";
361 pinctrl-0 = <&i2c1_xfer>;
362};
363
364&i2c2 {
365 pinctrl-names = "default";
366 pinctrl-0 = <&i2c2_xfer>;
367};
368
369&i2c3 {
370 pinctrl-names = "default";
371 pinctrl-0 = <&i2c3_xfer>;
372};
373
374&i2c4 {
375 pinctrl-names = "default";
376 pinctrl-0 = <&i2c4_xfer>;
377};
378
379&mmc0 {
380 pinctrl-names = "default";
381 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
382};
383
384&mmc1 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
387};
388
389&pwm0 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&pwm0_out>;
392};
393
394&pwm1 {
395 pinctrl-names = "default";
396 pinctrl-0 = <&pwm1_out>;
397};
398
399&pwm2 {
400 pinctrl-names = "default";
401 pinctrl-0 = <&pwm2_out>;
402};
403
404&pwm3 {
405 pinctrl-names = "default";
406 pinctrl-0 = <&pwm3_out>;
407};
408
409&uart0 {
410 pinctrl-names = "default";
411 pinctrl-0 = <&uart0_xfer>;
412};
413
414&uart1 {
415 pinctrl-names = "default";
416 pinctrl-0 = <&uart1_xfer>;
417};
418
419&uart2 {
420 pinctrl-names = "default";
421 pinctrl-0 = <&uart2_xfer>;
422};
423
424&uart3 {
425 pinctrl-names = "default";
426 pinctrl-0 = <&uart3_xfer>;
427};
diff --git a/arch/arm/boot/dts/rk3188-clocks.dtsi b/arch/arm/boot/dts/rk3188-clocks.dtsi
deleted file mode 100644
index b1b92dc245ce..000000000000
--- a/arch/arm/boot/dts/rk3188-clocks.dtsi
+++ /dev/null
@@ -1,289 +0,0 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/ {
17 clocks {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 ranges;
21
22 /*
23 * This is a dummy clock, to be used as placeholder on
24 * other mux clocks when a specific parent clock is not
25 * yet implemented. It should be dropped when the driver
26 * is complete.
27 */
28 dummy: dummy {
29 compatible = "fixed-clock";
30 clock-frequency = <0>;
31 #clock-cells = <0>;
32 };
33
34 xin24m: xin24m {
35 compatible = "fixed-clock";
36 clock-frequency = <24000000>;
37 #clock-cells = <0>;
38 };
39
40 dummy48m: dummy48m {
41 compatible = "fixed-clock";
42 clock-frequency = <48000000>;
43 #clock-cells = <0>;
44 };
45
46 dummy150m: dummy150m {
47 compatible = "fixed-clock";
48 clock-frequency = <150000000>;
49 #clock-cells = <0>;
50 };
51
52 clk_gates0: gate-clk@200000d0 {
53 compatible = "rockchip,rk2928-gate-clk";
54 reg = <0x200000d0 0x4>;
55 clocks = <&dummy150m>, <&dummy>,
56 <&dummy>, <&dummy>,
57 <&dummy>, <&dummy>,
58 <&dummy>, <&dummy>,
59 <&dummy>, <&dummy>,
60 <&dummy>, <&dummy>,
61 <&dummy>, <&dummy>,
62 <&dummy>, <&dummy>;
63
64 clock-output-names =
65 "gate_core_periph", "gate_cpu_gpll",
66 "gate_ddrphy", "gate_aclk_cpu",
67 "gate_hclk_cpu", "gate_pclk_cpu",
68 "gate_atclk_cpu", "gate_aclk_core",
69 "reserved", "gate_i2s0",
70 "gate_i2s0_frac", "reserved",
71 "reserved", "gate_spdif",
72 "gate_spdif_frac", "gate_testclk";
73
74 #clock-cells = <1>;
75 };
76
77 clk_gates1: gate-clk@200000d4 {
78 compatible = "rockchip,rk2928-gate-clk";
79 reg = <0x200000d4 0x4>;
80 clocks = <&xin24m>, <&xin24m>,
81 <&xin24m>, <&dummy>,
82 <&dummy>, <&xin24m>,
83 <&xin24m>, <&dummy>,
84 <&xin24m>, <&dummy>,
85 <&xin24m>, <&dummy>,
86 <&xin24m>, <&dummy>,
87 <&xin24m>, <&dummy>;
88
89 clock-output-names =
90 "gate_timer0", "gate_timer1",
91 "gate_timer3", "gate_jtag",
92 "gate_aclk_lcdc1_src", "gate_otgphy0",
93 "gate_otgphy1", "gate_ddr_gpll",
94 "gate_uart0", "gate_frac_uart0",
95 "gate_uart1", "gate_frac_uart1",
96 "gate_uart2", "gate_frac_uart2",
97 "gate_uart3", "gate_frac_uart3";
98
99 #clock-cells = <1>;
100 };
101
102 clk_gates2: gate-clk@200000d8 {
103 compatible = "rockchip,rk2928-gate-clk";
104 reg = <0x200000d8 0x4>;
105 clocks = <&clk_gates2 1>, <&dummy>,
106 <&dummy>, <&dummy>,
107 <&dummy>, <&dummy>,
108 <&clk_gates2 3>, <&dummy>,
109 <&dummy>, <&dummy>,
110 <&dummy>, <&dummy48m>,
111 <&dummy>, <&dummy48m>,
112 <&dummy>, <&dummy>;
113
114 clock-output-names =
115 "gate_periph_src", "gate_aclk_periph",
116 "gate_hclk_periph", "gate_pclk_periph",
117 "gate_smc", "gate_mac",
118 "gate_hsadc", "gate_hsadc_frac",
119 "gate_saradc", "gate_spi0",
120 "gate_spi1", "gate_mmc0",
121 "gate_mac_lbtest", "gate_mmc1",
122 "gate_emmc", "reserved";
123
124 #clock-cells = <1>;
125 };
126
127 clk_gates3: gate-clk@200000dc {
128 compatible = "rockchip,rk2928-gate-clk";
129 reg = <0x200000dc 0x4>;
130 clocks = <&dummy>, <&dummy>,
131 <&dummy>, <&dummy>,
132 <&xin24m>, <&xin24m>,
133 <&dummy>, <&dummy>,
134 <&xin24m>, <&dummy>,
135 <&dummy>, <&dummy>,
136 <&dummy>, <&dummy>,
137 <&xin24m>, <&dummy>;
138
139 clock-output-names =
140 "gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
141 "gate_dclk_lcdc1", "gate_pclkin_cif0",
142 "gate_timer2", "gate_timer4",
143 "gate_hsicphy", "gate_cif0_out",
144 "gate_timer5", "gate_aclk_vepu",
145 "gate_hclk_vepu", "gate_aclk_vdpu",
146 "gate_hclk_vdpu", "reserved",
147 "gate_timer6", "gate_aclk_gpu_src";
148
149 #clock-cells = <1>;
150 };
151
152 clk_gates4: gate-clk@200000e0 {
153 compatible = "rockchip,rk2928-gate-clk";
154 reg = <0x200000e0 0x4>;
155 clocks = <&clk_gates2 2>, <&clk_gates2 3>,
156 <&clk_gates2 1>, <&clk_gates2 1>,
157 <&clk_gates2 1>, <&clk_gates2 2>,
158 <&clk_gates2 2>, <&clk_gates2 2>,
159 <&clk_gates0 4>, <&clk_gates0 4>,
160 <&clk_gates0 3>, <&dummy>,
161 <&clk_gates0 3>, <&dummy>,
162 <&dummy>, <&dummy>;
163
164 clock-output-names =
165 "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
166 "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
167 "gate_aclk_pei_niu", "gate_hclk_usb_peri",
168 "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
169 "gate_hclk_cpubus", "gate_hclk_ahb2apb",
170 "gate_aclk_strc_sys", "reserved",
171 "gate_aclk_intmem", "reserved",
172 "gate_hclk_imem1", "gate_hclk_imem0";
173
174 #clock-cells = <1>;
175 };
176
177 clk_gates5: gate-clk@200000e4 {
178 compatible = "rockchip,rk2928-gate-clk";
179 reg = <0x200000e4 0x4>;
180 clocks = <&clk_gates0 3>, <&clk_gates2 1>,
181 <&clk_gates0 5>, <&clk_gates0 5>,
182 <&clk_gates0 5>, <&clk_gates0 5>,
183 <&clk_gates0 4>, <&clk_gates0 5>,
184 <&clk_gates2 1>, <&clk_gates2 2>,
185 <&clk_gates2 2>, <&clk_gates2 2>,
186 <&clk_gates2 2>, <&clk_gates4 5>;
187
188 clock-output-names =
189 "gate_aclk_dmac1", "gate_aclk_dmac2",
190 "gate_pclk_efuse", "gate_pclk_tzpc",
191 "gate_pclk_grf", "gate_pclk_pmu",
192 "gate_hclk_rom", "gate_pclk_ddrupctl",
193 "gate_aclk_smc", "gate_hclk_nandc",
194 "gate_hclk_mmc0", "gate_hclk_mmc1",
195 "gate_hclk_emmc", "gate_hclk_otg0";
196
197 #clock-cells = <1>;
198 };
199
200 clk_gates6: gate-clk@200000e8 {
201 compatible = "rockchip,rk2928-gate-clk";
202 reg = <0x200000e8 0x4>;
203 clocks = <&clk_gates3 0>, <&clk_gates0 4>,
204 <&clk_gates0 4>, <&clk_gates1 4>,
205 <&clk_gates0 4>, <&clk_gates3 0>,
206 <&dummy>, <&dummy>,
207 <&clk_gates3 0>, <&clk_gates0 4>,
208 <&clk_gates0 4>, <&clk_gates1 4>,
209 <&clk_gates0 4>, <&clk_gates3 0>;
210
211 clock-output-names =
212 "gate_aclk_lcdc0", "gate_hclk_lcdc0",
213 "gate_hclk_lcdc1", "gate_aclk_lcdc1",
214 "gate_hclk_cif0", "gate_aclk_cif0",
215 "reserved", "reserved",
216 "gate_aclk_ipp", "gate_hclk_ipp",
217 "gate_hclk_rga", "gate_aclk_rga",
218 "gate_hclk_vio_bus", "gate_aclk_vio0";
219
220 #clock-cells = <1>;
221 };
222
223 clk_gates7: gate-clk@200000ec {
224 compatible = "rockchip,rk2928-gate-clk";
225 reg = <0x200000ec 0x4>;
226 clocks = <&clk_gates2 2>, <&clk_gates0 4>,
227 <&clk_gates0 4>, <&dummy>,
228 <&dummy>, <&clk_gates2 2>,
229 <&clk_gates2 2>, <&clk_gates0 5>,
230 <&dummy>, <&clk_gates0 5>,
231 <&clk_gates0 5>, <&clk_gates2 3>,
232 <&clk_gates2 3>, <&clk_gates2 3>,
233 <&clk_gates2 3>, <&clk_gates2 3>;
234
235 clock-output-names =
236 "gate_hclk_emac", "gate_hclk_spdif",
237 "gate_hclk_i2s0_2ch", "gate_hclk_otg1",
238 "gate_hclk_hsic", "gate_hclk_hsadc",
239 "gate_hclk_pidf", "gate_pclk_timer0",
240 "reserved", "gate_pclk_timer2",
241 "gate_pclk_pwm01", "gate_pclk_pwm23",
242 "gate_pclk_spi0", "gate_pclk_spi1",
243 "gate_pclk_saradc", "gate_pclk_wdt";
244
245 #clock-cells = <1>;
246 };
247
248 clk_gates8: gate-clk@200000f0 {
249 compatible = "rockchip,rk2928-gate-clk";
250 reg = <0x200000f0 0x4>;
251 clocks = <&clk_gates0 5>, <&clk_gates0 5>,
252 <&clk_gates2 3>, <&clk_gates2 3>,
253 <&clk_gates0 5>, <&clk_gates0 5>,
254 <&clk_gates2 3>, <&clk_gates2 3>,
255 <&clk_gates2 3>, <&clk_gates0 5>,
256 <&clk_gates0 5>, <&clk_gates0 5>,
257 <&clk_gates2 3>, <&dummy>;
258
259 clock-output-names =
260 "gate_pclk_uart0", "gate_pclk_uart1",
261 "gate_pclk_uart2", "gate_pclk_uart3",
262 "gate_pclk_i2c0", "gate_pclk_i2c1",
263 "gate_pclk_i2c2", "gate_pclk_i2c3",
264 "gate_pclk_i2c4", "gate_pclk_gpio0",
265 "gate_pclk_gpio1", "gate_pclk_gpio2",
266 "gate_pclk_gpio3", "gate_aclk_gps";
267
268 #clock-cells = <1>;
269 };
270
271 clk_gates9: gate-clk@200000f4 {
272 compatible = "rockchip,rk2928-gate-clk";
273 reg = <0x200000f4 0x4>;
274 clocks = <&dummy>, <&dummy>,
275 <&dummy>, <&dummy>,
276 <&dummy>, <&dummy>,
277 <&dummy>, <&dummy>;
278
279 clock-output-names =
280 "gate_clk_core_dbg", "gate_pclk_dbg",
281 "gate_clk_trace", "gate_atclk",
282 "gate_clk_l2c", "gate_aclk_vio1",
283 "gate_pclk_publ", "gate_aclk_gpu";
284
285 #clock-cells = <1>;
286 };
287 };
288
289};
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index a5eee55079cb..b7f34232e3d2 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -23,59 +23,203 @@
23 reg = <0x60000000 0x80000000>; 23 reg = <0x60000000 0x80000000>;
24 }; 24 };
25 25
26 soc { 26 gpio-keys {
27 uart0: serial@10124000 { 27 compatible = "gpio-keys";
28 status = "okay"; 28 #address-cells = <1>;
29 #size-cells = <0>;
30 autorepeat;
31
32 button@0 {
33 gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
34 linux,code = <116>;
35 label = "GPIO Key Power";
36 linux,input-type = <1>;
37 gpio-key,wakeup = <1>;
38 debounce-interval = <100>;
29 }; 39 };
40 };
41
42 gpio-leds {
43 compatible = "gpio-leds";
30 44
31 uart1: serial@10126000 { 45 green {
32 status = "okay"; 46 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
47 default-state = "off";
33 }; 48 };
34 49
35 uart2: serial@20064000 { 50 yellow {
36 pinctrl-names = "default"; 51 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
37 pinctrl-0 = <&uart2_xfer>; 52 default-state = "off";
38 status = "okay";
39 }; 53 };
40 54
41 uart3: serial@20068000 { 55 sleep {
42 status = "okay"; 56 gpios = <&gpio0 15 0>;
57 default-state = "off";
43 }; 58 };
59 };
60
61 ir_recv: gpio-ir-receiver {
62 compatible = "gpio-ir-receiver";
63 gpios = <&gpio0 10 1>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&ir_recv_pin>;
66 };
67
68 vcc_sd0: sdmmc-regulator {
69 compatible = "regulator-fixed";
70 regulator-name = "sdmmc-supply";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 gpio = <&gpio3 1 GPIO_ACTIVE_LOW>;
74 startup-delay-us = <100000>;
75 vin-supply = <&vcc_io>;
76 };
77};
78
79&i2c1 {
80 status = "okay";
81 clock-frequency = <400000>;
82
83 act8846: act8846@5a {
84 compatible = "active-semi,act8846";
85 reg = <0x5a>;
86 status = "okay";
87
88 pinctrl-names = "default";
89 pinctrl-0 = <&act8846_dvs0_ctl>;
44 90
45 gpio-keys { 91 regulators {
46 compatible = "gpio-keys"; 92 vcc_ddr: REG1 {
47 #address-cells = <1>; 93 regulator-name = "VCC_DDR";
48 #size-cells = <0>; 94 regulator-min-microvolt = <1200000>;
49 autorepeat; 95 regulator-max-microvolt = <1200000>;
50 96 regulator-always-on;
51 button@0 { 97 };
52 gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; 98
53 linux,code = <116>; 99 vdd_log: REG2 {
54 label = "GPIO Key Power"; 100 regulator-name = "VDD_LOG";
55 linux,input-type = <1>; 101 regulator-min-microvolt = <1000000>;
56 gpio-key,wakeup = <1>; 102 regulator-max-microvolt = <1000000>;
57 debounce-interval = <100>; 103 regulator-always-on;
104 };
105
106 vdd_arm: REG3 {
107 regulator-name = "VDD_ARM";
108 regulator-min-microvolt = <875000>;
109 regulator-max-microvolt = <1300000>;
110 regulator-always-on;
111 };
112
113 vcc_io: REG4 {
114 regulator-name = "VCC_IO";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 regulator-always-on;
118 };
119
120 vdd_10: REG5 {
121 regulator-name = "VDD_10";
122 regulator-min-microvolt = <1000000>;
123 regulator-max-microvolt = <1000000>;
124 regulator-always-on;
125 };
126
127 vdd_hdmi: REG6 {
128 regulator-name = "VDD_HDMI";
129 regulator-min-microvolt = <2500000>;
130 regulator-max-microvolt = <2500000>;
131 regulator-always-on;
132 };
133
134 vcc18: REG7 {
135 regulator-name = "VCC_18";
136 regulator-min-microvolt = <1800000>;
137 regulator-max-microvolt = <1800000>;
138 regulator-always-on;
139 };
140
141 vcca_33: REG8 {
142 regulator-name = "VCCA_33";
143 regulator-min-microvolt = <3300000>;
144 regulator-max-microvolt = <3300000>;
145 regulator-always-on;
58 }; 146 };
59 };
60 147
61 gpio-leds { 148 vcc_rmii: REG9 {
62 compatible = "gpio-leds"; 149 regulator-name = "VCC_RMII";
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 regulator-always-on;
153 };
63 154
64 green { 155 vccio_wl: REG10 {
65 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; 156 regulator-name = "VCCIO_WL";
66 default-state = "off"; 157 regulator-min-microvolt = <3300000>;
158 regulator-max-microvolt = <3300000>;
159 regulator-always-on;
67 }; 160 };
68 161
69 yellow { 162 vcc_18: REG11 {
70 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; 163 regulator-name = "VCC18_IO";
71 default-state = "off"; 164 regulator-min-microvolt = <1800000>;
165 regulator-max-microvolt = <1800000>;
166 regulator-always-on;
72 }; 167 };
73 168
74 sleep { 169 vcc28: REG12 {
75 gpios = <&gpio0 15 0>; 170 regulator-name = "VCC_28";
76 default-state = "off"; 171 regulator-min-microvolt = <2800000>;
172 regulator-max-microvolt = <2800000>;
173 regulator-always-on;
77 }; 174 };
78 }; 175 };
176 };
177};
178
179&mmc0 {
180 num-slots = <1>;
181 status = "okay";
182 vmmc-supply = <&vcc_sd0>;
183
184 slot@0 {
185 reg = <0>;
186 bus-width = <4>;
187 disable-wp;
188 };
189};
190
191&pinctrl {
192 pcfg_output_low: pcfg-output-low {
193 output-low;
194 };
195
196 act8846 {
197 act8846_dvs0_ctl: act8846-dvs0-ctl {
198 rockchip,pins = <RK_GPIO3 27 RK_FUNC_GPIO &pcfg_output_low>;
199 };
200 };
79 201
202 ir-receiver {
203 ir_recv_pin: ir-recv-pin {
204 rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>;
205 };
80 }; 206 };
81}; 207};
208
209&uart0 {
210 status = "okay";
211};
212
213&uart1 {
214 status = "okay";
215};
216
217&uart2 {
218 pinctrl-names = "default";
219 pinctrl-0 = <&uart2_xfer>;
220 status = "okay";
221};
222
223&uart3 {
224 status = "okay";
225};
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 238c996d4a7f..27215e0b5c3b 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -15,8 +15,8 @@
15 15
16#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/pinctrl/rockchip.h> 17#include <dt-bindings/pinctrl/rockchip.h>
18#include <dt-bindings/clock/rk3188-cru.h>
18#include "rk3xxx.dtsi" 19#include "rk3xxx.dtsi"
19#include "rk3188-clocks.dtsi"
20 20
21/ { 21/ {
22 compatible = "rockchip,rk3188"; 22 compatible = "rockchip,rk3188";
@@ -52,215 +52,351 @@
52 }; 52 };
53 }; 53 };
54 54
55 soc { 55 sram: sram@10080000 {
56 global-timer@1013c200 { 56 compatible = "mmio-sram";
57 interrupts = <GIC_PPI 11 0xf04>; 57 reg = <0x10080000 0x8000>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges = <0 0x10080000 0x8000>;
61
62 smp-sram@0 {
63 compatible = "rockchip,rk3066-smp-sram";
64 reg = <0x0 0x50>;
58 }; 65 };
66 };
67
68 cru: clock-controller@20000000 {
69 compatible = "rockchip,rk3188-cru";
70 reg = <0x20000000 0x1000>;
71 rockchip,grf = <&grf>;
72
73 #clock-cells = <1>;
74 #reset-cells = <1>;
75 };
76
77 pinctrl: pinctrl {
78 compatible = "rockchip,rk3188-pinctrl";
79 rockchip,grf = <&grf>;
80 rockchip,pmu = <&pmu>;
81
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
85
86 gpio0: gpio0@0x2000a000 {
87 compatible = "rockchip,rk3188-gpio-bank0";
88 reg = <0x2000a000 0x100>;
89 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&cru PCLK_GPIO0>;
91
92 gpio-controller;
93 #gpio-cells = <2>;
59 94
60 local-timer@1013c600 { 95 interrupt-controller;
61 interrupts = <GIC_PPI 13 0xf04>; 96 #interrupt-cells = <2>;
62 }; 97 };
63 98
64 sram: sram@10080000 { 99 gpio1: gpio1@0x2003c000 {
65 compatible = "mmio-sram"; 100 compatible = "rockchip,gpio-bank";
66 reg = <0x10080000 0x8000>; 101 reg = <0x2003c000 0x100>;
67 #address-cells = <1>; 102 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
68 #size-cells = <1>; 103 clocks = <&cru PCLK_GPIO1>;
69 ranges = <0 0x10080000 0x8000>;
70 104
71 smp-sram@0 { 105 gpio-controller;
72 compatible = "rockchip,rk3066-smp-sram"; 106 #gpio-cells = <2>;
73 reg = <0x0 0x50>; 107
74 }; 108 interrupt-controller;
109 #interrupt-cells = <2>;
75 }; 110 };
76 111
77 pinctrl@20008000 { 112 gpio2: gpio2@2003e000 {
78 compatible = "rockchip,rk3188-pinctrl"; 113 compatible = "rockchip,gpio-bank";
79 rockchip,grf = <&grf>; 114 reg = <0x2003e000 0x100>;
80 rockchip,pmu = <&pmu>; 115 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&cru PCLK_GPIO2>;
81 117
82 #address-cells = <1>; 118 gpio-controller;
83 #size-cells = <1>; 119 #gpio-cells = <2>;
84 ranges;
85 120
86 gpio0: gpio0@0x2000a000 { 121 interrupt-controller;
87 compatible = "rockchip,rk3188-gpio-bank0"; 122 #interrupt-cells = <2>;
88 reg = <0x2000a000 0x100>; 123 };
89 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&clk_gates8 9>;
91 124
92 gpio-controller; 125 gpio3: gpio3@20080000 {
93 #gpio-cells = <2>; 126 compatible = "rockchip,gpio-bank";
127 reg = <0x20080000 0x100>;
128 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&cru PCLK_GPIO3>;
94 130
95 interrupt-controller; 131 gpio-controller;
96 #interrupt-cells = <2>; 132 #gpio-cells = <2>;
97 };
98 133
99 gpio1: gpio1@0x2003c000 { 134 interrupt-controller;
100 compatible = "rockchip,gpio-bank"; 135 #interrupt-cells = <2>;
101 reg = <0x2003c000 0x100>; 136 };
102 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&clk_gates8 10>;
104 137
105 gpio-controller; 138 pcfg_pull_up: pcfg_pull_up {
106 #gpio-cells = <2>; 139 bias-pull-up;
140 };
107 141
108 interrupt-controller; 142 pcfg_pull_down: pcfg_pull_down {
109 #interrupt-cells = <2>; 143 bias-pull-down;
110 }; 144 };
111 145
112 gpio2: gpio2@2003e000 { 146 pcfg_pull_none: pcfg_pull_none {
113 compatible = "rockchip,gpio-bank"; 147 bias-disable;
114 reg = <0x2003e000 0x100>; 148 };
115 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&clk_gates8 11>;
117 149
118 gpio-controller; 150 i2c0 {
119 #gpio-cells = <2>; 151 i2c0_xfer: i2c0-xfer {
152 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
153 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
154 };
155 };
120 156
121 interrupt-controller; 157 i2c1 {
122 #interrupt-cells = <2>; 158 i2c1_xfer: i2c1-xfer {
159 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
160 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
123 }; 161 };
162 };
124 163
125 gpio3: gpio3@20080000 { 164 i2c2 {
126 compatible = "rockchip,gpio-bank"; 165 i2c2_xfer: i2c2-xfer {
127 reg = <0x20080000 0x100>; 166 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
128 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 167 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
129 clocks = <&clk_gates8 12>; 168 };
169 };
130 170
131 gpio-controller; 171 i2c3 {
132 #gpio-cells = <2>; 172 i2c3_xfer: i2c3-xfer {
173 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
174 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
175 };
176 };
133 177
134 interrupt-controller; 178 i2c4 {
135 #interrupt-cells = <2>; 179 i2c4_xfer: i2c4-xfer {
180 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
181 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
136 }; 182 };
183 };
137 184
138 pcfg_pull_up: pcfg_pull_up { 185 pwm0 {
139 bias-pull-up; 186 pwm0_out: pwm0-out {
187 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
140 }; 188 };
189 };
141 190
142 pcfg_pull_down: pcfg_pull_down { 191 pwm1 {
143 bias-pull-down; 192 pwm1_out: pwm1-out {
193 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
144 }; 194 };
195 };
145 196
146 pcfg_pull_none: pcfg_pull_none { 197 pwm2 {
147 bias-disable; 198 pwm2_out: pwm2-out {
199 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
148 }; 200 };
201 };
149 202
150 uart0 { 203 pwm3 {
151 uart0_xfer: uart0-xfer { 204 pwm3_out: pwm3-out {
152 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>, 205 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
153 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>; 206 };
154 }; 207 };
155 208
156 uart0_cts: uart0-cts { 209 uart0 {
157 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>; 210 uart0_xfer: uart0-xfer {
158 }; 211 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
212 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
213 };
159 214
160 uart0_rts: uart0-rts { 215 uart0_cts: uart0-cts {
161 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>; 216 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
162 };
163 }; 217 };
164 218
165 uart1 { 219 uart0_rts: uart0-rts {
166 uart1_xfer: uart1-xfer { 220 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
167 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>, 221 };
168 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>; 222 };
169 }; 223
224 uart1 {
225 uart1_xfer: uart1-xfer {
226 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
227 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
228 };
170 229
171 uart1_cts: uart1-cts { 230 uart1_cts: uart1-cts {
172 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>; 231 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
173 }; 232 };
174 233
175 uart1_rts: uart1-rts { 234 uart1_rts: uart1-rts {
176 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>; 235 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
177 };
178 }; 236 };
237 };
179 238
180 uart2 { 239 uart2 {
181 uart2_xfer: uart2-xfer { 240 uart2_xfer: uart2-xfer {
182 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>, 241 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
183 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>; 242 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
184 };
185 /* no rts / cts for uart2 */
186 }; 243 };
244 /* no rts / cts for uart2 */
245 };
187 246
188 uart3 { 247 uart3 {
189 uart3_xfer: uart3-xfer { 248 uart3_xfer: uart3-xfer {
190 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>, 249 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
191 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>; 250 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
192 }; 251 };
193 252
194 uart3_cts: uart3-cts { 253 uart3_cts: uart3-cts {
195 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>; 254 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
196 }; 255 };
197 256
198 uart3_rts: uart3-rts { 257 uart3_rts: uart3-rts {
199 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>; 258 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
200 };
201 }; 259 };
260 };
202 261
203 sd0 { 262 sd0 {
204 sd0_clk: sd0-clk { 263 sd0_clk: sd0-clk {
205 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>; 264 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
206 }; 265 };
207 266
208 sd0_cmd: sd0-cmd { 267 sd0_cmd: sd0-cmd {
209 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>; 268 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
210 }; 269 };
211 270
212 sd0_cd: sd0-cd { 271 sd0_cd: sd0-cd {
213 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>; 272 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
214 }; 273 };
215 274
216 sd0_wp: sd0-wp { 275 sd0_wp: sd0-wp {
217 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>; 276 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
218 }; 277 };
219 278
220 sd0_pwr: sd0-pwr { 279 sd0_pwr: sd0-pwr {
221 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>; 280 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
222 }; 281 };
223 282
224 sd0_bus1: sd0-bus-width1 { 283 sd0_bus1: sd0-bus-width1 {
225 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>; 284 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
226 }; 285 };
227 286
228 sd0_bus4: sd0-bus-width4 { 287 sd0_bus4: sd0-bus-width4 {
229 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>, 288 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
230 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>, 289 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
231 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>, 290 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
232 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>; 291 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
233 };
234 }; 292 };
293 };
235 294
236 sd1 { 295 sd1 {
237 sd1_clk: sd1-clk { 296 sd1_clk: sd1-clk {
238 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>; 297 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
239 }; 298 };
240 299
241 sd1_cmd: sd1-cmd { 300 sd1_cmd: sd1-cmd {
242 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>; 301 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
243 }; 302 };
244 303
245 sd1_cd: sd1-cd { 304 sd1_cd: sd1-cd {
246 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>; 305 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
247 }; 306 };
248 307
249 sd1_wp: sd1-wp { 308 sd1_wp: sd1-wp {
250 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>; 309 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
251 }; 310 };
252 311
253 sd1_bus1: sd1-bus-width1 { 312 sd1_bus1: sd1-bus-width1 {
254 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>; 313 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
255 }; 314 };
256 315
257 sd1_bus4: sd1-bus-width4 { 316 sd1_bus4: sd1-bus-width4 {
258 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>, 317 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
259 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>, 318 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
260 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>, 319 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
261 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; 320 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
262 };
263 }; 321 };
264 }; 322 };
265 }; 323 };
266}; 324};
325
326&global_timer {
327 interrupts = <GIC_PPI 11 0xf04>;
328};
329
330&local_timer {
331 interrupts = <GIC_PPI 13 0xf04>;
332};
333
334&i2c0 {
335 compatible = "rockchip,rk3188-i2c";
336 pinctrl-names = "default";
337 pinctrl-0 = <&i2c0_xfer>;
338};
339
340&i2c1 {
341 compatible = "rockchip,rk3188-i2c";
342 pinctrl-names = "default";
343 pinctrl-0 = <&i2c1_xfer>;
344};
345
346&i2c2 {
347 compatible = "rockchip,rk3188-i2c";
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c2_xfer>;
350};
351
352&i2c3 {
353 compatible = "rockchip,rk3188-i2c";
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c3_xfer>;
356};
357
358&i2c4 {
359 compatible = "rockchip,rk3188-i2c";
360 pinctrl-names = "default";
361 pinctrl-0 = <&i2c4_xfer>;
362};
363
364&pwm0 {
365 pinctrl-names = "default";
366 pinctrl-0 = <&pwm0_out>;
367};
368
369&pwm1 {
370 pinctrl-names = "default";
371 pinctrl-0 = <&pwm1_out>;
372};
373
374&pwm2 {
375 pinctrl-names = "default";
376 pinctrl-0 = <&pwm2_out>;
377};
378
379&pwm3 {
380 pinctrl-names = "default";
381 pinctrl-0 = <&pwm3_out>;
382};
383
384&uart0 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&uart0_xfer>;
387};
388
389&uart1 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&uart1_xfer>;
392};
393
394&uart2 {
395 pinctrl-names = "default";
396 pinctrl-0 = <&uart2_xfer>;
397};
398
399&uart3 {
400 pinctrl-names = "default";
401 pinctrl-0 = <&uart3_xfer>;
402};
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 2adf1cc9e85d..c6f05610ed2d 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -20,120 +20,240 @@
20/ { 20/ {
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&gic>;
22 22
23 soc { 23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &i2c4;
29 };
30
31 xin24m: oscillator {
32 compatible = "fixed-clock";
33 clock-frequency = <24000000>;
34 #clock-cells = <0>;
35 clock-output-names = "xin24m";
36 };
37
38 L2: l2-cache-controller@10138000 {
39 compatible = "arm,pl310-cache";
40 reg = <0x10138000 0x1000>;
41 cache-unified;
42 cache-level = <2>;
43 };
44
45 scu@1013c000 {
46 compatible = "arm,cortex-a9-scu";
47 reg = <0x1013c000 0x100>;
48 };
49
50 global_timer: global-timer@1013c200 {
51 compatible = "arm,cortex-a9-global-timer";
52 reg = <0x1013c200 0x20>;
53 interrupts = <GIC_PPI 11 0x304>;
54 clocks = <&cru CORE_PERI>;
55 };
56
57 local_timer: local-timer@1013c600 {
58 compatible = "arm,cortex-a9-twd-timer";
59 reg = <0x1013c600 0x20>;
60 interrupts = <GIC_PPI 13 0x304>;
61 clocks = <&cru CORE_PERI>;
62 };
63
64 gic: interrupt-controller@1013d000 {
65 compatible = "arm,cortex-a9-gic";
66 interrupt-controller;
67 #interrupt-cells = <3>;
68 reg = <0x1013d000 0x1000>,
69 <0x1013c100 0x0100>;
70 };
71
72 uart0: serial@10124000 {
73 compatible = "snps,dw-apb-uart";
74 reg = <0x10124000 0x400>;
75 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
76 reg-shift = <2>;
77 reg-io-width = <1>;
78 clock-names = "baudclk", "apb_pclk";
79 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
80 status = "disabled";
81 };
82
83 uart1: serial@10126000 {
84 compatible = "snps,dw-apb-uart";
85 reg = <0x10126000 0x400>;
86 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
87 reg-shift = <2>;
88 reg-io-width = <1>;
89 clock-names = "baudclk", "apb_pclk";
90 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
91 status = "disabled";
92 };
93
94 mmc0: dwmmc@10214000 {
95 compatible = "rockchip,rk2928-dw-mshc";
96 reg = <0x10214000 0x1000>;
97 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
24 #address-cells = <1>; 98 #address-cells = <1>;
25 #size-cells = <1>; 99 #size-cells = <0>;
26 compatible = "simple-bus"; 100
27 ranges; 101 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
28 102 clock-names = "biu", "ciu";
29 scu@1013c000 { 103
30 compatible = "arm,cortex-a9-scu"; 104 status = "disabled";
31 reg = <0x1013c000 0x100>; 105 };
32 }; 106
33 107 mmc1: dwmmc@10218000 {
34 pmu: pmu@20004000 { 108 compatible = "rockchip,rk2928-dw-mshc";
35 compatible = "rockchip,rk3066-pmu", "syscon"; 109 reg = <0x10218000 0x1000>;
36 reg = <0x20004000 0x100>; 110 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
37 }; 111 #address-cells = <1>;
38 112 #size-cells = <0>;
39 grf: grf@20008000 { 113
40 compatible = "syscon"; 114 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
41 reg = <0x20008000 0x200>; 115 clock-names = "biu", "ciu";
42 }; 116
43 117 status = "disabled";
44 gic: interrupt-controller@1013d000 { 118 };
45 compatible = "arm,cortex-a9-gic"; 119
46 interrupt-controller; 120 pmu: pmu@20004000 {
47 #interrupt-cells = <3>; 121 compatible = "rockchip,rk3066-pmu", "syscon";
48 reg = <0x1013d000 0x1000>, 122 reg = <0x20004000 0x100>;
49 <0x1013c100 0x0100>; 123 };
50 }; 124
51 125 grf: grf@20008000 {
52 L2: l2-cache-controller@10138000 { 126 compatible = "syscon";
53 compatible = "arm,pl310-cache"; 127 reg = <0x20008000 0x200>;
54 reg = <0x10138000 0x1000>; 128 };
55 cache-unified; 129
56 cache-level = <2>; 130 i2c0: i2c@2002d000 {
57 }; 131 compatible = "rockchip,rk3066-i2c";
58 132 reg = <0x2002d000 0x1000>;
59 global-timer@1013c200 { 133 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
60 compatible = "arm,cortex-a9-global-timer"; 134 #address-cells = <1>;
61 reg = <0x1013c200 0x20>; 135 #size-cells = <0>;
62 interrupts = <GIC_PPI 11 0x304>; 136
63 clocks = <&dummy150m>; 137 rockchip,grf = <&grf>;
64 }; 138 rockchip,bus-index = <0>;
65 139
66 local-timer@1013c600 { 140 clock-names = "i2c";
67 compatible = "arm,cortex-a9-twd-timer"; 141 clocks = <&cru PCLK_I2C0>;
68 reg = <0x1013c600 0x20>; 142
69 interrupts = <GIC_PPI 13 0x304>; 143 status = "disabled";
70 clocks = <&dummy150m>; 144 };
71 }; 145
72 146 i2c1: i2c@2002f000 {
73 uart0: serial@10124000 { 147 compatible = "rockchip,rk3066-i2c";
74 compatible = "snps,dw-apb-uart"; 148 reg = <0x2002f000 0x1000>;
75 reg = <0x10124000 0x400>; 149 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
76 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 150 #address-cells = <1>;
77 reg-shift = <2>; 151 #size-cells = <0>;
78 reg-io-width = <1>; 152
79 clocks = <&clk_gates1 8>; 153 rockchip,grf = <&grf>;
80 status = "disabled"; 154
81 }; 155 clocks = <&cru PCLK_I2C1>;
82 156 clock-names = "i2c";
83 uart1: serial@10126000 { 157
84 compatible = "snps,dw-apb-uart"; 158 status = "disabled";
85 reg = <0x10126000 0x400>; 159 };
86 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 160
87 reg-shift = <2>; 161 pwm0: pwm@20030000 {
88 reg-io-width = <1>; 162 compatible = "rockchip,rk2928-pwm";
89 clocks = <&clk_gates1 10>; 163 reg = <0x20030000 0x10>;
90 status = "disabled"; 164 #pwm-cells = <2>;
91 }; 165 clocks = <&cru PCLK_PWM01>;
92 166 status = "disabled";
93 uart2: serial@20064000 { 167 };
94 compatible = "snps,dw-apb-uart"; 168
95 reg = <0x20064000 0x400>; 169 pwm1: pwm@20030010 {
96 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 170 compatible = "rockchip,rk2928-pwm";
97 reg-shift = <2>; 171 reg = <0x20030010 0x10>;
98 reg-io-width = <1>; 172 #pwm-cells = <2>;
99 clocks = <&clk_gates1 12>; 173 clocks = <&cru PCLK_PWM01>;
100 status = "disabled"; 174 status = "disabled";
101 }; 175 };
102 176
103 uart3: serial@20068000 { 177 pwm2: pwm@20050020 {
104 compatible = "snps,dw-apb-uart"; 178 compatible = "rockchip,rk2928-pwm";
105 reg = <0x20068000 0x400>; 179 reg = <0x20050020 0x10>;
106 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 180 #pwm-cells = <2>;
107 reg-shift = <2>; 181 clocks = <&cru PCLK_PWM23>;
108 reg-io-width = <1>; 182 status = "disabled";
109 clocks = <&clk_gates1 14>; 183 };
110 status = "disabled"; 184
111 }; 185 pwm3: pwm@20050030 {
112 186 compatible = "rockchip,rk2928-pwm";
113 dwmmc@10214000 { 187 reg = <0x20050030 0x10>;
114 compatible = "rockchip,rk2928-dw-mshc"; 188 #pwm-cells = <2>;
115 reg = <0x10214000 0x1000>; 189 clocks = <&cru PCLK_PWM23>;
116 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 190 status = "disabled";
117 #address-cells = <1>; 191 };
118 #size-cells = <0>; 192
119 193 i2c2: i2c@20056000 {
120 clocks = <&clk_gates5 10>, <&clk_gates2 11>; 194 compatible = "rockchip,rk3066-i2c";
121 clock-names = "biu", "ciu"; 195 reg = <0x20056000 0x1000>;
122 196 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
123 status = "disabled"; 197 #address-cells = <1>;
124 }; 198 #size-cells = <0>;
125 199
126 dwmmc@10218000 { 200 rockchip,grf = <&grf>;
127 compatible = "rockchip,rk2928-dw-mshc"; 201
128 reg = <0x10218000 0x1000>; 202 clocks = <&cru PCLK_I2C2>;
129 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 203 clock-names = "i2c";
130 #address-cells = <1>; 204
131 #size-cells = <0>; 205 status = "disabled";
132 206 };
133 clocks = <&clk_gates5 11>, <&clk_gates2 13>; 207
134 clock-names = "biu", "ciu"; 208 i2c3: i2c@2005a000 {
135 209 compatible = "rockchip,rk3066-i2c";
136 status = "disabled"; 210 reg = <0x2005a000 0x1000>;
137 }; 211 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
212 #address-cells = <1>;
213 #size-cells = <0>;
214
215 rockchip,grf = <&grf>;
216
217 clocks = <&cru PCLK_I2C3>;
218 clock-names = "i2c";
219
220 status = "disabled";
221 };
222
223 i2c4: i2c@2005e000 {
224 compatible = "rockchip,rk3066-i2c";
225 reg = <0x2005e000 0x1000>;
226 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
227 #address-cells = <1>;
228 #size-cells = <0>;
229
230 rockchip,grf = <&grf>;
231
232 clocks = <&cru PCLK_I2C4>;
233 clock-names = "i2c";
234
235 status = "disabled";
236 };
237
238 uart2: serial@20064000 {
239 compatible = "snps,dw-apb-uart";
240 reg = <0x20064000 0x400>;
241 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
242 reg-shift = <2>;
243 reg-io-width = <1>;
244 clock-names = "baudclk", "apb_pclk";
245 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
246 status = "disabled";
247 };
248
249 uart3: serial@20068000 {
250 compatible = "snps,dw-apb-uart";
251 reg = <0x20068000 0x400>;
252 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
253 reg-shift = <2>;
254 reg-io-width = <1>;
255 clock-names = "baudclk", "apb_pclk";
256 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
257 status = "disabled";
138 }; 258 };
139}; 259};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 18:17:14 -0400