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authorPeter De Schrijver <pdeschrijver@nvidia.com>2014-06-12 11:36:38 -0400
committerThierry Reding <treding@nvidia.com>2014-07-17 08:36:10 -0400
commit155dfc7b543345ed45521900bbd32c0db4ea266e (patch)
tree28f05e49cf046f33d04e62626af83e03d6c2d58c
parent783c8f4c84451bc444e314a71b447239c6ef6fd9 (diff)
soc/tegra: Add efuse and apbmisc bindings
Add efuse and apbmisc bindings for Tegra20, Tegra30, Tegra114 and Tegra124. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt40
-rw-r--r--Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt13
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi15
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi15
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi15
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi15
6 files changed, 113 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
new file mode 100644
index 000000000000..d8c98c7614d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt
@@ -0,0 +1,40 @@
1NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
2
3Required properties:
4- compatible : should be:
5 "nvidia,tegra20-efuse"
6 "nvidia,tegra30-efuse"
7 "nvidia,tegra114-efuse"
8 "nvidia,tegra124-efuse"
9 Details:
10 nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
11 due to a hardware bug. Tegra20 also lacks certain information which is
12 available in later generations such as fab code, lot code, wafer id,..
13 nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
14 The differences between these SoCs are the size of the efuse array,
15 the location of the spare (OEM programmable) bits and the location of
16 the speedo data.
17- reg: Should contain 1 entry: the entry gives the physical address and length
18 of the fuse registers.
19- clocks: Must contain an entry for each entry in clock-names.
20 See ../clocks/clock-bindings.txt for details.
21- clock-names: Must include the following entries:
22 - fuse
23- resets: Must contain an entry for each entry in reset-names.
24 See ../reset/reset.txt for details.
25- reset-names: Must include the following entries:
26 - fuse
27
28Example:
29
30 fuse@7000f800 {
31 compatible = "nvidia,tegra20-efuse";
32 reg = <0x7000F800 0x400>,
33 <0x70000000 0x400>;
34 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
35 clock-names = "fuse";
36 resets = <&tegra_car 39>;
37 reset-names = "fuse";
38 };
39
40
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
new file mode 100644
index 000000000000..b97b8bef1fe5
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
@@ -0,0 +1,13 @@
1NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block
2
3Required properties:
4- compatible : should be:
5 "nvidia,tegra20-apbmisc"
6 "nvidia,tegra30-apbmisc"
7 "nvidia,tegra114-apbmisc"
8 "nvidia,tegra124-apbmisc"
9- reg: Should contain 2 entries: the first entry gives the physical address
10 and length of the registers which contain revision and debug features.
11 The second entry gives the physical address and length of the
12 registers indicating the strapping options.
13
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index fdc559ab2db3..335a1d8047f2 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -220,6 +220,12 @@
220 interrupt-controller; 220 interrupt-controller;
221 }; 221 };
222 222
223 apbmisc@70000800 {
224 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
225 reg = <0x70000800 0x64 /* Chip revision */
226 0x70000008 0x04>; /* Strapping options */
227 };
228
223 pinmux: pinmux@70000868 { 229 pinmux: pinmux@70000868 {
224 compatible = "nvidia,tegra114-pinmux"; 230 compatible = "nvidia,tegra114-pinmux";
225 reg = <0x70000868 0x148 /* Pad control registers */ 231 reg = <0x70000868 0x148 /* Pad control registers */
@@ -485,6 +491,15 @@
485 clock-names = "pclk", "clk32k_in"; 491 clock-names = "pclk", "clk32k_in";
486 }; 492 };
487 493
494 fuse@7000f800 {
495 compatible = "nvidia,tegra114-efuse";
496 reg = <0x7000f800 0x400>;
497 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
498 clock-names = "fuse";
499 resets = <&tegra_car 39>;
500 reset-names = "fuse";
501 };
502
488 iommu@70019010 { 503 iommu@70019010 {
489 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; 504 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
490 reg = <0x70019010 0x02c 505 reg = <0x70019010 0x02c
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 6e6bc4e8185c..226941c07d15 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -179,6 +179,12 @@
179 #dma-cells = <1>; 179 #dma-cells = <1>;
180 }; 180 };
181 181
182 apbmisc@0,70000800 {
183 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
184 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
185 <0x0 0x7000E864 0x0 0x04>; /* Strapping options */
186 };
187
182 pinmux: pinmux@0,70000868 { 188 pinmux: pinmux@0,70000868 {
183 compatible = "nvidia,tegra124-pinmux"; 189 compatible = "nvidia,tegra124-pinmux";
184 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 190 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
@@ -449,6 +455,15 @@
449 clock-names = "pclk", "clk32k_in"; 455 clock-names = "pclk", "clk32k_in";
450 }; 456 };
451 457
458 fuse@0,7000f800 {
459 compatible = "nvidia,tegra124-efuse";
460 reg = <0x0 0x7000f800 0x0 0x400>;
461 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
462 clock-names = "fuse";
463 resets = <&tegra_car 39>;
464 reset-names = "fuse";
465 };
466
452 sdhci@0,700b0000 { 467 sdhci@0,700b0000 {
453 compatible = "nvidia,tegra124-sdhci"; 468 compatible = "nvidia,tegra124-sdhci";
454 reg = <0x0 0x700b0000 0x0 0x200>; 469 reg = <0x0 0x700b0000 0x0 0x200>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index a7ddf70df50b..243d84cdbae8 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -236,6 +236,12 @@
236 interrupt-controller; 236 interrupt-controller;
237 }; 237 };
238 238
239 apbmisc@70000800 {
240 compatible = "nvidia,tegra20-apbmisc";
241 reg = <0x70000800 0x64 /* Chip revision */
242 0x70000008 0x04>; /* Strapping options */
243 };
244
239 pinmux: pinmux@70000014 { 245 pinmux: pinmux@70000014 {
240 compatible = "nvidia,tegra20-pinmux"; 246 compatible = "nvidia,tegra20-pinmux";
241 reg = <0x70000014 0x10 /* Tri-state registers */ 247 reg = <0x70000014 0x10 /* Tri-state registers */
@@ -545,6 +551,15 @@
545 #size-cells = <0>; 551 #size-cells = <0>;
546 }; 552 };
547 553
554 fuse@7000f800 {
555 compatible = "nvidia,tegra20-efuse";
556 reg = <0x7000F800 0x400>;
557 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
558 clock-names = "fuse";
559 resets = <&tegra_car 39>;
560 reset-names = "fuse";
561 };
562
548 pcie-controller@80003000 { 563 pcie-controller@80003000 {
549 compatible = "nvidia,tegra20-pcie"; 564 compatible = "nvidia,tegra20-pcie";
550 device_type = "pci"; 565 device_type = "pci";
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index dec4fc823901..0b1ede940d1f 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -335,6 +335,12 @@
335 interrupt-controller; 335 interrupt-controller;
336 }; 336 };
337 337
338 apbmisc@70000800 {
339 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
340 reg = <0x70000800 0x64 /* Chip revision */
341 0x70000008 0x04>; /* Strapping options */
342 };
343
338 pinmux: pinmux@70000868 { 344 pinmux: pinmux@70000868 {
339 compatible = "nvidia,tegra30-pinmux"; 345 compatible = "nvidia,tegra30-pinmux";
340 reg = <0x70000868 0xd4 /* Pad control registers */ 346 reg = <0x70000868 0xd4 /* Pad control registers */
@@ -631,6 +637,15 @@
631 nvidia,ahb = <&ahb>; 637 nvidia,ahb = <&ahb>;
632 }; 638 };
633 639
640 fuse@7000f800 {
641 compatible = "nvidia,tegra30-efuse";
642 reg = <0x7000f800 0x400>;
643 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
644 clock-names = "fuse";
645 resets = <&tegra_car 39>;
646 reset-names = "fuse";
647 };
648
634 ahub@70080000 { 649 ahub@70080000 {
635 compatible = "nvidia,tegra30-ahub"; 650 compatible = "nvidia,tegra30-ahub";
636 reg = <0x70080000 0x200 651 reg = <0x70080000 0x200