diff options
author | Ulf Hansson <ulf.hansson@linaro.org> | 2014-04-23 15:52:03 -0400 |
---|---|---|
committer | Vinod Koul <vinod.koul@intel.com> | 2014-05-07 02:20:27 -0400 |
commit | 123e4ca172707267eef5fbe9f0c58bd4c412685c (patch) | |
tree | e0ed3501c400acc1e474af3c2e399c42613b0c86 | |
parent | 2dafca17c8807bc622daf111ec359a4baad550f6 (diff) |
dma: ste_dma40: Convert to PM macros while providing the PM callbacks
Converting to the PM macros makes us simplify and remove some code.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r-- | drivers/dma/ste_dma40.c | 150 |
1 files changed, 71 insertions, 79 deletions
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 45e809f4acda..0b29af321873 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c | |||
@@ -1054,62 +1054,6 @@ static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len, | |||
1054 | return len; | 1054 | return len; |
1055 | } | 1055 | } |
1056 | 1056 | ||
1057 | |||
1058 | #ifdef CONFIG_PM | ||
1059 | static void dma40_backup(void __iomem *baseaddr, u32 *backup, | ||
1060 | u32 *regaddr, int num, bool save) | ||
1061 | { | ||
1062 | int i; | ||
1063 | |||
1064 | for (i = 0; i < num; i++) { | ||
1065 | void __iomem *addr = baseaddr + regaddr[i]; | ||
1066 | |||
1067 | if (save) | ||
1068 | backup[i] = readl_relaxed(addr); | ||
1069 | else | ||
1070 | writel_relaxed(backup[i], addr); | ||
1071 | } | ||
1072 | } | ||
1073 | |||
1074 | static void d40_save_restore_registers(struct d40_base *base, bool save) | ||
1075 | { | ||
1076 | int i; | ||
1077 | |||
1078 | /* Save/Restore channel specific registers */ | ||
1079 | for (i = 0; i < base->num_phy_chans; i++) { | ||
1080 | void __iomem *addr; | ||
1081 | int idx; | ||
1082 | |||
1083 | if (base->phy_res[i].reserved) | ||
1084 | continue; | ||
1085 | |||
1086 | addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA; | ||
1087 | idx = i * ARRAY_SIZE(d40_backup_regs_chan); | ||
1088 | |||
1089 | dma40_backup(addr, &base->reg_val_backup_chan[idx], | ||
1090 | d40_backup_regs_chan, | ||
1091 | ARRAY_SIZE(d40_backup_regs_chan), | ||
1092 | save); | ||
1093 | } | ||
1094 | |||
1095 | /* Save/Restore global registers */ | ||
1096 | dma40_backup(base->virtbase, base->reg_val_backup, | ||
1097 | d40_backup_regs, ARRAY_SIZE(d40_backup_regs), | ||
1098 | save); | ||
1099 | |||
1100 | /* Save/Restore registers only existing on dma40 v3 and later */ | ||
1101 | if (base->gen_dmac.backup) | ||
1102 | dma40_backup(base->virtbase, base->reg_val_backup_v4, | ||
1103 | base->gen_dmac.backup, | ||
1104 | base->gen_dmac.backup_size, | ||
1105 | save); | ||
1106 | } | ||
1107 | #else | ||
1108 | static void d40_save_restore_registers(struct d40_base *base, bool save) | ||
1109 | { | ||
1110 | } | ||
1111 | #endif | ||
1112 | |||
1113 | static int __d40_execute_command_phy(struct d40_chan *d40c, | 1057 | static int __d40_execute_command_phy(struct d40_chan *d40c, |
1114 | enum d40_command command) | 1058 | enum d40_command command) |
1115 | { | 1059 | { |
@@ -2996,8 +2940,8 @@ failure1: | |||
2996 | } | 2940 | } |
2997 | 2941 | ||
2998 | /* Suspend resume functionality */ | 2942 | /* Suspend resume functionality */ |
2999 | #ifdef CONFIG_PM | 2943 | #ifdef CONFIG_PM_SLEEP |
3000 | static int dma40_pm_suspend(struct device *dev) | 2944 | static int dma40_suspend(struct device *dev) |
3001 | { | 2945 | { |
3002 | struct platform_device *pdev = to_platform_device(dev); | 2946 | struct platform_device *pdev = to_platform_device(dev); |
3003 | struct d40_base *base = platform_get_drvdata(pdev); | 2947 | struct d40_base *base = platform_get_drvdata(pdev); |
@@ -3008,6 +2952,69 @@ static int dma40_pm_suspend(struct device *dev) | |||
3008 | return ret; | 2952 | return ret; |
3009 | } | 2953 | } |
3010 | 2954 | ||
2955 | static int dma40_resume(struct device *dev) | ||
2956 | { | ||
2957 | struct platform_device *pdev = to_platform_device(dev); | ||
2958 | struct d40_base *base = platform_get_drvdata(pdev); | ||
2959 | int ret = 0; | ||
2960 | |||
2961 | if (base->lcpa_regulator) | ||
2962 | ret = regulator_enable(base->lcpa_regulator); | ||
2963 | |||
2964 | return ret; | ||
2965 | } | ||
2966 | #endif | ||
2967 | |||
2968 | #ifdef CONFIG_PM | ||
2969 | static void dma40_backup(void __iomem *baseaddr, u32 *backup, | ||
2970 | u32 *regaddr, int num, bool save) | ||
2971 | { | ||
2972 | int i; | ||
2973 | |||
2974 | for (i = 0; i < num; i++) { | ||
2975 | void __iomem *addr = baseaddr + regaddr[i]; | ||
2976 | |||
2977 | if (save) | ||
2978 | backup[i] = readl_relaxed(addr); | ||
2979 | else | ||
2980 | writel_relaxed(backup[i], addr); | ||
2981 | } | ||
2982 | } | ||
2983 | |||
2984 | static void d40_save_restore_registers(struct d40_base *base, bool save) | ||
2985 | { | ||
2986 | int i; | ||
2987 | |||
2988 | /* Save/Restore channel specific registers */ | ||
2989 | for (i = 0; i < base->num_phy_chans; i++) { | ||
2990 | void __iomem *addr; | ||
2991 | int idx; | ||
2992 | |||
2993 | if (base->phy_res[i].reserved) | ||
2994 | continue; | ||
2995 | |||
2996 | addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA; | ||
2997 | idx = i * ARRAY_SIZE(d40_backup_regs_chan); | ||
2998 | |||
2999 | dma40_backup(addr, &base->reg_val_backup_chan[idx], | ||
3000 | d40_backup_regs_chan, | ||
3001 | ARRAY_SIZE(d40_backup_regs_chan), | ||
3002 | save); | ||
3003 | } | ||
3004 | |||
3005 | /* Save/Restore global registers */ | ||
3006 | dma40_backup(base->virtbase, base->reg_val_backup, | ||
3007 | d40_backup_regs, ARRAY_SIZE(d40_backup_regs), | ||
3008 | save); | ||
3009 | |||
3010 | /* Save/Restore registers only existing on dma40 v3 and later */ | ||
3011 | if (base->gen_dmac.backup) | ||
3012 | dma40_backup(base->virtbase, base->reg_val_backup_v4, | ||
3013 | base->gen_dmac.backup, | ||
3014 | base->gen_dmac.backup_size, | ||
3015 | save); | ||
3016 | } | ||
3017 | |||
3011 | static int dma40_runtime_suspend(struct device *dev) | 3018 | static int dma40_runtime_suspend(struct device *dev) |
3012 | { | 3019 | { |
3013 | struct platform_device *pdev = to_platform_device(dev); | 3020 | struct platform_device *pdev = to_platform_device(dev); |
@@ -3034,29 +3041,14 @@ static int dma40_runtime_resume(struct device *dev) | |||
3034 | base->virtbase + D40_DREG_GCC); | 3041 | base->virtbase + D40_DREG_GCC); |
3035 | return 0; | 3042 | return 0; |
3036 | } | 3043 | } |
3037 | 3044 | #endif | |
3038 | static int dma40_resume(struct device *dev) | ||
3039 | { | ||
3040 | struct platform_device *pdev = to_platform_device(dev); | ||
3041 | struct d40_base *base = platform_get_drvdata(pdev); | ||
3042 | int ret = 0; | ||
3043 | |||
3044 | if (base->lcpa_regulator) | ||
3045 | ret = regulator_enable(base->lcpa_regulator); | ||
3046 | |||
3047 | return ret; | ||
3048 | } | ||
3049 | 3045 | ||
3050 | static const struct dev_pm_ops dma40_pm_ops = { | 3046 | static const struct dev_pm_ops dma40_pm_ops = { |
3051 | .suspend = dma40_pm_suspend, | 3047 | SET_SYSTEM_SLEEP_PM_OPS(dma40_suspend, dma40_resume) |
3052 | .runtime_suspend = dma40_runtime_suspend, | 3048 | SET_PM_RUNTIME_PM_OPS(dma40_runtime_suspend, |
3053 | .runtime_resume = dma40_runtime_resume, | 3049 | dma40_runtime_resume, |
3054 | .resume = dma40_resume, | 3050 | NULL) |
3055 | }; | 3051 | }; |
3056 | #define DMA40_PM_OPS (&dma40_pm_ops) | ||
3057 | #else | ||
3058 | #define DMA40_PM_OPS NULL | ||
3059 | #endif | ||
3060 | 3052 | ||
3061 | /* Initialization functions. */ | 3053 | /* Initialization functions. */ |
3062 | 3054 | ||
@@ -3753,7 +3745,7 @@ static struct platform_driver d40_driver = { | |||
3753 | .driver = { | 3745 | .driver = { |
3754 | .owner = THIS_MODULE, | 3746 | .owner = THIS_MODULE, |
3755 | .name = D40_NAME, | 3747 | .name = D40_NAME, |
3756 | .pm = DMA40_PM_OPS, | 3748 | .pm = &dma40_pm_ops, |
3757 | .of_match_table = d40_match, | 3749 | .of_match_table = d40_match, |
3758 | }, | 3750 | }, |
3759 | }; | 3751 | }; |