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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-06-27 07:23:11 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-07-02 05:56:12 -0400
commit108f6af0a82cf3b61f3ac6728e2241805a935b64 (patch)
treeb7ef30935a4d632131f9b5dbc6085a106fb05cc6
parente22c12f9146d50ee6b0cf97db46b3310409f64e6 (diff)
ARM: entry: data abort: always use r6 for offset
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mm/abort-lv4t.S6
-rw-r--r--arch/arm/mm/proc-arm6_7.S6
2 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index 921aaab0c8c5..54b6d279371a 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -102,13 +102,13 @@ ENTRY(v4t_late_abort)
102 tst r8, #1 << 21 @ check writeback bit 102 tst r8, #1 << 21 @ check writeback bit
103 beq do_DataAbort @ no writeback -> no fixup 103 beq do_DataAbort @ no writeback -> no fixup
104.data_arm_lateldrpostconst: 104.data_arm_lateldrpostconst:
105 movs r9, r8, lsl #20 @ Get offset 105 movs r6, r8, lsl #20 @ Get offset
106 beq do_DataAbort @ zero -> no fixup 106 beq do_DataAbort @ zero -> no fixup
107 and r5, r8, #15 << 16 @ Extract 'n' from instruction 107 and r5, r8, #15 << 16 @ Extract 'n' from instruction
108 ldr r7, [r2, r5, lsr #14] @ Get register 'Rn' 108 ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
109 tst r8, #1 << 23 @ Check U bit 109 tst r8, #1 << 23 @ Check U bit
110 subne r7, r7, r9, lsr #20 @ Undo increment 110 subne r7, r7, r6, lsr #20 @ Undo increment
111 addeq r7, r7, r9, lsr #20 @ Undo decrement 111 addeq r7, r7, r6, lsr #20 @ Undo decrement
112 str r7, [r2, r5, lsr #14] @ Put register 'Rn' 112 str r7, [r2, r5, lsr #14] @ Put register 'Rn'
113 b do_DataAbort 113 b do_DataAbort
114 114
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 141906eae260..4d963114c66b 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -116,13 +116,13 @@ ENTRY(cpu_arm6_data_abort)
116 tst r8, #1 << 21 @ check writeback bit 116 tst r8, #1 << 21 @ check writeback bit
117 beq do_DataAbort @ no writeback -> no fixup 117 beq do_DataAbort @ no writeback -> no fixup
118.data_arm_lateldrpostconst: 118.data_arm_lateldrpostconst:
119 movs r9, r8, lsl #20 @ Get offset 119 movs r6, r8, lsl #20 @ Get offset
120 beq do_DataAbort @ zero -> no fixup 120 beq do_DataAbort @ zero -> no fixup
121 and r5, r8, #15 << 16 @ Extract 'n' from instruction 121 and r5, r8, #15 << 16 @ Extract 'n' from instruction
122 ldr r7, [r2, r5, lsr #14] @ Get register 'Rn' 122 ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
123 tst r8, #1 << 23 @ Check U bit 123 tst r8, #1 << 23 @ Check U bit
124 subne r7, r7, r9, lsr #20 @ Undo increment 124 subne r7, r7, r6, lsr #20 @ Undo increment
125 addeq r7, r7, r9, lsr #20 @ Undo decrement 125 addeq r7, r7, r6, lsr #20 @ Undo decrement
126 str r7, [r2, r5, lsr #14] @ Put register 'Rn' 126 str r7, [r2, r5, lsr #14] @ Put register 'Rn'
127 b do_DataAbort 127 b do_DataAbort
128 128