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authorArnd Bergmann <arnd@arndb.de>2014-03-17 06:08:40 -0400
committerArnd Bergmann <arnd@arndb.de>2014-03-17 07:21:17 -0400
commit0f4d5641a65b4a8428a4b9a7ad6f0ed580863e19 (patch)
tree1a21edd7844f8cf3993fe0e94f7e460c8b4d9e06
parent64d865f403914afc5cc661aa1412e46715a8d51b (diff)
parent4de29e636946dbc97586de6136a3c496a55fd5e6 (diff)
Merge tag 'mvebu-dt-3.15-5' of git://git.infradead.org/linux-mvebu into next/dt
Merge "mvebu dt changes for v3.15 (incremental #5)" from Jason Cooper: - mvebu - 38x - add 2GHz fixed clock, core divider clock, and nand controller - 385 - add nand controller and partitions to 385-DB board * tag 'mvebu-dt-3.15-5' of git://git.infradead.org/linux-mvebu: ARM: mvebu: Enable NAND controller in Armada 385-DB ARM: mvebu: Add support for NAND controller in Armada 38x SoC ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r--arch/arm/boot/dts/armada-385-db.dts21
-rw-r--r--arch/arm/boot/dts/armada-38x.dtsi25
2 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
index 9a136428ec29..6828d77696a6 100644
--- a/arch/arm/boot/dts/armada-385-db.dts
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -80,6 +80,27 @@
80 reg = <1>; 80 reg = <1>;
81 }; 81 };
82 }; 82 };
83
84 flash@d0000 {
85 status = "okay";
86 num-cs = <1>;
87 marvell,nand-keep-config;
88 marvell,nand-enable-arbiter;
89 nand-on-flash-bbt;
90
91 partition@0 {
92 label = "U-Boot";
93 reg = <0 0x800000>;
94 };
95 partition@800000 {
96 label = "Linux";
97 reg = <0x800000 0x800000>;
98 };
99 partition@1000000 {
100 label = "Filesystem";
101 reg = <0x1000000 0x3f000000>;
102 };
103 };
83 }; 104 };
84 105
85 pcie-controller { 106 pcie-controller {
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 812ce280b349..a064f59da02d 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -337,10 +337,35 @@
337 compatible = "marvell,orion-mdio"; 337 compatible = "marvell,orion-mdio";
338 reg = <0x72004 0x4>; 338 reg = <0x72004 0x4>;
339 }; 339 };
340
341 coredivclk: clock@e4250 {
342 compatible = "marvell,armada-380-corediv-clock";
343 reg = <0xe4250 0xc>;
344 #clock-cells = <1>;
345 clocks = <&mainpll>;
346 clock-output-names = "nand";
347 };
348
349 flash@d0000 {
350 compatible = "marvell,armada370-nand";
351 reg = <0xd0000 0x54>;
352 #address-cells = <1>;
353 #size-cells = <1>;
354 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&coredivclk 0>;
356 status = "disabled";
357 };
340 }; 358 };
341 }; 359 };
342 360
343 clocks { 361 clocks {
362 /* 2 GHz fixed main PLL */
363 mainpll: mainpll {
364 compatible = "fixed-clock";
365 #clock-cells = <0>;
366 clock-frequency = <2000000000>;
367 };
368
344 /* 25 MHz reference crystal */ 369 /* 25 MHz reference crystal */
345 refclk: oscillator { 370 refclk: oscillator {
346 compatible = "fixed-clock"; 371 compatible = "fixed-clock";