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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2014-02-17 09:23:28 -0500
committerJason Cooper <jason@lakedaemon.net>2014-02-17 17:50:20 -0500
commit0d3d96ab0059074a18dbb5fc2f9df859c06019bf (patch)
tree4a69c326d62413f25fee5457fdec1cce075a62e2
parent44e255a5844dcb84d7e9bfab96c6493ce98dca67 (diff)
ARM: mvebu: add Device Tree description of the Armada 380/385 SoCs
The Armada 380 and 385 SoCs are new SoCs from Marvell, based on a Cortex-A9 cores (single core for 380, dual core for 385) and a number of hardware blocks that are common with earlier SoCs from the mvebu family. The provided Device Tree describes the following parts of the SoC: * CPU * Device Bus * Clocks * Interrupt controllers: GIC and MPIC * GPIO controllers * I2C buses * L2 cache * MBus controller * Pinctrl * Serial * SPI buses * System controller (for reboot) * Timer * XOR engines * PCIe controllers * Network interfaces Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat
-rw-r--r--arch/arm/boot/dts/armada-380.dtsi117
-rw-r--r--arch/arm/boot/dts/armada-385.dtsi149
-rw-r--r--arch/arm/boot/dts/armada-38x.dtsi345
3 files changed, 611 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
new file mode 100644
index 000000000000..5a46ec7d207b
--- /dev/null
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -0,0 +1,117 @@
1/*
2 * Device Tree Include file for Marvell Armada 380 SoC.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15/include/ "armada-38x.dtsi"
16
17/ {
18 model = "Marvell Armada 380 family SoC";
19 compatible = "marvell,armada380", "marvell,armada38x";
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a9";
27 reg = <0>;
28 };
29 };
30
31 soc {
32 internal-regs {
33 pinctrl {
34 compatible = "marvell,mv88f6810-pinctrl";
35 reg = <0x18000 0x20>;
36 };
37 };
38
39 pcie-controller {
40 compatible = "marvell,armada-370-pcie";
41 status = "disabled";
42 device_type = "pci";
43
44 #address-cells = <3>;
45 #size-cells = <2>;
46
47 msi-parent = <&mpic>;
48 bus-range = <0x00 0xff>;
49
50 ranges =
51 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
53 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
54 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
55 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
56 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
57 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
58 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
59 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
60 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
61
62 /* x1 port */
63 pcie@1,0 {
64 device_type = "pci";
65 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
66 reg = <0x0800 0 0 0 0>;
67 #address-cells = <3>;
68 #size-cells = <2>;
69 #interrupt-cells = <1>;
70 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
71 0x81000000 0 0 0x81000000 0x1 0 1 0>;
72 interrupt-map-mask = <0 0 0 0>;
73 interrupt-map = <0 0 0 0 &gic 0 29 0x4>;
74 marvell,pcie-port = <0>;
75 marvell,pcie-lane = <0>;
76 clocks = <&gateclk 8>;
77 status = "disabled";
78 };
79
80 /* x1 port */
81 pcie@2,0 {
82 device_type = "pci";
83 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
84 reg = <0x1000 0 0 0 0>;
85 #address-cells = <3>;
86 #size-cells = <2>;
87 #interrupt-cells = <1>;
88 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
89 0x81000000 0 0 0x81000000 0x2 0 1 0>;
90 interrupt-map-mask = <0 0 0 0>;
91 interrupt-map = <0 0 0 0 &gic 0 33 0x4>;
92 marvell,pcie-port = <1>;
93 marvell,pcie-lane = <0>;
94 clocks = <&gateclk 5>;
95 status = "disabled";
96 };
97
98 /* x1 port */
99 pcie@3,0 {
100 device_type = "pci";
101 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
102 reg = <0x1000 0 0 0 0>;
103 #address-cells = <3>;
104 #size-cells = <2>;
105 #interrupt-cells = <1>;
106 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
107 0x81000000 0 0 0x81000000 0x3 0 1 0>;
108 interrupt-map-mask = <0 0 0 0>;
109 interrupt-map = <0 0 0 0 &gic 0 70 0x4>;
110 marvell,pcie-port = <2>;
111 marvell,pcie-lane = <0>;
112 clocks = <&gateclk 6>;
113 status = "disabled";
114 };
115 };
116 };
117};
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
new file mode 100644
index 000000000000..b22f5f1bd337
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -0,0 +1,149 @@
1/*
2 * Device Tree Include file for Marvell Armada 385 SoC.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include "armada-38x.dtsi"
16
17/ {
18 model = "Marvell Armada 385 family SoC";
19 compatible = "marvell,armada385", "marvell,armada38x";
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a9";
27 reg = <0>;
28 };
29 cpu@1 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a9";
32 reg = <1>;
33 };
34 };
35
36 soc {
37 internal-regs {
38 pinctrl {
39 compatible = "marvell,mv88f6820-pinctrl";
40 reg = <0x18000 0x20>;
41 };
42 };
43
44 pcie-controller {
45 compatible = "marvell,armada-370-pcie";
46 status = "disabled";
47 device_type = "pci";
48
49 #address-cells = <3>;
50 #size-cells = <2>;
51
52 msi-parent = <&mpic>;
53 bus-range = <0x00 0xff>;
54
55 ranges =
56 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
57 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
58 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
59 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
60 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
61 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
62 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
63 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
64 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
65 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
66 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
67 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
68
69 /*
70 * This port can be either x4 or x1. When
71 * configured in x4 by the bootloader, then
72 * pcie@4,0 is not available.
73 */
74 pcie@1,0 {
75 device_type = "pci";
76 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
77 reg = <0x0800 0 0 0 0>;
78 #address-cells = <3>;
79 #size-cells = <2>;
80 #interrupt-cells = <1>;
81 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
82 0x81000000 0 0 0x81000000 0x1 0 1 0>;
83 interrupt-map-mask = <0 0 0 0>;
84 interrupt-map = <0 0 0 0 &gic 0 29 0x4>;
85 marvell,pcie-port = <0>;
86 marvell,pcie-lane = <0>;
87 clocks = <&gateclk 8>;
88 status = "disabled";
89 };
90
91 /* x1 port */
92 pcie@2,0 {
93 device_type = "pci";
94 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
95 reg = <0x1000 0 0 0 0>;
96 #address-cells = <3>;
97 #size-cells = <2>;
98 #interrupt-cells = <1>;
99 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
100 0x81000000 0 0 0x81000000 0x2 0 1 0>;
101 interrupt-map-mask = <0 0 0 0>;
102 interrupt-map = <0 0 0 0 &gic 0 33 0x4>;
103 marvell,pcie-port = <1>;
104 marvell,pcie-lane = <0>;
105 clocks = <&gateclk 5>;
106 status = "disabled";
107 };
108
109 /* x1 port */
110 pcie@3,0 {
111 device_type = "pci";
112 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
113 reg = <0x1000 0 0 0 0>;
114 #address-cells = <3>;
115 #size-cells = <2>;
116 #interrupt-cells = <1>;
117 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
118 0x81000000 0 0 0x81000000 0x3 0 1 0>;
119 interrupt-map-mask = <0 0 0 0>;
120 interrupt-map = <0 0 0 0 &gic 0 70 0x4>;
121 marvell,pcie-port = <2>;
122 marvell,pcie-lane = <0>;
123 clocks = <&gateclk 6>;
124 status = "disabled";
125 };
126
127 /*
128 * x1 port only available when pcie@1,0 is
129 * configured as a x1 port
130 */
131 pcie@4,0 {
132 device_type = "pci";
133 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
134 reg = <0x1000 0 0 0 0>;
135 #address-cells = <3>;
136 #size-cells = <2>;
137 #interrupt-cells = <1>;
138 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
139 0x81000000 0 0 0x81000000 0x4 0 1 0>;
140 interrupt-map-mask = <0 0 0 0>;
141 interrupt-map = <0 0 0 0 &gic 0 71 0x4>;
142 marvell,pcie-port = <3>;
143 marvell,pcie-lane = <0>;
144 clocks = <&gateclk 7>;
145 status = "disabled";
146 };
147 };
148 };
149};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
new file mode 100644
index 000000000000..5a10248f4bb9
--- /dev/null
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -0,0 +1,345 @@
1/*
2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include "skeleton.dtsi"
16
17#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
18
19/ {
20 model = "Marvell Armada 38x family SoC";
21 compatible = "marvell,armada38x";
22
23 aliases {
24 gpio0 = &gpio0;
25 gpio1 = &gpio1;
26 eth0 = &eth0;
27 eth1 = &eth1;
28 eth2 = &eth2;
29 };
30
31 soc {
32 compatible = "marvell,armada380-mbus", "marvell,armada370-mbus",
33 "simple-bus";
34 #address-cells = <2>;
35 #size-cells = <1>;
36 controller = <&mbusc>;
37 interrupt-parent = <&gic>;
38 pcie-mem-aperture = <0xe0000000 0x8000000>;
39 pcie-io-aperture = <0xe8000000 0x100000>;
40
41 bootrom {
42 compatible = "marvell,bootrom";
43 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
44 };
45
46 devbus-bootcs {
47 compatible = "marvell,mvebu-devbus";
48 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
49 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
50 #address-cells = <1>;
51 #size-cells = <1>;
52 clocks = <&coreclk 0>;
53 status = "disabled";
54 };
55
56 devbus-cs0 {
57 compatible = "marvell,mvebu-devbus";
58 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
59 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
60 #address-cells = <1>;
61 #size-cells = <1>;
62 clocks = <&coreclk 0>;
63 status = "disabled";
64 };
65
66 devbus-cs1 {
67 compatible = "marvell,mvebu-devbus";
68 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
69 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
70 #address-cells = <1>;
71 #size-cells = <1>;
72 clocks = <&coreclk 0>;
73 status = "disabled";
74 };
75
76 devbus-cs2 {
77 compatible = "marvell,mvebu-devbus";
78 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
79 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
80 #address-cells = <1>;
81 #size-cells = <1>;
82 clocks = <&coreclk 0>;
83 status = "disabled";
84 };
85
86 devbus-cs3 {
87 compatible = "marvell,mvebu-devbus";
88 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
89 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
90 #address-cells = <1>;
91 #size-cells = <1>;
92 clocks = <&coreclk 0>;
93 status = "disabled";
94 };
95
96 internal-regs {
97 compatible = "simple-bus";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
101
102 L2: cache-controller@8000 {
103 compatible = "arm,pl310-cache";
104 reg = <0x8000 0x1000>;
105 cache-unified;
106 cache-level = <2>;
107 };
108
109 timer@c600 {
110 compatible = "arm,cortex-a9-twd-timer";
111 reg = <0xc600 0x20>;
112 interrupts = <1 13 0x301>;
113 clocks = <&coreclk 2>;
114 };
115
116 gic: interrupt-controller@d000 {
117 compatible = "arm,cortex-a9-gic";
118 #interrupt-cells = <3>;
119 #size-cells = <0>;
120 interrupt-controller;
121 reg = <0xd000 0x1000>,
122 <0xc100 0x100>;
123 };
124
125 spi0: spi@10600 {
126 compatible = "marvell,orion-spi";
127 reg = <0x10600 0x50>;
128 #address-cells = <1>;
129 #size-cells = <0>;
130 cell-index = <0>;
131 interrupts = <0 1 0x4>;
132 clocks = <&coreclk 0>;
133 status = "disabled";
134 };
135
136 spi1: spi@10680 {
137 compatible = "marvell,orion-spi";
138 reg = <0x10680 0x50>;
139 #address-cells = <1>;
140 #size-cells = <0>;
141 cell-index = <1>;
142 interrupts = <0 63 0x4>;
143 clocks = <&coreclk 0>;
144 status = "disabled";
145 };
146
147 i2c0: i2c@11000 {
148 compatible = "marvell,mv64xxx-i2c";
149 reg = <0x11000 0x20>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 interrupts = <0 2 0x4>;
153 timeout-ms = <1000>;
154 clocks = <&coreclk 0>;
155 status = "disabled";
156 };
157
158 i2c1: i2c@11100 {
159 compatible = "marvell,mv64xxx-i2c";
160 reg = <0x11100 0x20>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 interrupts = <0 3 0x4>;
164 timeout-ms = <1000>;
165 clocks = <&coreclk 0>;
166 status = "disabled";
167 };
168
169 serial@12000 {
170 compatible = "snps,dw-apb-uart";
171 reg = <0x12000 0x100>;
172 reg-shift = <2>;
173 interrupts = <0 12 4>;
174 reg-io-width = <1>;
175 status = "disabled";
176 };
177
178 serial@12100 {
179 compatible = "snps,dw-apb-uart";
180 reg = <0x12100 0x100>;
181 reg-shift = <2>;
182 interrupts = <0 13 4>;
183 reg-io-width = <1>;
184 status = "disabled";
185 };
186
187 pinctrl {
188 compatible = "marvell,mv88f6820-pinctrl";
189 reg = <0x18000 0x20>;
190 };
191
192 gpio0: gpio@18100 {
193 compatible = "marvell,orion-gpio";
194 reg = <0x18100 0x40>;
195 ngpios = <32>;
196 gpio-controller;
197 #gpio-cells = <2>;
198 interrupt-controller;
199 #interrupt-cells = <2>;
200 interrupts = <0 53 0x4>, <0 54 0x4>,
201 <0 55 0x4>, <0 56 0x4>;
202 };
203
204 gpio1: gpio@18140 {
205 compatible = "marvell,orion-gpio";
206 reg = <0x18140 0x40>;
207 ngpios = <28>;
208 gpio-controller;
209 #gpio-cells = <2>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
212 interrupts = <0 58 0x4>, <0 59 0x4>,
213 <0 60 0x4>, <0 61 0x4>;
214 };
215
216 system-controller@18200 {
217 compatible = "marvell,armada-380-system-controller",
218 "marvell,armada-370-xp-system-controller";
219 reg = <0x18200 0x100>;
220 };
221
222 gateclk: clock-gating-control@18220 {
223 compatible = "marvell,armada-380-gating-clock";
224 reg = <0x18220 0x4>;
225 clocks = <&coreclk 0>;
226 #clock-cells = <1>;
227 };
228
229 coreclk: mvebu-sar@18600 {
230 compatible = "marvell,armada-380-core-clock";
231 reg = <0x18600 0x04>;
232 #clock-cells = <1>;
233 };
234
235 mbusc: mbus-controller@20000 {
236 compatible = "marvell,mbus-controller";
237 reg = <0x20000 0x100>, <0x20180 0x20>;
238 };
239
240 mpic: interrupt-controller@20000 {
241 compatible = "marvell,mpic";
242 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
243 #interrupt-cells = <1>;
244 #size-cells = <1>;
245 interrupt-controller;
246 msi-controller;
247 interrupts = <1 15 0x4>;
248 };
249
250 timer@20300 {
251 compatible = "marvell,armada-380-timer",
252 "marvell,armada-xp-timer";
253 reg = <0x20300 0x30>, <0x21040 0x30>;
254 interrupts-extended = <&gic 0 8 4>,
255 <&gic 0 9 4>,
256 <&gic 0 10 4>,
257 <&gic 0 11 4>,
258 <&mpic 5>,
259 <&mpic 6>;
260 clocks = <&coreclk 2>, <&refclk>;
261 clock-names = "nbclk", "fixed";
262 };
263
264 eth1: ethernet@30000 {
265 compatible = "marvell,armada-370-neta";
266 reg = <0x30000 0x4000>;
267 interrupts-extended = <&mpic 10>;
268 clocks = <&gateclk 3>;
269 status = "disabled";
270 };
271
272 eth2: ethernet@34000 {
273 compatible = "marvell,armada-370-neta";
274 reg = <0x34000 0x4000>;
275 interrupts-extended = <&mpic 12>;
276 clocks = <&gateclk 2>;
277 status = "disabled";
278 };
279
280 xor@60800 {
281 compatible = "marvell,orion-xor";
282 reg = <0x60800 0x100
283 0x60a00 0x100>;
284 clocks = <&gateclk 22>;
285 status = "okay";
286
287 xor00 {
288 interrupts = <0 22 0x4>;
289 dmacap,memcpy;
290 dmacap,xor;
291 };
292 xor01 {
293 interrupts = <0 23 0x4>;
294 dmacap,memcpy;
295 dmacap,xor;
296 dmacap,memset;
297 };
298 };
299
300 xor@60900 {
301 compatible = "marvell,orion-xor";
302 reg = <0x60900 0x100
303 0x60b00 0x100>;
304 clocks = <&gateclk 28>;
305 status = "okay";
306
307 xor10 {
308 interrupts = <0 65 0x4>;
309 dmacap,memcpy;
310 dmacap,xor;
311 };
312 xor11 {
313 interrupts = <0 66 0x4>;
314 dmacap,memcpy;
315 dmacap,xor;
316 dmacap,memset;
317 };
318 };
319
320 eth0: ethernet@70000 {
321 compatible = "marvell,armada-370-neta";
322 reg = <0x70000 0x4000>;
323 interrupts-extended = <&mpic 8>;
324 clocks = <&gateclk 4>;
325 status = "disabled";
326 };
327
328 mdio {
329 #address-cells = <1>;
330 #size-cells = <0>;
331 compatible = "marvell,orion-mdio";
332 reg = <0x72004 0x4>;
333 };
334 };
335 };
336
337 clocks {
338 /* 25 MHz reference crystal */
339 refclk: oscillator {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <25000000>;
343 };
344 };
345};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 08:53:33 -0400