drm: Replace pitch with pitches[] in drm_framebuffer

Otherwise each driver would need to keep the information inside
their own framebuffer object structure. Also add offsets[]. BOs
on the other hand are driver specific, so those can be kept in
driver specific structures.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

22 files changed, 64 insertions, 58 deletions

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 07d78e27ec3d..0d1faa72e1ff 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2292,7 +2292,7 @@ int drm_mode_getfb(struct drm_device *dev,
         r->width = fb->width;
         r->depth = fb->depth;
         r->bpp = fb->bits_per_pixel;
-        r->pitch = fb->pitch;
+        r->pitch = fb->pitches[0];
         fb->funcs->create_handle(fb, file_priv, &r->handle);
 
 out:
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 2ce61d72d416..ccbdc0b5854c 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -814,9 +814,14 @@ EXPORT_SYMBOL(drm_helper_connector_dpms);
 int drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
                                    struct drm_mode_fb_cmd2 *mode_cmd)
 {
+        int i;
+
         fb->width = mode_cmd->width;
         fb->height = mode_cmd->height;
-        fb->pitch = mode_cmd->pitches[0];
+        for (i = 0; i < 4; i++) {
+                fb->pitches[i] = mode_cmd->pitches[i];
+                fb->offsets[i] = mode_cmd->offsets[i];
+        }
         drm_fb_get_bpp_depth(mode_cmd->pixel_format, &fb->depth,
                                     &fb->bits_per_pixel);
         fb->pixel_format = mode_cmd->pixel_format;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 9337e5e2dbb6..73893e5068a4 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -119,7 +119,7 @@ static int exynos_drm_overlay_update(struct exynos_drm_overlay *overlay,
         overlay->fb_width = fb->width;
         overlay->fb_height = fb->height;
         overlay->bpp = fb->bits_per_pixel;
-        overlay->pitch = fb->pitch;
+        overlay->pitch = fb->pitches[0];
 
         /* set overlay range to be displayed. */
         overlay->crtc_x = pos->crtc_x;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index 1f4b3d1a7713..81fba29b696d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -100,7 +100,7 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper,
 
         exynos_fb->fb = fb;
 
-        drm_fb_helper_fill_fix(fbi, fb->pitch, fb->depth);
+        drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->depth);
         drm_fb_helper_fill_var(fbi, helper, fb_width, fb_height);
 
         entry = exynos_drm_fb_get_buf(fb);
@@ -110,7 +110,7 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper,
         }
 
         offset = fbi->var.xoffset * (fb->bits_per_pixel >> 3);
-        offset += fbi->var.yoffset * fb->pitch;
+        offset += fbi->var.yoffset * fb->pitches[0];
 
         dev->mode_config.fb_base = entry->paddr;
         fbi->screen_base = entry->vaddr + offset;
diff --git a/drivers/gpu/drm/gma500/accel_2d.c b/drivers/gpu/drm/gma500/accel_2d.c
index f0ce82aed654..d5ef1a5793c8 100644
--- a/drivers/gpu/drm/gma500/accel_2d.c
+++ b/drivers/gpu/drm/gma500/accel_2d.c
@@ -253,7 +253,7 @@ static void psbfb_copyarea_accel(struct fb_info *info,
                 return;
 
         offset = psbfb->gtt->offset;
-        stride = fb->pitch;
+        stride = fb->pitches[0];
 
         switch (fb->depth) {
         case 8:
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c
index 7b97c600eff0..c63a32776a9e 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -507,9 +507,9 @@ int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
         if (ret < 0)
                 goto psb_intel_pipe_set_base_exit;
         start = psbfb->gtt->offset;
-        offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
+        offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
 
-        REG_WRITE(dspstride, crtc->fb->pitch);
+        REG_WRITE(dspstride, crtc->fb->pitches[0]);
 
         dspcntr = REG_READ(dspcntr_reg);
         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c
index 9ec167600d04..75cfafe2ff81 100644
--- a/drivers/gpu/drm/gma500/framebuffer.c
+++ b/drivers/gpu/drm/gma500/framebuffer.c
@@ -500,7 +500,7 @@ static int psbfb_create(struct psb_fbdev *fbdev,
                 info->apertures->ranges[0].size = dev_priv->gtt.stolen_size;
         }
 
-        drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
+        drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
         drm_fb_helper_fill_var(info, &fbdev->psb_fb_helper,
                                 sizes->fb_width, sizes->fb_height);
 
diff --git a/drivers/gpu/drm/gma500/oaktrail_crtc.c b/drivers/gpu/drm/gma500/oaktrail_crtc.c
index 8e15b5af1213..fe17e1f000bf 100644
--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
+++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
@@ -543,9 +543,9 @@ int oaktrail_pipe_set_base(struct drm_crtc *crtc,
                 return 0;
 
         start = psbfb->gtt->offset;
-        offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
+        offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
 
-        REG_WRITE(dspstride, crtc->fb->pitch);
+        REG_WRITE(dspstride, crtc->fb->pitches[0]);
 
         dspcntr = REG_READ(dspcntr_reg);
         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c b/drivers/gpu/drm/gma500/psb_intel_display.c
index ab650765a647..7bc0edee9c0d 100644
--- a/drivers/gpu/drm/gma500/psb_intel_display.c
+++ b/drivers/gpu/drm/gma500/psb_intel_display.c
@@ -365,9 +365,9 @@ int psb_intel_pipe_set_base(struct drm_crtc *crtc,
                 goto psb_intel_pipe_set_base_exit;
         start = psbfb->gtt->offset;
 
-        offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
+        offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
 
-        REG_WRITE(dspstride, crtc->fb->pitch);
+        REG_WRITE(dspstride, crtc->fb->pitches[0]);
 
         dspcntr = REG_READ(dspcntr_reg);
         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9ee2729fe5c6..96643ee240da 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1204,7 +1204,7 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
         } else {
                 int dspaddr = DSPADDR(intel_crtc->plane);
                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
-                                                        crtc->y * crtc->fb->pitch +
+                                                        crtc->y * crtc->fb->pitches[0] +
                                                         crtc->x * crtc->fb->bits_per_pixel/8);
         }
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5dd9bf60bce0..8ecbc2f11633 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1511,8 +1511,8 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
         u32 fbc_ctl, fbc_ctl2;
 
         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
-        if (fb->pitch < cfb_pitch)
-                cfb_pitch = fb->pitch;
+        if (fb->pitches[0] < cfb_pitch)
+                cfb_pitch = fb->pitches[0];
 
         /* FBC_CTL wants 64B units */
         cfb_pitch = (cfb_pitch / 64) - 1;
@@ -2073,11 +2073,11 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
         I915_WRITE(reg, dspcntr);
 
         Start = obj->gtt_offset;
-        Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
+        Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
 
         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
-                      Start, Offset, x, y, fb->pitch);
-        I915_WRITE(DSPSTRIDE(plane), fb->pitch);
+                      Start, Offset, x, y, fb->pitches[0]);
+        I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
         if (INTEL_INFO(dev)->gen >= 4) {
                 I915_WRITE(DSPSURF(plane), Start);
                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
@@ -2154,11 +2154,11 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
         I915_WRITE(reg, dspcntr);
 
         Start = obj->gtt_offset;
-        Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
+        Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
 
         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
-                      Start, Offset, x, y, fb->pitch);
-        I915_WRITE(DSPSTRIDE(plane), fb->pitch);
+                      Start, Offset, x, y, fb->pitches[0]);
+        I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
         I915_WRITE(DSPSURF(plane), Start);
         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
         I915_WRITE(DSPADDR(plane), Offset);
@@ -6353,11 +6353,11 @@ mode_fits_in_fbdev(struct drm_device *dev,
                 return NULL;
 
         fb = &dev_priv->fbdev->ifb.base;
-        if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
-                                                          fb->bits_per_pixel))
+        if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
+                                                               fb->bits_per_pixel))
                 return NULL;
 
-        if (obj->base.size < mode->vdisplay * fb->pitch)
+        if (obj->base.size < mode->vdisplay * fb->pitches[0])
                 return NULL;
 
         return fb;
@@ -6990,7 +6990,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
                 goto out;
 
         /* Offset into the new buffer for cases of shared fbs between CRTCs */
-        offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
+        offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
 
         ret = BEGIN_LP_RING(6);
         if (ret)
@@ -7007,7 +7007,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
         OUT_RING(MI_NOOP);
         OUT_RING(MI_DISPLAY_FLIP |
                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-        OUT_RING(fb->pitch);
+        OUT_RING(fb->pitches[0]);
         OUT_RING(obj->gtt_offset + offset);
         OUT_RING(MI_NOOP);
         ADVANCE_LP_RING();
@@ -7031,7 +7031,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
                 goto out;
 
         /* Offset into the new buffer for cases of shared fbs between CRTCs */
-        offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
+        offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
 
         ret = BEGIN_LP_RING(6);
         if (ret)
@@ -7045,7 +7045,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
         OUT_RING(MI_NOOP);
         OUT_RING(MI_DISPLAY_FLIP_I915 |
                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-        OUT_RING(fb->pitch);
+        OUT_RING(fb->pitches[0]);
         OUT_RING(obj->gtt_offset + offset);
         OUT_RING(MI_NOOP);
 
@@ -7078,7 +7078,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
          */
         OUT_RING(MI_DISPLAY_FLIP |
                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-        OUT_RING(fb->pitch);
+        OUT_RING(fb->pitches[0]);
         OUT_RING(obj->gtt_offset | obj->tiling_mode);
 
         /* XXX Enabling the panel-fitter across page-flip is so far
@@ -7113,7 +7113,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
 
         OUT_RING(MI_DISPLAY_FLIP |
                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-        OUT_RING(fb->pitch | obj->tiling_mode);
+        OUT_RING(fb->pitches[0] | obj->tiling_mode);
         OUT_RING(obj->gtt_offset);
 
         pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
@@ -7149,7 +7149,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
                 goto out;
 
         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
-        intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
+        intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
         intel_ring_emit(ring, (obj->gtt_offset));
         intel_ring_emit(ring, (MI_NOOP));
         intel_ring_advance(ring);
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index dc1db4ff4245..f02fc71a57a5 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -149,7 +149,7 @@ static int intelfb_create(struct intel_fbdev *ifbdev,
 
 //      memset(info->screen_base, 0, size);
 
-        drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
+        drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
         drm_fb_helper_fill_var(info, &ifbdev->helper, sizes->fb_width, sizes->fb_height);
 
         info->pixmap.size = 64*1024;
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 7687a77f01d1..2531ef54c3e9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -107,14 +107,14 @@ nouveau_framebuffer_init(struct drm_device *dev,
 
                 if (!tile_flags) {
                         if (dev_priv->card_type < NV_D0)
-                                nv_fb->r_pitch = 0x00100000 | fb->pitch;
+                                nv_fb->r_pitch = 0x00100000 | fb->pitches[0];
                         else
-                                nv_fb->r_pitch = 0x01000000 | fb->pitch;
+                                nv_fb->r_pitch = 0x01000000 | fb->pitches[0];
                 } else {
                         u32 mode = nvbo->tile_mode;
                         if (dev_priv->card_type >= NV_C0)
                                 mode >>= 4;
-                        nv_fb->r_pitch = ((fb->pitch / 4) << 4) | mode;
+                        nv_fb->r_pitch = ((fb->pitches[0] / 4) << 4) | mode;
                 }
         }
 
@@ -294,7 +294,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
         /* Initialize a page flip struct */
         *s = (struct nouveau_page_flip_state)
                 { { }, event, nouveau_crtc(crtc)->index,
-                  fb->bits_per_pixel, fb->pitch, crtc->x, crtc->y,
+                  fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y,
                   new_bo->bo.offset };
 
         /* Choose the channel the flip will be handled in */
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index d663065181bf..defffd140781 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -370,7 +370,7 @@ nouveau_fbcon_create(struct nouveau_fbdev *nfbdev,
         info->screen_base = nvbo_kmap_obj_iovirtual(nouveau_fb->nvbo);
         info->screen_size = size;
 
-        drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
+        drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
         drm_fb_helper_fill_var(info, &nfbdev->helper, sizes->fb_width, sizes->fb_height);
 
         /* Set aperture base/size for vesafb takeover */
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index 5e45398a9e2d..728d07584d39 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -364,7 +364,7 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
         regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
         regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
         /* framebuffer can be larger than crtc scanout area. */
-        regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitch / 8;
+        regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
         regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
         regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
         regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
@@ -377,9 +377,9 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
 
         /* framebuffer can be larger than crtc scanout area. */
         regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
-                XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
+                XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
         regp->CRTC[NV_CIO_CRE_42] =
-                XLATE(fb->pitch / 8, 11, NV_CIO_CRE_42_OFFSET_11);
+                XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
         regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
                                             MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
         regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
@@ -835,18 +835,18 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
         NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
                       regp->ramdac_gen_ctrl);
 
-        regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitch >> 3;
+        regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
         regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
-                XLATE(drm_fb->pitch >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
+                XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
         regp->CRTC[NV_CIO_CRE_42] =
-                XLATE(drm_fb->pitch / 8, 11, NV_CIO_CRE_42_OFFSET_11);
+                XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
         crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
 
         /* Update the framebuffer location. */
         regp->fb_start = nv_crtc->fb.offset & ~3;
-        regp->fb_start += (y * drm_fb->pitch) + (x * drm_fb->bits_per_pixel / 8);
+        regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8);
         nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
 
         /* Update the arbitration parameters. */
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 87921c88a95c..7567ff2510e0 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1153,7 +1153,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
 
-        fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
+        fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 
@@ -1322,7 +1322,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
 
-        fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
+        fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 96d9ba96c87d..d3ffc18774a6 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -406,7 +406,7 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
         if (!ASIC_IS_AVIVO(rdev)) {
                 /* crtc offset is from display base addr not FB location */
                 base -= radeon_crtc->legacy_display_base_addr;
-                pitch_pixels = fb->pitch / (fb->bits_per_pixel / 8);
+                pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 
                 if (tiling_flags & RADEON_TILING_MACRO) {
                         if (ASIC_IS_R300(rdev)) {
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 0dc749eb4222..cf2bf35b56b8 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -232,7 +232,7 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev,
 
         strcpy(info->fix.id, "radeondrmfb");
 
-        drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
+        drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
 
         info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
         info->fbops = &radeonfb_ops;
@@ -275,7 +275,7 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev,
         DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
         DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
         DRM_INFO("fb depth is %d\n", fb->depth);
-        DRM_INFO("   pitch is %d\n", fb->pitch);
+        DRM_INFO("   pitch is %d\n", fb->pitches[0]);
 
         vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
         return 0;
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 41a5d48e657b..95b93604b679 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -437,7 +437,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 
         crtc_offset_cntl = 0;
 
-        pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
+        pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
         crtc_pitch  = (((pitch_pixels * target_fb->bits_per_pixel) +
                         ((target_fb->bits_per_pixel * 8) - 1)) /
                        (target_fb->bits_per_pixel * 8));
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 760d04aee380..0585987f2945 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -605,7 +605,7 @@ static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
 
         /* XXX get the first 3 from the surface info */
         vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
-        vfbs->base.base.pitch = mode_cmd->pitch;
+        vfbs->base.base.pitches[0] = mode_cmd->pitch;
         vfbs->base.base.depth = mode_cmd->depth;
         vfbs->base.base.width = mode_cmd->width;
         vfbs->base.base.height = mode_cmd->height;
@@ -719,7 +719,7 @@ static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
         cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
         cmd->body.format.colorDepth = depth;
         cmd->body.format.reserved = 0;
-        cmd->body.bytesPerLine = framebuffer->base.pitch;
+        cmd->body.bytesPerLine = framebuffer->base.pitches[0];
         cmd->body.ptr.gmrId = framebuffer->user_handle;
         cmd->body.ptr.offset = 0;
 
@@ -961,7 +961,7 @@ static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
         }
 
         vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
-        vfbd->base.base.pitch = mode_cmd->pitch;
+        vfbd->base.base.pitches[0] = mode_cmd->pitch;
         vfbd->base.base.depth = mode_cmd->depth;
         vfbd->base.base.width = mode_cmd->width;
         vfbd->base.base.height = mode_cmd->height;
@@ -1243,7 +1243,7 @@ int vmw_kms_readback(struct vmw_private *dev_priv,
         cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
         cmd->body.format.colorDepth = vfb->base.depth;
         cmd->body.format.reserved = 0;
-        cmd->body.bytesPerLine = vfb->base.pitch;
+        cmd->body.bytesPerLine = vfb->base.pitches[0];
         cmd->body.ptr.gmrId = vfb->user_handle;
         cmd->body.ptr.offset = 0;
 
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
index 90c5e3928491..15a6805e48b0 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
@@ -94,7 +94,7 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv)
                         return 0;
                 fb = entry->base.crtc.fb;
 
-                return vmw_kms_write_svga(dev_priv, w, h, fb->pitch,
+                return vmw_kms_write_svga(dev_priv, w, h, fb->pitches[0],
                                           fb->bits_per_pixel, fb->depth);
         }
 
@@ -102,7 +102,7 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv)
                 entry = list_entry(lds->active.next, typeof(*entry), active);
                 fb = entry->base.crtc.fb;
 
-                vmw_kms_write_svga(dev_priv, fb->width, fb->height, fb->pitch,
+                vmw_kms_write_svga(dev_priv, fb->width, fb->height, fb->pitches[0],
                                    fb->bits_per_pixel, fb->depth);
         }
 
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 42c89b201ffd..2deb6f99f950 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -239,7 +239,8 @@ struct drm_framebuffer {
         struct list_head head;
         struct drm_mode_object base;
         const struct drm_framebuffer_funcs *funcs;
-        unsigned int pitch;
+        unsigned int pitches[4];
+        unsigned int offsets[4];
         unsigned int width;
         unsigned int height;
         /* depth can be 15 or 16 */