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authorArnd Bergmann <arnd@arndb.de>2014-11-28 10:18:18 -0500
committerArnd Bergmann <arnd@arndb.de>2014-11-28 10:18:18 -0500
commit00239d9da38419792494ce7d2bb69a4ee8b5b374 (patch)
tree58976abf01ffe581899ae48d879239c3dac17590
parente155aee2b279b099da5c5cfd6df5795e7388ece1 (diff)
parent4a109c50d1958a2783df01980b55508fe47bb79c (diff)
Merge tag 'at91-cleanup4' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/cleanup
Pull "Fourth batch of cleanup/SoC for 3.19" from Nicolas Ferre: - removal of legacy board support for the last SoC having board C files: at91rm9200 - removal or modification of some Kconfig options - switch to USE_OF for all the AT91 SoCs - removal of the old AT91-specific clocks and IRQ drivers * tag 'at91-cleanup4' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: ARM: at91: remove unused IRQ function declarations ARM: at91: remove legacy IRQ driver and related code ARM: at91: remove old at91-specific clock driver ARM: at91: remove clock data in at91sam9n12.c and at91sam9x5.c files ARM: at91: remove all !DT related configuration options ARM: at91/trivial: update Kconfig comment to mention SAMA5 ARM: at91: always USE_OF from now on ARM: at91/Kconfig: remove ARCH_AT91RM9200 option for drivers ARM: at91: switch configuration option to SOC_AT91RM9200 ARM: at91: remove at91rm9200 legacy board support ARM: at91: remove at91rm9200 legacy boards files Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm/Kconfig5
-rw-r--r--arch/arm/configs/at91rm9200_defconfig161
-rw-r--r--arch/arm/mach-at91/Kconfig34
-rw-r--r--arch/arm/mach-at91/Kconfig.non_dt114
-rw-r--r--arch/arm/mach-at91/Makefile19
-rw-r--r--arch/arm/mach-at91/at91_aic.h99
-rw-r--r--arch/arm/mach-at91/at91rm9200.c341
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c1212
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c213
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c311
-rw-r--r--arch/arm/mach-at91/board-1arm.c99
-rw-r--r--arch/arm/mach-at91/board-carmeva.c167
-rw-r--r--arch/arm/mach-at91/board-cpuat91.c189
-rw-r--r--arch/arm/mach-at91/board-csb337.c260
-rw-r--r--arch/arm/mach-at91/board-csb637.c142
-rw-r--r--arch/arm/mach-at91/board-dt-rm9200.c1
-rw-r--r--arch/arm/mach-at91/board-dt-sam9.c1
-rw-r--r--arch/arm/mach-at91/board-dt-sama5.c1
-rw-r--r--arch/arm/mach-at91/board-eb9200.c126
-rw-r--r--arch/arm/mach-at91/board-ecbat91.c191
-rw-r--r--arch/arm/mach-at91/board-eco920.c160
-rw-r--r--arch/arm/mach-at91/board-kafa.c113
-rw-r--r--arch/arm/mach-at91/board-kb9202.c159
-rw-r--r--arch/arm/mach-at91/board-picotux200.c129
-rw-r--r--arch/arm/mach-at91/board-rm9200ek.c196
-rw-r--r--arch/arm/mach-at91/board-yl-9200.c597
-rw-r--r--arch/arm/mach-at91/clock.c977
-rw-r--r--arch/arm/mach-at91/clock.h49
-rw-r--r--arch/arm/mach-at91/generic.h17
-rw-r--r--arch/arm/mach-at91/irq.c296
-rw-r--r--arch/arm/mach-at91/pm.c22
-rw-r--r--arch/arm/mach-at91/setup.c13
-rw-r--r--drivers/net/ethernet/cadence/Kconfig2
-rw-r--r--drivers/rtc/Kconfig2
-rw-r--r--drivers/watchdog/Kconfig4
35 files changed, 19 insertions, 6403 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6c6fdb8a36e1..fd4515ca8358 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -378,10 +378,11 @@ config ARCH_AT91
378 select IRQ_DOMAIN 378 select IRQ_DOMAIN
379 select NEED_MACH_IO_H if PCCARD 379 select NEED_MACH_IO_H if PCCARD
380 select PINCTRL 380 select PINCTRL
381 select PINCTRL_AT91 if USE_OF 381 select PINCTRL_AT91
382 select USE_OF
382 help 383 help
383 This enables support for systems based on Atmel 384 This enables support for systems based on Atmel
384 AT91RM9200 and AT91SAM9* processors. 385 AT91RM9200, AT91SAM9 and SAMA5 processors.
385 386
386config ARCH_CLPS711X 387config ARCH_CLPS711X
387 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 388 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
deleted file mode 100644
index bf057719dab0..000000000000
--- a/arch/arm/configs/at91rm9200_defconfig
+++ /dev/null
@@ -1,161 +0,0 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y
4CONFIG_NO_HZ=y
5CONFIG_HIGH_RES_TIMERS=y
6CONFIG_IKCONFIG=y
7CONFIG_IKCONFIG_PROC=y
8CONFIG_LOG_BUF_SHIFT=14
9CONFIG_USER_NS=y
10CONFIG_BLK_DEV_INITRD=y
11CONFIG_MODULES=y
12CONFIG_MODULE_FORCE_LOAD=y
13CONFIG_MODULE_UNLOAD=y
14CONFIG_MODVERSIONS=y
15CONFIG_MODULE_SRCVERSION_ALL=y
16# CONFIG_BLK_DEV_BSG is not set
17# CONFIG_IOSCHED_CFQ is not set
18CONFIG_ARCH_AT91=y
19CONFIG_ARCH_AT91RM9200=y
20CONFIG_MACH_ONEARM=y
21CONFIG_MACH_AT91RM9200EK=y
22CONFIG_MACH_CSB337=y
23CONFIG_MACH_CSB637=y
24CONFIG_MACH_CARMEVA=y
25CONFIG_MACH_ATEB9200=y
26CONFIG_MACH_KB9200=y
27CONFIG_MACH_PICOTUX2XX=y
28CONFIG_MACH_KAFA=y
29CONFIG_MACH_ECBAT91=y
30CONFIG_MACH_YL9200=y
31CONFIG_MACH_CPUAT91=y
32CONFIG_MACH_ECO920=y
33CONFIG_MTD_AT91_DATAFLASH_CARD=y
34CONFIG_AT91_TIMER_HZ=100
35# CONFIG_ARM_THUMB is not set
36CONFIG_PCCARD=y
37CONFIG_AT91_CF=y
38CONFIG_AEABI=y
39# CONFIG_COMPACTION is not set
40CONFIG_ZBOOT_ROM_TEXT=0x10000000
41CONFIG_ZBOOT_ROM_BSS=0x20040000
42CONFIG_KEXEC=y
43CONFIG_AUTO_ZRELADDR=y
44CONFIG_FPE_NWFPE=y
45CONFIG_BINFMT_MISC=y
46CONFIG_NET=y
47CONFIG_PACKET=y
48CONFIG_UNIX=y
49CONFIG_INET=y
50CONFIG_IP_MULTICAST=y
51CONFIG_IP_PNP=y
52CONFIG_IP_PNP_DHCP=y
53CONFIG_IP_PNP_BOOTP=y
54# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
55# CONFIG_INET_XFRM_MODE_TUNNEL is not set
56# CONFIG_INET_XFRM_MODE_BEET is not set
57# CONFIG_INET_DIAG is not set
58CONFIG_IPV6=y
59CONFIG_IPV6_PRIVACY=y
60CONFIG_IPV6_ROUTER_PREF=y
61CONFIG_IPV6_ROUTE_INFO=y
62CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
63CONFIG_DEVTMPFS=y
64CONFIG_DEVTMPFS_MOUNT=y
65# CONFIG_STANDALONE is not set
66# CONFIG_PREVENT_FIRMWARE_BUILD is not set
67CONFIG_MTD=y
68CONFIG_MTD_CMDLINE_PARTS=y
69CONFIG_MTD_CHAR=y
70CONFIG_MTD_BLOCK=y
71CONFIG_MTD_CFI=y
72CONFIG_MTD_JEDECPROBE=y
73CONFIG_MTD_CFI_INTELEXT=y
74CONFIG_MTD_CFI_AMDSTD=y
75CONFIG_MTD_COMPLEX_MAPPINGS=y
76CONFIG_MTD_PHYSMAP=y
77CONFIG_MTD_PLATRAM=y
78CONFIG_MTD_DATAFLASH=y
79CONFIG_MTD_NAND=y
80CONFIG_MTD_NAND_ATMEL=y
81CONFIG_MTD_NAND_PLATFORM=y
82CONFIG_MTD_UBI=y
83CONFIG_MTD_UBI_GLUEBI=y
84CONFIG_BLK_DEV_LOOP=y
85CONFIG_BLK_DEV_RAM=y
86CONFIG_BLK_DEV_RAM_SIZE=8192
87CONFIG_NETDEVICES=y
88CONFIG_MII=y
89CONFIG_ARM_AT91_ETHER=y
90CONFIG_DAVICOM_PHY=y
91CONFIG_SMSC_PHY=y
92CONFIG_MICREL_PHY=y
93# CONFIG_WLAN is not set
94# CONFIG_INPUT_MOUSEDEV is not set
95CONFIG_INPUT_EVDEV=y
96CONFIG_KEYBOARD_GPIO=y
97# CONFIG_INPUT_MOUSE is not set
98CONFIG_INPUT_TOUCHSCREEN=y
99# CONFIG_LEGACY_PTYS is not set
100CONFIG_SERIAL_ATMEL=y
101CONFIG_SERIAL_ATMEL_CONSOLE=y
102CONFIG_HW_RANDOM=y
103CONFIG_I2C=y
104CONFIG_I2C_CHARDEV=y
105CONFIG_I2C_GPIO=y
106CONFIG_SPI=y
107CONFIG_SPI_ATMEL=y
108CONFIG_GPIO_SYSFS=y
109# CONFIG_HWMON is not set
110CONFIG_WATCHDOG=y
111CONFIG_WATCHDOG_NOWAYOUT=y
112CONFIG_AT91RM9200_WATCHDOG=y
113CONFIG_FB=y
114CONFIG_FB_MODE_HELPERS=y
115CONFIG_FB_TILEBLITTING=y
116CONFIG_FB_S1D13XXX=y
117CONFIG_BACKLIGHT_LCD_SUPPORT=y
118CONFIG_LCD_CLASS_DEVICE=y
119CONFIG_BACKLIGHT_CLASS_DEVICE=y
120# CONFIG_BACKLIGHT_GENERIC is not set
121CONFIG_FRAMEBUFFER_CONSOLE=y
122CONFIG_FONTS=y
123CONFIG_LOGO=y
124CONFIG_USB=y
125CONFIG_USB_OHCI_HCD=y
126CONFIG_USB_GADGET=y
127CONFIG_USB_AT91=y
128CONFIG_USB_G_SERIAL=y
129CONFIG_MMC=y
130CONFIG_MMC_ATMELMCI=y
131CONFIG_NEW_LEDS=y
132CONFIG_LEDS_CLASS=y
133CONFIG_LEDS_GPIO=y
134CONFIG_LEDS_TRIGGERS=y
135CONFIG_LEDS_TRIGGER_TIMER=y
136CONFIG_LEDS_TRIGGER_HEARTBEAT=y
137CONFIG_LEDS_TRIGGER_GPIO=y
138CONFIG_RTC_CLASS=y
139CONFIG_RTC_DRV_AT91RM9200=y
140CONFIG_EXT4_FS=y
141CONFIG_AUTOFS4_FS=y
142CONFIG_VFAT_FS=y
143CONFIG_TMPFS=y
144CONFIG_UBIFS_FS=y
145CONFIG_UBIFS_FS_ADVANCED_COMPR=y
146CONFIG_NFS_FS=y
147CONFIG_ROOT_NFS=y
148CONFIG_NLS_CODEPAGE_437=y
149CONFIG_NLS_CODEPAGE_850=y
150CONFIG_NLS_ISO8859_1=y
151CONFIG_NLS_UTF8=y
152CONFIG_MAGIC_SYSRQ=y
153CONFIG_DEBUG_FS=y
154CONFIG_DEBUG_KERNEL=y
155# CONFIG_FTRACE is not set
156CONFIG_DEBUG_USER=y
157CONFIG_DEBUG_LL=y
158CONFIG_EARLY_PRINTK=y
159CONFIG_CRYPTO_PCBC=y
160CONFIG_CRYPTO_SHA1=y
161CONFIG_XZ_DEC_ARMTHUMB=y
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 162a88930a8b..231893d71658 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -15,23 +15,10 @@ config HAVE_AT91_DBGU1
15config HAVE_AT91_DBGU2 15config HAVE_AT91_DBGU2
16 bool 16 bool
17 17
18config AT91_USE_OLD_CLK
19 bool
20
21config COMMON_CLK_AT91 18config COMMON_CLK_AT91
22 bool 19 bool
23 default USE_OF && !AT91_USE_OLD_CLK
24 select COMMON_CLK 20 select COMMON_CLK
25 21
26config OLD_CLK_AT91
27 bool
28 default AT91_USE_OLD_CLK
29
30config OLD_IRQ_AT91
31 bool
32 select MULTI_IRQ_HANDLER
33 select SPARSE_IRQ
34
35config HAVE_AT91_SMD 22config HAVE_AT91_SMD
36 bool 23 bool
37 24
@@ -40,18 +27,19 @@ config HAVE_AT91_H32MX
40 27
41config SOC_AT91SAM9 28config SOC_AT91SAM9
42 bool 29 bool
43 select ATMEL_AIC_IRQ if !OLD_IRQ_AT91 30 select ATMEL_AIC_IRQ
31 select COMMON_CLK_AT91
44 select CPU_ARM926T 32 select CPU_ARM926T
45 select GENERIC_CLOCKEVENTS 33 select GENERIC_CLOCKEVENTS
46 select MEMORY if USE_OF 34 select MEMORY
47 select ATMEL_SDRAMC if USE_OF 35 select ATMEL_SDRAMC
48 36
49config SOC_SAMA5 37config SOC_SAMA5
50 bool 38 bool
51 select ATMEL_AIC5_IRQ 39 select ATMEL_AIC5_IRQ
40 select COMMON_CLK_AT91
52 select CPU_V7 41 select CPU_V7
53 select GENERIC_CLOCKEVENTS 42 select GENERIC_CLOCKEVENTS
54 select USE_OF
55 select MEMORY 43 select MEMORY
56 select ATMEL_SDRAMC 44 select ATMEL_SDRAMC
57 select PHYLIB if NETDEVICES 45 select PHYLIB if NETDEVICES
@@ -109,7 +97,8 @@ endif
109if SOC_SAM_V4_V5 97if SOC_SAM_V4_V5
110config SOC_AT91RM9200 98config SOC_AT91RM9200
111 bool "AT91RM9200" 99 bool "AT91RM9200"
112 select ATMEL_AIC_IRQ if !OLD_IRQ_AT91 100 select ATMEL_AIC_IRQ
101 select COMMON_CLK_AT91
113 select CPU_ARM920T 102 select CPU_ARM920T
114 select GENERIC_CLOCKEVENTS 103 select GENERIC_CLOCKEVENTS
115 select HAVE_AT91_DBGU0 104 select HAVE_AT91_DBGU0
@@ -185,17 +174,11 @@ config SOC_AT91SAM9N12
185# ---------------------------------------------------------- 174# ----------------------------------------------------------
186endif # SOC_SAM_V4_V5 175endif # SOC_SAM_V4_V5
187 176
188
189if SOC_SAM_V4_V5
190source arch/arm/mach-at91/Kconfig.non_dt
191endif
192
193comment "Generic Board Type" 177comment "Generic Board Type"
194 178
195config MACH_AT91RM9200_DT 179config MACH_AT91RM9200_DT
196 bool "Atmel AT91RM9200 Evaluation Kits with device-tree support" 180 bool "Atmel AT91RM9200 Evaluation Kits with device-tree support"
197 depends on SOC_AT91RM9200 181 depends on SOC_AT91RM9200
198 select USE_OF
199 help 182 help
200 Select this if you want to experiment device-tree with 183 Select this if you want to experiment device-tree with
201 an Atmel RM9200 Evaluation Kit. 184 an Atmel RM9200 Evaluation Kit.
@@ -203,7 +186,6 @@ config MACH_AT91RM9200_DT
203config MACH_AT91SAM9_DT 186config MACH_AT91SAM9_DT
204 bool "Atmel AT91SAM Evaluation Kits with device-tree support" 187 bool "Atmel AT91SAM Evaluation Kits with device-tree support"
205 depends on SOC_AT91SAM9 188 depends on SOC_AT91SAM9
206 select USE_OF
207 help 189 help
208 Select this if you want to experiment device-tree with 190 Select this if you want to experiment device-tree with
209 an Atmel Evaluation Kit. 191 an Atmel Evaluation Kit.
@@ -229,7 +211,7 @@ config AT91_TIMER_HZ
229 int "Kernel HZ (jiffies per second)" 211 int "Kernel HZ (jiffies per second)"
230 range 32 1024 212 range 32 1024
231 depends on ARCH_AT91 213 depends on ARCH_AT91
232 default "128" if ARCH_AT91RM9200 214 default "128" if SOC_AT91RM9200
233 default "100" 215 default "100"
234 help 216 help
235 On AT91rm9200 chips where you're using a system clock derived 217 On AT91rm9200 chips where you're using a system clock derived
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
deleted file mode 100644
index 5fc138da89fb..000000000000
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ /dev/null
@@ -1,114 +0,0 @@
1menu "Atmel Non-DT world"
2
3config HAVE_AT91_DATAFLASH_CARD
4 bool
5
6choice
7 prompt "Atmel AT91 Processor Devices for non DT boards"
8
9config ARCH_AT91_NONE
10 bool "None"
11
12config ARCH_AT91RM9200
13 bool "AT91RM9200"
14 select SOC_AT91RM9200
15 select AT91_USE_OLD_CLK
16 select OLD_IRQ_AT91
17
18endchoice
19
20# ----------------------------------------------------------
21
22if ARCH_AT91RM9200
23
24comment "AT91RM9200 Board Type"
25
26config MACH_ONEARM
27 bool "Ajeco 1ARM Single Board Computer"
28 help
29 Select this if you are using Ajeco's 1ARM Single Board Computer.
30 <http://www.ajeco.fi/>
31
32config MACH_AT91RM9200EK
33 bool "Atmel AT91RM9200-EK Evaluation Kit"
34 select HAVE_AT91_DATAFLASH_CARD
35 help
36 Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
37 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
38
39config MACH_CSB337
40 bool "Cogent CSB337"
41 help
42 Select this if you are using Cogent's CSB337 board.
43 <http://www.cogcomp.com/csb_csb337.htm>
44
45config MACH_CSB637
46 bool "Cogent CSB637"
47 help
48 Select this if you are using Cogent's CSB637 board.
49 <http://www.cogcomp.com/csb_csb637.htm>
50
51config MACH_CARMEVA
52 bool "Conitec ARM&EVA"
53 help
54 Select this if you are using Conitec's AT91RM9200-MCU-Module.
55 <http://www.conitec.net/english/linuxboard.php>
56
57config MACH_ATEB9200
58 bool "Embest ATEB9200"
59 help
60 Select this if you are using Embest's ATEB9200 board.
61 <http://www.embedinfo.com/english/product/ATEB9200.asp>
62
63config MACH_KB9200
64 bool "KwikByte KB920x"
65 help
66 Select this if you are using KwikByte's KB920x board.
67 <http://www.kwikbyte.com/KB9202.html>
68
69config MACH_PICOTUX2XX
70 bool "picotux 200"
71 help
72 Select this if you are using a picotux 200.
73 <http://www.picotux.com/>
74
75config MACH_KAFA
76 bool "Sperry-Sun KAFA board"
77 help
78 Select this if you are using Sperry-Sun's KAFA board.
79
80config MACH_ECBAT91
81 bool "emQbit ECB_AT91 SBC"
82 select HAVE_AT91_DATAFLASH_CARD
83 help
84 Select this if you are using emQbit's ECB_AT91 board.
85 <http://wiki.emqbit.com/free-ecb-at91>
86
87config MACH_YL9200
88 bool "ucDragon YL-9200"
89 help
90 Select this if you are using the ucDragon YL-9200 board.
91
92config MACH_CPUAT91
93 bool "Eukrea CPUAT91"
94 help
95 Select this if you are using the Eukrea Electromatique's
96 CPUAT91 board <http://www.eukrea.com/>.
97
98config MACH_ECO920
99 bool "eco920"
100 help
101 Select this if you are using the eco920 board
102endif
103
104# ----------------------------------------------------------
105
106comment "AT91 Board Options"
107
108config MTD_AT91_DATAFLASH_CARD
109 bool "Enable DataFlash Card support"
110 depends on HAVE_AT91_DATAFLASH_CARD
111 help
112 Enable support for the DataFlash card.
113
114endmenu
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index b2495d71f7ac..2371b8845bf5 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -4,8 +4,6 @@
4 4
5obj-y := gpio.o setup.o sysirq_mask.o 5obj-y := gpio.o setup.o sysirq_mask.o
6 6
7obj-$(CONFIG_OLD_IRQ_AT91) += irq.o
8obj-$(CONFIG_OLD_CLK_AT91) += clock.o
9obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o 7obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
10 8
11# CPU-specific support 9# CPU-specific support
@@ -20,23 +18,6 @@ obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
20obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o 18obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
21obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o 19obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
22 20
23obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
24
25# AT91RM9200 board-specific support
26obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
27obj-$(CONFIG_MACH_AT91RM9200EK) += board-rm9200ek.o
28obj-$(CONFIG_MACH_CSB337) += board-csb337.o
29obj-$(CONFIG_MACH_CSB637) += board-csb637.o
30obj-$(CONFIG_MACH_CARMEVA) += board-carmeva.o
31obj-$(CONFIG_MACH_KB9200) += board-kb9202.o
32obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o
33obj-$(CONFIG_MACH_KAFA) += board-kafa.o
34obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o
35obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o
36obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o
37obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o
38obj-$(CONFIG_MACH_ECO920) += board-eco920.o
39
40# AT91SAM board with device-tree 21# AT91SAM board with device-tree
41obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o 22obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
42obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o 23obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
diff --git a/arch/arm/mach-at91/at91_aic.h b/arch/arm/mach-at91/at91_aic.h
deleted file mode 100644
index eaea66197fa1..000000000000
--- a/arch/arm/mach-at91/at91_aic.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_aic.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Advanced Interrupt Controller (AIC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_AIC_H
17#define AT91_AIC_H
18
19#ifndef __ASSEMBLY__
20extern void __iomem *at91_aic_base;
21
22#define at91_aic_read(field) \
23 __raw_readl(at91_aic_base + field)
24
25#define at91_aic_write(field, value) \
26 __raw_writel(value, at91_aic_base + field)
27#else
28.extern at91_aic_base
29#endif
30
31/* Number of irq lines managed by AIC */
32#define NR_AIC_IRQS 32
33#define NR_AIC5_IRQS 128
34
35#define AT91_AIC5_SSR 0x0 /* Source Select Register [AIC5] */
36#define AT91_AIC5_INTSEL_MSK (0x7f << 0) /* Interrupt Line Selection Mask */
37
38#define AT91_AIC_IRQ_MIN_PRIORITY 0
39#define AT91_AIC_IRQ_MAX_PRIORITY 7
40
41#define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */
42#define AT91_AIC5_SMR 0x4 /* Source Mode Register [AIC5] */
43#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
44#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
45#define AT91_AIC_SRCTYPE_LOW (0 << 5)
46#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
47#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
48#define AT91_AIC_SRCTYPE_RISING (3 << 5)
49
50#define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
51#define AT91_AIC5_SVR 0x8 /* Source Vector Register [AIC5] */
52#define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */
53#define AT91_AIC5_IVR 0x10 /* Interrupt Vector Register [AIC5] */
54#define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */
55#define AT91_AIC5_FVR 0x14 /* Fast Interrupt Vector Register [AIC5] */
56#define AT91_AIC_ISR 0x108 /* Interrupt Status Register */
57#define AT91_AIC5_ISR 0x18 /* Interrupt Status Register [AIC5] */
58#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
59
60#define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */
61#define AT91_AIC5_IPR0 0x20 /* Interrupt Pending Register 0 [AIC5] */
62#define AT91_AIC5_IPR1 0x24 /* Interrupt Pending Register 1 [AIC5] */
63#define AT91_AIC5_IPR2 0x28 /* Interrupt Pending Register 2 [AIC5] */
64#define AT91_AIC5_IPR3 0x2c /* Interrupt Pending Register 3 [AIC5] */
65#define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */
66#define AT91_AIC5_IMR 0x30 /* Interrupt Mask Register [AIC5] */
67#define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */
68#define AT91_AIC5_CISR 0x34 /* Core Interrupt Status Register [AIC5] */
69#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
70#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
71
72#define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */
73#define AT91_AIC5_IECR 0x40 /* Interrupt Enable Command Register [AIC5] */
74#define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */
75#define AT91_AIC5_IDCR 0x44 /* Interrupt Disable Command Register [AIC5] */
76#define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */
77#define AT91_AIC5_ICCR 0x48 /* Interrupt Clear Command Register [AIC5] */
78#define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */
79#define AT91_AIC5_ISCR 0x4c /* Interrupt Set Command Register [AIC5] */
80#define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */
81#define AT91_AIC5_EOICR 0x38 /* End of Interrupt Command Register [AIC5] */
82#define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */
83#define AT91_AIC5_SPU 0x3c /* Spurious Interrupt Vector Register [AIC5] */
84#define AT91_AIC_DCR 0x138 /* Debug Control Register */
85#define AT91_AIC5_DCR 0x6c /* Debug Control Register [AIC5] */
86#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
87#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
88
89#define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */
90#define AT91_AIC5_FFER 0x50 /* Fast Forcing Enable Register [AIC5] */
91#define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */
92#define AT91_AIC5_FFDR 0x54 /* Fast Forcing Disable Register [AIC5] */
93#define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */
94#define AT91_AIC5_FFSR 0x58 /* Fast Forcing Status Register [AIC5] */
95
96void at91_aic_handle_irq(struct pt_regs *regs);
97void at91_aic5_handle_irq(struct pt_regs *regs);
98
99#endif
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 038702ee8bc6..b52916947535 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -11,296 +11,15 @@
11 */ 11 */
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/reboot.h>
15#include <linux/clk/at91_pmc.h> 14#include <linux/clk/at91_pmc.h>
16 15
17#include <asm/irq.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h> 16#include <asm/mach/map.h>
20#include <asm/system_misc.h> 17#include <asm/system_misc.h>
21#include <mach/at91rm9200.h>
22#include <mach/at91_st.h> 18#include <mach/at91_st.h>
23#include <mach/cpu.h>
24#include <mach/hardware.h> 19#include <mach/hardware.h>
25 20
26#include "at91_aic.h"
27#include "soc.h" 21#include "soc.h"
28#include "generic.h" 22#include "generic.h"
29#include "sam9_smc.h"
30#include "pm.h"
31
32#if defined(CONFIG_OLD_CLK_AT91)
33#include "clock.h"
34/* --------------------------------------------------------------------
35 * Clocks
36 * -------------------------------------------------------------------- */
37
38/*
39 * The peripheral clocks.
40 */
41static struct clk udc_clk = {
42 .name = "udc_clk",
43 .pmc_mask = 1 << AT91RM9200_ID_UDP,
44 .type = CLK_TYPE_PERIPHERAL,
45};
46static struct clk ohci_clk = {
47 .name = "ohci_clk",
48 .pmc_mask = 1 << AT91RM9200_ID_UHP,
49 .type = CLK_TYPE_PERIPHERAL,
50};
51static struct clk ether_clk = {
52 .name = "ether_clk",
53 .pmc_mask = 1 << AT91RM9200_ID_EMAC,
54 .type = CLK_TYPE_PERIPHERAL,
55};
56static struct clk mmc_clk = {
57 .name = "mci_clk",
58 .pmc_mask = 1 << AT91RM9200_ID_MCI,
59 .type = CLK_TYPE_PERIPHERAL,
60};
61static struct clk twi_clk = {
62 .name = "twi_clk",
63 .pmc_mask = 1 << AT91RM9200_ID_TWI,
64 .type = CLK_TYPE_PERIPHERAL,
65};
66static struct clk usart0_clk = {
67 .name = "usart0_clk",
68 .pmc_mask = 1 << AT91RM9200_ID_US0,
69 .type = CLK_TYPE_PERIPHERAL,
70};
71static struct clk usart1_clk = {
72 .name = "usart1_clk",
73 .pmc_mask = 1 << AT91RM9200_ID_US1,
74 .type = CLK_TYPE_PERIPHERAL,
75};
76static struct clk usart2_clk = {
77 .name = "usart2_clk",
78 .pmc_mask = 1 << AT91RM9200_ID_US2,
79 .type = CLK_TYPE_PERIPHERAL,
80};
81static struct clk usart3_clk = {
82 .name = "usart3_clk",
83 .pmc_mask = 1 << AT91RM9200_ID_US3,
84 .type = CLK_TYPE_PERIPHERAL,
85};
86static struct clk spi_clk = {
87 .name = "spi_clk",
88 .pmc_mask = 1 << AT91RM9200_ID_SPI,
89 .type = CLK_TYPE_PERIPHERAL,
90};
91static struct clk pioA_clk = {
92 .name = "pioA_clk",
93 .pmc_mask = 1 << AT91RM9200_ID_PIOA,
94 .type = CLK_TYPE_PERIPHERAL,
95};
96static struct clk pioB_clk = {
97 .name = "pioB_clk",
98 .pmc_mask = 1 << AT91RM9200_ID_PIOB,
99 .type = CLK_TYPE_PERIPHERAL,
100};
101static struct clk pioC_clk = {
102 .name = "pioC_clk",
103 .pmc_mask = 1 << AT91RM9200_ID_PIOC,
104 .type = CLK_TYPE_PERIPHERAL,
105};
106static struct clk pioD_clk = {
107 .name = "pioD_clk",
108 .pmc_mask = 1 << AT91RM9200_ID_PIOD,
109 .type = CLK_TYPE_PERIPHERAL,
110};
111static struct clk ssc0_clk = {
112 .name = "ssc0_clk",
113 .pmc_mask = 1 << AT91RM9200_ID_SSC0,
114 .type = CLK_TYPE_PERIPHERAL,
115};
116static struct clk ssc1_clk = {
117 .name = "ssc1_clk",
118 .pmc_mask = 1 << AT91RM9200_ID_SSC1,
119 .type = CLK_TYPE_PERIPHERAL,
120};
121static struct clk ssc2_clk = {
122 .name = "ssc2_clk",
123 .pmc_mask = 1 << AT91RM9200_ID_SSC2,
124 .type = CLK_TYPE_PERIPHERAL,
125};
126static struct clk tc0_clk = {
127 .name = "tc0_clk",
128 .pmc_mask = 1 << AT91RM9200_ID_TC0,
129 .type = CLK_TYPE_PERIPHERAL,
130};
131static struct clk tc1_clk = {
132 .name = "tc1_clk",
133 .pmc_mask = 1 << AT91RM9200_ID_TC1,
134 .type = CLK_TYPE_PERIPHERAL,
135};
136static struct clk tc2_clk = {
137 .name = "tc2_clk",
138 .pmc_mask = 1 << AT91RM9200_ID_TC2,
139 .type = CLK_TYPE_PERIPHERAL,
140};
141static struct clk tc3_clk = {
142 .name = "tc3_clk",
143 .pmc_mask = 1 << AT91RM9200_ID_TC3,
144 .type = CLK_TYPE_PERIPHERAL,
145};
146static struct clk tc4_clk = {
147 .name = "tc4_clk",
148 .pmc_mask = 1 << AT91RM9200_ID_TC4,
149 .type = CLK_TYPE_PERIPHERAL,
150};
151static struct clk tc5_clk = {
152 .name = "tc5_clk",
153 .pmc_mask = 1 << AT91RM9200_ID_TC5,
154 .type = CLK_TYPE_PERIPHERAL,
155};
156
157static struct clk *periph_clocks[] __initdata = {
158 &pioA_clk,
159 &pioB_clk,
160 &pioC_clk,
161 &pioD_clk,
162 &usart0_clk,
163 &usart1_clk,
164 &usart2_clk,
165 &usart3_clk,
166 &mmc_clk,
167 &udc_clk,
168 &twi_clk,
169 &spi_clk,
170 &ssc0_clk,
171 &ssc1_clk,
172 &ssc2_clk,
173 &tc0_clk,
174 &tc1_clk,
175 &tc2_clk,
176 &tc3_clk,
177 &tc4_clk,
178 &tc5_clk,
179 &ohci_clk,
180 &ether_clk,
181 // irq0 .. irq6
182};
183
184static struct clk_lookup periph_clocks_lookups[] = {
185 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
186 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
187 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
188 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
189 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
190 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
191 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
192 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
193 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
194 CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
195 CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
196 CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
197 CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
198 /* fake hclk clock */
199 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
200 CLKDEV_CON_ID("pioA", &pioA_clk),
201 CLKDEV_CON_ID("pioB", &pioB_clk),
202 CLKDEV_CON_ID("pioC", &pioC_clk),
203 CLKDEV_CON_ID("pioD", &pioD_clk),
204 /* usart lookup table for DT entries */
205 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
206 CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
207 CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
208 CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
209 CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
210 /* tc lookup table for DT entries */
211 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
212 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
213 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
214 CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
215 CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
216 CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
217 CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
218 CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", &ether_clk),
219 CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
220 CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
221 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
225};
226
227static struct clk_lookup usart_clocks_lookups[] = {
228 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
233};
234
235/*
236 * The four programmable clocks.
237 * You must configure pin multiplexing to bring these signals out.
238 */
239static struct clk pck0 = {
240 .name = "pck0",
241 .pmc_mask = AT91_PMC_PCK0,
242 .type = CLK_TYPE_PROGRAMMABLE,
243 .id = 0,
244};
245static struct clk pck1 = {
246 .name = "pck1",
247 .pmc_mask = AT91_PMC_PCK1,
248 .type = CLK_TYPE_PROGRAMMABLE,
249 .id = 1,
250};
251static struct clk pck2 = {
252 .name = "pck2",
253 .pmc_mask = AT91_PMC_PCK2,
254 .type = CLK_TYPE_PROGRAMMABLE,
255 .id = 2,
256};
257static struct clk pck3 = {
258 .name = "pck3",
259 .pmc_mask = AT91_PMC_PCK3,
260 .type = CLK_TYPE_PROGRAMMABLE,
261 .id = 3,
262};
263
264static void __init at91rm9200_register_clocks(void)
265{
266 int i;
267
268 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
269 clk_register(periph_clocks[i]);
270
271 clkdev_add_table(periph_clocks_lookups,
272 ARRAY_SIZE(periph_clocks_lookups));
273 clkdev_add_table(usart_clocks_lookups,
274 ARRAY_SIZE(usart_clocks_lookups));
275
276 clk_register(&pck0);
277 clk_register(&pck1);
278 clk_register(&pck2);
279 clk_register(&pck3);
280}
281#else
282#define at91rm9200_register_clocks NULL
283#endif
284
285/* --------------------------------------------------------------------
286 * GPIO
287 * -------------------------------------------------------------------- */
288
289static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
290 {
291 .id = AT91RM9200_ID_PIOA,
292 .regbase = AT91RM9200_BASE_PIOA,
293 }, {
294 .id = AT91RM9200_ID_PIOB,
295 .regbase = AT91RM9200_BASE_PIOB,
296 }, {
297 .id = AT91RM9200_ID_PIOC,
298 .regbase = AT91RM9200_BASE_PIOC,
299 }, {
300 .id = AT91RM9200_ID_PIOD,
301 .regbase = AT91RM9200_BASE_PIOD,
302 }
303};
304 23
305static void at91rm9200_idle(void) 24static void at91rm9200_idle(void)
306{ 25{
@@ -329,74 +48,14 @@ static void __init at91rm9200_map_io(void)
329 at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE); 48 at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
330} 49}
331 50
332static void __init at91rm9200_ioremap_registers(void)
333{
334 at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
335 at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
336 at91_pm_set_standby(at91rm9200_standby);
337}
338
339static void __init at91rm9200_initialize(void) 51static void __init at91rm9200_initialize(void)
340{ 52{
341 arm_pm_idle = at91rm9200_idle; 53 arm_pm_idle = at91rm9200_idle;
342 arm_pm_restart = at91rm9200_restart; 54 arm_pm_restart = at91rm9200_restart;
343
344 /* Initialize GPIO subsystem */
345 at91_gpio_init(at91rm9200_gpio,
346 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
347} 55}
348 56
349 57
350/* --------------------------------------------------------------------
351 * Interrupt initialization
352 * -------------------------------------------------------------------- */
353
354/*
355 * The default interrupt priority levels (0 = lowest, 7 = highest).
356 */
357static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
358 7, /* Advanced Interrupt Controller (FIQ) */
359 7, /* System Peripherals */
360 1, /* Parallel IO Controller A */
361 1, /* Parallel IO Controller B */
362 1, /* Parallel IO Controller C */
363 1, /* Parallel IO Controller D */
364 5, /* USART 0 */
365 5, /* USART 1 */
366 5, /* USART 2 */
367 5, /* USART 3 */
368 0, /* Multimedia Card Interface */
369 2, /* USB Device Port */
370 6, /* Two-Wire Interface */
371 5, /* Serial Peripheral Interface */
372 4, /* Serial Synchronous Controller 0 */
373 4, /* Serial Synchronous Controller 1 */
374 4, /* Serial Synchronous Controller 2 */
375 0, /* Timer Counter 0 */
376 0, /* Timer Counter 1 */
377 0, /* Timer Counter 2 */
378 0, /* Timer Counter 3 */
379 0, /* Timer Counter 4 */
380 0, /* Timer Counter 5 */
381 2, /* USB Host port */
382 3, /* Ethernet MAC */
383 0, /* Advanced Interrupt Controller (IRQ0) */
384 0, /* Advanced Interrupt Controller (IRQ1) */
385 0, /* Advanced Interrupt Controller (IRQ2) */
386 0, /* Advanced Interrupt Controller (IRQ3) */
387 0, /* Advanced Interrupt Controller (IRQ4) */
388 0, /* Advanced Interrupt Controller (IRQ5) */
389 0 /* Advanced Interrupt Controller (IRQ6) */
390};
391
392AT91_SOC_START(at91rm9200) 58AT91_SOC_START(at91rm9200)
393 .map_io = at91rm9200_map_io, 59 .map_io = at91rm9200_map_io,
394 .default_irq_priority = at91rm9200_default_irq_priority,
395 .extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
396 | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
397 | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
398 | (1 << AT91RM9200_ID_IRQ6),
399 .ioremap_registers = at91rm9200_ioremap_registers,
400 .register_clocks = at91rm9200_register_clocks,
401 .init = at91rm9200_initialize, 60 .init = at91rm9200_initialize,
402AT91_SOC_END 61AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
deleted file mode 100644
index 74f1eaf97801..000000000000
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ /dev/null
@@ -1,1212 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91rm9200_devices.c
3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15
16#include <linux/dma-mapping.h>
17#include <linux/gpio.h>
18#include <linux/gpio/machine.h>
19#include <linux/platform_device.h>
20#include <linux/i2c-gpio.h>
21
22#include <mach/at91rm9200.h>
23#include <mach/at91rm9200_mc.h>
24#include <mach/at91_ramc.h>
25#include <mach/hardware.h>
26
27#include "board.h"
28#include "generic.h"
29#include "gpio.h"
30
31
32/* --------------------------------------------------------------------
33 * USB Host
34 * -------------------------------------------------------------------- */
35
36#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
37static u64 ohci_dmamask = DMA_BIT_MASK(32);
38static struct at91_usbh_data usbh_data;
39
40static struct resource usbh_resources[] = {
41 [0] = {
42 .start = AT91RM9200_UHP_BASE,
43 .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
48 .end = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53static struct platform_device at91rm9200_usbh_device = {
54 .name = "at91_ohci",
55 .id = -1,
56 .dev = {
57 .dma_mask = &ohci_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &usbh_data,
60 },
61 .resource = usbh_resources,
62 .num_resources = ARRAY_SIZE(usbh_resources),
63};
64
65void __init at91_add_device_usbh(struct at91_usbh_data *data)
66{
67 int i;
68
69 if (!data)
70 return;
71
72 /* Enable overcurrent notification */
73 for (i = 0; i < data->ports; i++) {
74 if (gpio_is_valid(data->overcurrent_pin[i]))
75 at91_set_gpio_input(data->overcurrent_pin[i], 1);
76 }
77
78 usbh_data = *data;
79 platform_device_register(&at91rm9200_usbh_device);
80}
81#else
82void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83#endif
84
85
86/* --------------------------------------------------------------------
87 * USB Device (Gadget)
88 * -------------------------------------------------------------------- */
89
90#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
91static struct at91_udc_data udc_data;
92
93static struct resource udc_resources[] = {
94 [0] = {
95 .start = AT91RM9200_BASE_UDP,
96 .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
97 .flags = IORESOURCE_MEM,
98 },
99 [1] = {
100 .start = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
101 .end = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
102 .flags = IORESOURCE_IRQ,
103 },
104};
105
106static struct platform_device at91rm9200_udc_device = {
107 .name = "at91_udc",
108 .id = -1,
109 .dev = {
110 .platform_data = &udc_data,
111 },
112 .resource = udc_resources,
113 .num_resources = ARRAY_SIZE(udc_resources),
114};
115
116void __init at91_add_device_udc(struct at91_udc_data *data)
117{
118 if (!data)
119 return;
120
121 if (gpio_is_valid(data->vbus_pin)) {
122 at91_set_gpio_input(data->vbus_pin, 0);
123 at91_set_deglitch(data->vbus_pin, 1);
124 }
125 if (gpio_is_valid(data->pullup_pin))
126 at91_set_gpio_output(data->pullup_pin, 0);
127
128 udc_data = *data;
129 platform_device_register(&at91rm9200_udc_device);
130}
131#else
132void __init at91_add_device_udc(struct at91_udc_data *data) {}
133#endif
134
135
136/* --------------------------------------------------------------------
137 * Ethernet
138 * -------------------------------------------------------------------- */
139
140#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
141static u64 eth_dmamask = DMA_BIT_MASK(32);
142static struct macb_platform_data eth_data;
143
144static struct resource eth_resources[] = {
145 [0] = {
146 .start = AT91RM9200_BASE_EMAC,
147 .end = AT91RM9200_BASE_EMAC + SZ_16K - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
151 .start = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
152 .end = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
153 .flags = IORESOURCE_IRQ,
154 },
155};
156
157static struct platform_device at91rm9200_eth_device = {
158 .name = "at91_ether",
159 .id = -1,
160 .dev = {
161 .dma_mask = &eth_dmamask,
162 .coherent_dma_mask = DMA_BIT_MASK(32),
163 .platform_data = &eth_data,
164 },
165 .resource = eth_resources,
166 .num_resources = ARRAY_SIZE(eth_resources),
167};
168
169void __init at91_add_device_eth(struct macb_platform_data *data)
170{
171 if (!data)
172 return;
173
174 if (gpio_is_valid(data->phy_irq_pin)) {
175 at91_set_gpio_input(data->phy_irq_pin, 0);
176 at91_set_deglitch(data->phy_irq_pin, 1);
177 }
178
179 /* Pins used for MII and RMII */
180 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
181 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
182 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
183 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
184 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
185 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
186 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
187 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
188 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
189 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
190
191 if (!data->is_rmii) {
192 at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
193 at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
194 at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
195 at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
196 at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
197 at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
198 at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
199 at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
200 }
201
202 eth_data = *data;
203 platform_device_register(&at91rm9200_eth_device);
204}
205#else
206void __init at91_add_device_eth(struct macb_platform_data *data) {}
207#endif
208
209
210/* --------------------------------------------------------------------
211 * Compact Flash / PCMCIA
212 * -------------------------------------------------------------------- */
213
214#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
215static struct at91_cf_data cf_data;
216
217#define CF_BASE AT91_CHIPSELECT_4
218
219static struct resource cf_resources[] = {
220 [0] = {
221 .start = CF_BASE,
222 /* ties up CS4, CS5 and CS6 */
223 .end = CF_BASE + (0x30000000 - 1),
224 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
225 },
226};
227
228static struct platform_device at91rm9200_cf_device = {
229 .name = "at91_cf",
230 .id = -1,
231 .dev = {
232 .platform_data = &cf_data,
233 },
234 .resource = cf_resources,
235 .num_resources = ARRAY_SIZE(cf_resources),
236};
237
238void __init at91_add_device_cf(struct at91_cf_data *data)
239{
240 unsigned int csa;
241
242 if (!data)
243 return;
244
245 data->chipselect = 4; /* can only use EBI ChipSelect 4 */
246
247 /* CF takes over CS4, CS5, CS6 */
248 csa = at91_ramc_read(0, AT91_EBI_CSA);
249 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
250
251 /*
252 * Static memory controller timing adjustments.
253 * REVISIT: these timings are in terms of MCK cycles, so
254 * when MCK changes (cpufreq etc) so must these values...
255 */
256 at91_ramc_write(0, AT91_SMC_CSR(4),
257 AT91_SMC_ACSS_STD
258 | AT91_SMC_DBW_16
259 | AT91_SMC_BAT
260 | AT91_SMC_WSEN
261 | AT91_SMC_NWS_(32) /* wait states */
262 | AT91_SMC_RWSETUP_(6) /* setup time */
263 | AT91_SMC_RWHOLD_(4) /* hold time */
264 );
265
266 /* input/irq */
267 if (gpio_is_valid(data->irq_pin)) {
268 at91_set_gpio_input(data->irq_pin, 1);
269 at91_set_deglitch(data->irq_pin, 1);
270 }
271 at91_set_gpio_input(data->det_pin, 1);
272 at91_set_deglitch(data->det_pin, 1);
273
274 /* outputs, initially off */
275 if (gpio_is_valid(data->vcc_pin))
276 at91_set_gpio_output(data->vcc_pin, 0);
277 at91_set_gpio_output(data->rst_pin, 0);
278
279 /* force poweron defaults for these pins ... */
280 at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */
281 at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */
282 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
283 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
284
285 /* nWAIT is _not_ a default setting */
286 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
287
288 cf_data = *data;
289 platform_device_register(&at91rm9200_cf_device);
290}
291#else
292void __init at91_add_device_cf(struct at91_cf_data *data) {}
293#endif
294
295
296/* --------------------------------------------------------------------
297 * MMC / SD
298 * -------------------------------------------------------------------- */
299
300#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
301static u64 mmc_dmamask = DMA_BIT_MASK(32);
302static struct mci_platform_data mmc_data;
303
304static struct resource mmc_resources[] = {
305 [0] = {
306 .start = AT91RM9200_BASE_MCI,
307 .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
308 .flags = IORESOURCE_MEM,
309 },
310 [1] = {
311 .start = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
312 .end = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
313 .flags = IORESOURCE_IRQ,
314 },
315};
316
317static struct platform_device at91rm9200_mmc_device = {
318 .name = "atmel_mci",
319 .id = -1,
320 .dev = {
321 .dma_mask = &mmc_dmamask,
322 .coherent_dma_mask = DMA_BIT_MASK(32),
323 .platform_data = &mmc_data,
324 },
325 .resource = mmc_resources,
326 .num_resources = ARRAY_SIZE(mmc_resources),
327};
328
329void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
330{
331 unsigned int i;
332 unsigned int slot_count = 0;
333
334 if (!data)
335 return;
336
337 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
338
339 if (!data->slot[i].bus_width)
340 continue;
341
342 /* input/irq */
343 if (gpio_is_valid(data->slot[i].detect_pin)) {
344 at91_set_gpio_input(data->slot[i].detect_pin, 1);
345 at91_set_deglitch(data->slot[i].detect_pin, 1);
346 }
347 if (gpio_is_valid(data->slot[i].wp_pin))
348 at91_set_gpio_input(data->slot[i].wp_pin, 1);
349
350 switch (i) {
351 case 0: /* slot A */
352 /* CMD */
353 at91_set_A_periph(AT91_PIN_PA28, 1);
354 /* DAT0, maybe DAT1..DAT3 */
355 at91_set_A_periph(AT91_PIN_PA29, 1);
356 if (data->slot[i].bus_width == 4) {
357 at91_set_B_periph(AT91_PIN_PB3, 1);
358 at91_set_B_periph(AT91_PIN_PB4, 1);
359 at91_set_B_periph(AT91_PIN_PB5, 1);
360 }
361 slot_count++;
362 break;
363 case 1: /* slot B */
364 /* CMD */
365 at91_set_B_periph(AT91_PIN_PA8, 1);
366 /* DAT0, maybe DAT1..DAT3 */
367 at91_set_B_periph(AT91_PIN_PA9, 1);
368 if (data->slot[i].bus_width == 4) {
369 at91_set_B_periph(AT91_PIN_PA10, 1);
370 at91_set_B_periph(AT91_PIN_PA11, 1);
371 at91_set_B_periph(AT91_PIN_PA12, 1);
372 }
373 slot_count++;
374 break;
375 default:
376 printk(KERN_ERR
377 "AT91: SD/MMC slot %d not available\n", i);
378 break;
379 }
380 if (slot_count) {
381 /* CLK */
382 at91_set_A_periph(AT91_PIN_PA27, 0);
383
384 mmc_data = *data;
385 platform_device_register(&at91rm9200_mmc_device);
386 }
387 }
388
389}
390#else
391void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
392#endif
393
394
395/* --------------------------------------------------------------------
396 * NAND / SmartMedia
397 * -------------------------------------------------------------------- */
398
399#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
400static struct atmel_nand_data nand_data;
401
402#define NAND_BASE AT91_CHIPSELECT_3
403
404static struct resource nand_resources[] = {
405 {
406 .start = NAND_BASE,
407 .end = NAND_BASE + SZ_256M - 1,
408 .flags = IORESOURCE_MEM,
409 }
410};
411
412static struct platform_device at91rm9200_nand_device = {
413 .name = "atmel_nand",
414 .id = -1,
415 .dev = {
416 .platform_data = &nand_data,
417 },
418 .resource = nand_resources,
419 .num_resources = ARRAY_SIZE(nand_resources),
420};
421
422void __init at91_add_device_nand(struct atmel_nand_data *data)
423{
424 unsigned int csa;
425
426 if (!data)
427 return;
428
429 /* enable the address range of CS3 */
430 csa = at91_ramc_read(0, AT91_EBI_CSA);
431 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
432
433 /* set the bus interface characteristics */
434 at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
435 | AT91_SMC_NWS_(5)
436 | AT91_SMC_TDF_(1)
437 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
438 | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
439 );
440
441 /* enable pin */
442 if (gpio_is_valid(data->enable_pin))
443 at91_set_gpio_output(data->enable_pin, 1);
444
445 /* ready/busy pin */
446 if (gpio_is_valid(data->rdy_pin))
447 at91_set_gpio_input(data->rdy_pin, 1);
448
449 /* card detect pin */
450 if (gpio_is_valid(data->det_pin))
451 at91_set_gpio_input(data->det_pin, 1);
452
453 at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
454 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
455
456 nand_data = *data;
457 platform_device_register(&at91rm9200_nand_device);
458}
459#else
460void __init at91_add_device_nand(struct atmel_nand_data *data) {}
461#endif
462
463
464/* --------------------------------------------------------------------
465 * TWI (i2c)
466 * -------------------------------------------------------------------- */
467
468/*
469 * Prefer the GPIO code since the TWI controller isn't robust
470 * (gets overruns and underruns under load) and can only issue
471 * repeated STARTs in one scenario (the driver doesn't yet handle them).
472 */
473#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
474
475static struct i2c_gpio_platform_data pdata = {
476 .sda_pin = AT91_PIN_PA25,
477 .sda_is_open_drain = 1,
478 .scl_pin = AT91_PIN_PA26,
479 .scl_is_open_drain = 1,
480 .udelay = 2, /* ~100 kHz */
481};
482
483static struct platform_device at91rm9200_twi_device = {
484 .name = "i2c-gpio",
485 .id = 0,
486 .dev.platform_data = &pdata,
487};
488
489void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
490{
491 at91_set_GPIO_periph(AT91_PIN_PA25, 1); /* TWD (SDA) */
492 at91_set_multi_drive(AT91_PIN_PA25, 1);
493
494 at91_set_GPIO_periph(AT91_PIN_PA26, 1); /* TWCK (SCL) */
495 at91_set_multi_drive(AT91_PIN_PA26, 1);
496
497 i2c_register_board_info(0, devices, nr_devices);
498 platform_device_register(&at91rm9200_twi_device);
499}
500
501#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
502
503static struct resource twi_resources[] = {
504 [0] = {
505 .start = AT91RM9200_BASE_TWI,
506 .end = AT91RM9200_BASE_TWI + SZ_16K - 1,
507 .flags = IORESOURCE_MEM,
508 },
509 [1] = {
510 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
511 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
512 .flags = IORESOURCE_IRQ,
513 },
514};
515
516static struct platform_device at91rm9200_twi_device = {
517 .name = "i2c-at91rm9200",
518 .id = 0,
519 .resource = twi_resources,
520 .num_resources = ARRAY_SIZE(twi_resources),
521};
522
523void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
524{
525 /* pins used for TWI interface */
526 at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
527 at91_set_multi_drive(AT91_PIN_PA25, 1);
528
529 at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
530 at91_set_multi_drive(AT91_PIN_PA26, 1);
531
532 i2c_register_board_info(0, devices, nr_devices);
533 platform_device_register(&at91rm9200_twi_device);
534}
535#else
536void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
537#endif
538
539
540/* --------------------------------------------------------------------
541 * SPI
542 * -------------------------------------------------------------------- */
543
544#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
545static u64 spi_dmamask = DMA_BIT_MASK(32);
546
547static struct resource spi_resources[] = {
548 [0] = {
549 .start = AT91RM9200_BASE_SPI,
550 .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
551 .flags = IORESOURCE_MEM,
552 },
553 [1] = {
554 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
555 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
556 .flags = IORESOURCE_IRQ,
557 },
558};
559
560static struct platform_device at91rm9200_spi_device = {
561 .name = "atmel_spi",
562 .id = 0,
563 .dev = {
564 .dma_mask = &spi_dmamask,
565 .coherent_dma_mask = DMA_BIT_MASK(32),
566 },
567 .resource = spi_resources,
568 .num_resources = ARRAY_SIZE(spi_resources),
569};
570
571static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
572
573void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
574{
575 int i;
576 unsigned long cs_pin;
577
578 at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
579 at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
580 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
581
582 /* Enable SPI chip-selects */
583 for (i = 0; i < nr_devices; i++) {
584 if (devices[i].controller_data)
585 cs_pin = (unsigned long) devices[i].controller_data;
586 else
587 cs_pin = spi_standard_cs[devices[i].chip_select];
588
589 if (devices[i].chip_select == 0) /* for CS0 errata */
590 at91_set_A_periph(cs_pin, 0);
591 else
592 at91_set_gpio_output(cs_pin, 1);
593
594
595 /* pass chip-select pin to driver */
596 devices[i].controller_data = (void *) cs_pin;
597 }
598
599 spi_register_board_info(devices, nr_devices);
600 platform_device_register(&at91rm9200_spi_device);
601}
602#else
603void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
604#endif
605
606
607/* --------------------------------------------------------------------
608 * Timer/Counter blocks
609 * -------------------------------------------------------------------- */
610
611#ifdef CONFIG_ATMEL_TCLIB
612
613static struct resource tcb0_resources[] = {
614 [0] = {
615 .start = AT91RM9200_BASE_TCB0,
616 .end = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
617 .flags = IORESOURCE_MEM,
618 },
619 [1] = {
620 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
621 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
622 .flags = IORESOURCE_IRQ,
623 },
624 [2] = {
625 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
626 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
627 .flags = IORESOURCE_IRQ,
628 },
629 [3] = {
630 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
631 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
632 .flags = IORESOURCE_IRQ,
633 },
634};
635
636static struct platform_device at91rm9200_tcb0_device = {
637 .name = "atmel_tcb",
638 .id = 0,
639 .resource = tcb0_resources,
640 .num_resources = ARRAY_SIZE(tcb0_resources),
641};
642
643static struct resource tcb1_resources[] = {
644 [0] = {
645 .start = AT91RM9200_BASE_TCB1,
646 .end = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
647 .flags = IORESOURCE_MEM,
648 },
649 [1] = {
650 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
651 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
652 .flags = IORESOURCE_IRQ,
653 },
654 [2] = {
655 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
656 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
657 .flags = IORESOURCE_IRQ,
658 },
659 [3] = {
660 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
661 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
662 .flags = IORESOURCE_IRQ,
663 },
664};
665
666static struct platform_device at91rm9200_tcb1_device = {
667 .name = "atmel_tcb",
668 .id = 1,
669 .resource = tcb1_resources,
670 .num_resources = ARRAY_SIZE(tcb1_resources),
671};
672
673static void __init at91_add_device_tc(void)
674{
675 platform_device_register(&at91rm9200_tcb0_device);
676 platform_device_register(&at91rm9200_tcb1_device);
677}
678#else
679static void __init at91_add_device_tc(void) { }
680#endif
681
682
683/* --------------------------------------------------------------------
684 * RTC
685 * -------------------------------------------------------------------- */
686
687#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
688static struct resource rtc_resources[] = {
689 [0] = {
690 .start = AT91RM9200_BASE_RTC,
691 .end = AT91RM9200_BASE_RTC + SZ_256 - 1,
692 .flags = IORESOURCE_MEM,
693 },
694 [1] = {
695 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
696 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
697 .flags = IORESOURCE_IRQ,
698 },
699};
700
701static struct platform_device at91rm9200_rtc_device = {
702 .name = "at91_rtc",
703 .id = -1,
704 .resource = rtc_resources,
705 .num_resources = ARRAY_SIZE(rtc_resources),
706};
707
708static void __init at91_add_device_rtc(void)
709{
710 platform_device_register(&at91rm9200_rtc_device);
711}
712#else
713static void __init at91_add_device_rtc(void) {}
714#endif
715
716
717/* --------------------------------------------------------------------
718 * Watchdog
719 * -------------------------------------------------------------------- */
720
721#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
722static struct platform_device at91rm9200_wdt_device = {
723 .name = "at91_wdt",
724 .id = -1,
725 .num_resources = 0,
726};
727
728static void __init at91_add_device_watchdog(void)
729{
730 platform_device_register(&at91rm9200_wdt_device);
731}
732#else
733static void __init at91_add_device_watchdog(void) {}
734#endif
735
736
737/* --------------------------------------------------------------------
738 * SSC -- Synchronous Serial Controller
739 * -------------------------------------------------------------------- */
740
741#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
742static u64 ssc0_dmamask = DMA_BIT_MASK(32);
743
744static struct resource ssc0_resources[] = {
745 [0] = {
746 .start = AT91RM9200_BASE_SSC0,
747 .end = AT91RM9200_BASE_SSC0 + SZ_16K - 1,
748 .flags = IORESOURCE_MEM,
749 },
750 [1] = {
751 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
752 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
753 .flags = IORESOURCE_IRQ,
754 },
755};
756
757static struct platform_device at91rm9200_ssc0_device = {
758 .name = "at91rm9200_ssc",
759 .id = 0,
760 .dev = {
761 .dma_mask = &ssc0_dmamask,
762 .coherent_dma_mask = DMA_BIT_MASK(32),
763 },
764 .resource = ssc0_resources,
765 .num_resources = ARRAY_SIZE(ssc0_resources),
766};
767
768static inline void configure_ssc0_pins(unsigned pins)
769{
770 if (pins & ATMEL_SSC_TF)
771 at91_set_A_periph(AT91_PIN_PB0, 1);
772 if (pins & ATMEL_SSC_TK)
773 at91_set_A_periph(AT91_PIN_PB1, 1);
774 if (pins & ATMEL_SSC_TD)
775 at91_set_A_periph(AT91_PIN_PB2, 1);
776 if (pins & ATMEL_SSC_RD)
777 at91_set_A_periph(AT91_PIN_PB3, 1);
778 if (pins & ATMEL_SSC_RK)
779 at91_set_A_periph(AT91_PIN_PB4, 1);
780 if (pins & ATMEL_SSC_RF)
781 at91_set_A_periph(AT91_PIN_PB5, 1);
782}
783
784static u64 ssc1_dmamask = DMA_BIT_MASK(32);
785
786static struct resource ssc1_resources[] = {
787 [0] = {
788 .start = AT91RM9200_BASE_SSC1,
789 .end = AT91RM9200_BASE_SSC1 + SZ_16K - 1,
790 .flags = IORESOURCE_MEM,
791 },
792 [1] = {
793 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
794 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
795 .flags = IORESOURCE_IRQ,
796 },
797};
798
799static struct platform_device at91rm9200_ssc1_device = {
800 .name = "at91rm9200_ssc",
801 .id = 1,
802 .dev = {
803 .dma_mask = &ssc1_dmamask,
804 .coherent_dma_mask = DMA_BIT_MASK(32),
805 },
806 .resource = ssc1_resources,
807 .num_resources = ARRAY_SIZE(ssc1_resources),
808};
809
810static inline void configure_ssc1_pins(unsigned pins)
811{
812 if (pins & ATMEL_SSC_TF)
813 at91_set_A_periph(AT91_PIN_PB6, 1);
814 if (pins & ATMEL_SSC_TK)
815 at91_set_A_periph(AT91_PIN_PB7, 1);
816 if (pins & ATMEL_SSC_TD)
817 at91_set_A_periph(AT91_PIN_PB8, 1);
818 if (pins & ATMEL_SSC_RD)
819 at91_set_A_periph(AT91_PIN_PB9, 1);
820 if (pins & ATMEL_SSC_RK)
821 at91_set_A_periph(AT91_PIN_PB10, 1);
822 if (pins & ATMEL_SSC_RF)
823 at91_set_A_periph(AT91_PIN_PB11, 1);
824}
825
826static u64 ssc2_dmamask = DMA_BIT_MASK(32);
827
828static struct resource ssc2_resources[] = {
829 [0] = {
830 .start = AT91RM9200_BASE_SSC2,
831 .end = AT91RM9200_BASE_SSC2 + SZ_16K - 1,
832 .flags = IORESOURCE_MEM,
833 },
834 [1] = {
835 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
836 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
837 .flags = IORESOURCE_IRQ,
838 },
839};
840
841static struct platform_device at91rm9200_ssc2_device = {
842 .name = "at91rm9200_ssc",
843 .id = 2,
844 .dev = {
845 .dma_mask = &ssc2_dmamask,
846 .coherent_dma_mask = DMA_BIT_MASK(32),
847 },
848 .resource = ssc2_resources,
849 .num_resources = ARRAY_SIZE(ssc2_resources),
850};
851
852static inline void configure_ssc2_pins(unsigned pins)
853{
854 if (pins & ATMEL_SSC_TF)
855 at91_set_A_periph(AT91_PIN_PB12, 1);
856 if (pins & ATMEL_SSC_TK)
857 at91_set_A_periph(AT91_PIN_PB13, 1);
858 if (pins & ATMEL_SSC_TD)
859 at91_set_A_periph(AT91_PIN_PB14, 1);
860 if (pins & ATMEL_SSC_RD)
861 at91_set_A_periph(AT91_PIN_PB15, 1);
862 if (pins & ATMEL_SSC_RK)
863 at91_set_A_periph(AT91_PIN_PB16, 1);
864 if (pins & ATMEL_SSC_RF)
865 at91_set_A_periph(AT91_PIN_PB17, 1);
866}
867
868/*
869 * SSC controllers are accessed through library code, instead of any
870 * kind of all-singing/all-dancing driver. For example one could be
871 * used by a particular I2S audio codec's driver, while another one
872 * on the same system might be used by a custom data capture driver.
873 */
874void __init at91_add_device_ssc(unsigned id, unsigned pins)
875{
876 struct platform_device *pdev;
877
878 /*
879 * NOTE: caller is responsible for passing information matching
880 * "pins" to whatever will be using each particular controller.
881 */
882 switch (id) {
883 case AT91RM9200_ID_SSC0:
884 pdev = &at91rm9200_ssc0_device;
885 configure_ssc0_pins(pins);
886 break;
887 case AT91RM9200_ID_SSC1:
888 pdev = &at91rm9200_ssc1_device;
889 configure_ssc1_pins(pins);
890 break;
891 case AT91RM9200_ID_SSC2:
892 pdev = &at91rm9200_ssc2_device;
893 configure_ssc2_pins(pins);
894 break;
895 default:
896 return;
897 }
898
899 platform_device_register(pdev);
900}
901
902#else
903void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
904#endif
905
906
907/* --------------------------------------------------------------------
908 * UART
909 * -------------------------------------------------------------------- */
910
911#if defined(CONFIG_SERIAL_ATMEL)
912static struct resource dbgu_resources[] = {
913 [0] = {
914 .start = AT91RM9200_BASE_DBGU,
915 .end = AT91RM9200_BASE_DBGU + SZ_512 - 1,
916 .flags = IORESOURCE_MEM,
917 },
918 [1] = {
919 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
920 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
921 .flags = IORESOURCE_IRQ,
922 },
923};
924
925static struct atmel_uart_data dbgu_data = {
926 .use_dma_tx = 0,
927 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
928};
929
930static u64 dbgu_dmamask = DMA_BIT_MASK(32);
931
932static struct platform_device at91rm9200_dbgu_device = {
933 .name = "atmel_usart",
934 .id = 0,
935 .dev = {
936 .dma_mask = &dbgu_dmamask,
937 .coherent_dma_mask = DMA_BIT_MASK(32),
938 .platform_data = &dbgu_data,
939 },
940 .resource = dbgu_resources,
941 .num_resources = ARRAY_SIZE(dbgu_resources),
942};
943
944static inline void configure_dbgu_pins(void)
945{
946 at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
947 at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
948}
949
950static struct resource uart0_resources[] = {
951 [0] = {
952 .start = AT91RM9200_BASE_US0,
953 .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
954 .flags = IORESOURCE_MEM,
955 },
956 [1] = {
957 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
958 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
959 .flags = IORESOURCE_IRQ,
960 },
961};
962
963static struct atmel_uart_data uart0_data = {
964 .use_dma_tx = 1,
965 .use_dma_rx = 1,
966};
967
968static struct gpiod_lookup_table uart0_gpios_table = {
969 .dev_id = "atmel_usart",
970 .table = {
971 GPIO_LOOKUP("pioA", 21, "rts", GPIO_ACTIVE_LOW),
972 { },
973 },
974};
975
976static u64 uart0_dmamask = DMA_BIT_MASK(32);
977
978static struct platform_device at91rm9200_uart0_device = {
979 .name = "atmel_usart",
980 .id = 1,
981 .dev = {
982 .dma_mask = &uart0_dmamask,
983 .coherent_dma_mask = DMA_BIT_MASK(32),
984 .platform_data = &uart0_data,
985 },
986 .resource = uart0_resources,
987 .num_resources = ARRAY_SIZE(uart0_resources),
988};
989
990static inline void configure_usart0_pins(unsigned pins)
991{
992 at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
993 at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
994
995 if (pins & ATMEL_UART_CTS)
996 at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
997
998 if (pins & ATMEL_UART_RTS) {
999 /*
1000 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
1001 * We need to drive the pin manually. The serial driver will driver
1002 * this to high when initializing.
1003 */
1004 gpiod_add_lookup_table(&uart0_gpios_table);
1005 }
1006}
1007
1008static struct resource uart1_resources[] = {
1009 [0] = {
1010 .start = AT91RM9200_BASE_US1,
1011 .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
1012 .flags = IORESOURCE_MEM,
1013 },
1014 [1] = {
1015 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
1016 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
1017 .flags = IORESOURCE_IRQ,
1018 },
1019};
1020
1021static struct atmel_uart_data uart1_data = {
1022 .use_dma_tx = 1,
1023 .use_dma_rx = 1,
1024};
1025
1026static u64 uart1_dmamask = DMA_BIT_MASK(32);
1027
1028static struct platform_device at91rm9200_uart1_device = {
1029 .name = "atmel_usart",
1030 .id = 2,
1031 .dev = {
1032 .dma_mask = &uart1_dmamask,
1033 .coherent_dma_mask = DMA_BIT_MASK(32),
1034 .platform_data = &uart1_data,
1035 },
1036 .resource = uart1_resources,
1037 .num_resources = ARRAY_SIZE(uart1_resources),
1038};
1039
1040static inline void configure_usart1_pins(unsigned pins)
1041{
1042 at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
1043 at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
1044
1045 if (pins & ATMEL_UART_RI)
1046 at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
1047 if (pins & ATMEL_UART_DTR)
1048 at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
1049 if (pins & ATMEL_UART_DCD)
1050 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
1051 if (pins & ATMEL_UART_CTS)
1052 at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
1053 if (pins & ATMEL_UART_DSR)
1054 at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
1055 if (pins & ATMEL_UART_RTS)
1056 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
1057}
1058
1059static struct resource uart2_resources[] = {
1060 [0] = {
1061 .start = AT91RM9200_BASE_US2,
1062 .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
1063 .flags = IORESOURCE_MEM,
1064 },
1065 [1] = {
1066 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
1067 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
1068 .flags = IORESOURCE_IRQ,
1069 },
1070};
1071
1072static struct atmel_uart_data uart2_data = {
1073 .use_dma_tx = 1,
1074 .use_dma_rx = 1,
1075};
1076
1077static u64 uart2_dmamask = DMA_BIT_MASK(32);
1078
1079static struct platform_device at91rm9200_uart2_device = {
1080 .name = "atmel_usart",
1081 .id = 3,
1082 .dev = {
1083 .dma_mask = &uart2_dmamask,
1084 .coherent_dma_mask = DMA_BIT_MASK(32),
1085 .platform_data = &uart2_data,
1086 },
1087 .resource = uart2_resources,
1088 .num_resources = ARRAY_SIZE(uart2_resources),
1089};
1090
1091static inline void configure_usart2_pins(unsigned pins)
1092{
1093 at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
1094 at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */
1095
1096 if (pins & ATMEL_UART_CTS)
1097 at91_set_B_periph(AT91_PIN_PA30, 0); /* CTS2 */
1098 if (pins & ATMEL_UART_RTS)
1099 at91_set_B_periph(AT91_PIN_PA31, 0); /* RTS2 */
1100}
1101
1102static struct resource uart3_resources[] = {
1103 [0] = {
1104 .start = AT91RM9200_BASE_US3,
1105 .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
1106 .flags = IORESOURCE_MEM,
1107 },
1108 [1] = {
1109 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
1110 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
1111 .flags = IORESOURCE_IRQ,
1112 },
1113};
1114
1115static struct atmel_uart_data uart3_data = {
1116 .use_dma_tx = 1,
1117 .use_dma_rx = 1,
1118};
1119
1120static u64 uart3_dmamask = DMA_BIT_MASK(32);
1121
1122static struct platform_device at91rm9200_uart3_device = {
1123 .name = "atmel_usart",
1124 .id = 4,
1125 .dev = {
1126 .dma_mask = &uart3_dmamask,
1127 .coherent_dma_mask = DMA_BIT_MASK(32),
1128 .platform_data = &uart3_data,
1129 },
1130 .resource = uart3_resources,
1131 .num_resources = ARRAY_SIZE(uart3_resources),
1132};
1133
1134static inline void configure_usart3_pins(unsigned pins)
1135{
1136 at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
1137 at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
1138
1139 if (pins & ATMEL_UART_CTS)
1140 at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */
1141 if (pins & ATMEL_UART_RTS)
1142 at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */
1143}
1144
1145static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1146
1147void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1148{
1149 struct platform_device *pdev;
1150 struct atmel_uart_data *pdata;
1151
1152 switch (id) {
1153 case 0: /* DBGU */
1154 pdev = &at91rm9200_dbgu_device;
1155 configure_dbgu_pins();
1156 break;
1157 case AT91RM9200_ID_US0:
1158 pdev = &at91rm9200_uart0_device;
1159 configure_usart0_pins(pins);
1160 break;
1161 case AT91RM9200_ID_US1:
1162 pdev = &at91rm9200_uart1_device;
1163 configure_usart1_pins(pins);
1164 break;
1165 case AT91RM9200_ID_US2:
1166 pdev = &at91rm9200_uart2_device;
1167 configure_usart2_pins(pins);
1168 break;
1169 case AT91RM9200_ID_US3:
1170 pdev = &at91rm9200_uart3_device;
1171 configure_usart3_pins(pins);
1172 break;
1173 default:
1174 return;
1175 }
1176 pdata = pdev->dev.platform_data;
1177 pdata->num = portnr; /* update to mapped ID */
1178
1179 if (portnr < ATMEL_MAX_UART)
1180 at91_uarts[portnr] = pdev;
1181}
1182
1183void __init at91_add_device_serial(void)
1184{
1185 int i;
1186
1187 for (i = 0; i < ATMEL_MAX_UART; i++) {
1188 if (at91_uarts[i])
1189 platform_device_register(at91_uarts[i]);
1190 }
1191}
1192#else
1193void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1194void __init at91_add_device_serial(void) {}
1195#endif
1196
1197
1198/* -------------------------------------------------------------------- */
1199
1200/*
1201 * These devices are always present and don't need any board-specific
1202 * setup.
1203 */
1204static int __init at91_add_standard_devices(void)
1205{
1206 at91_add_device_rtc();
1207 at91_add_device_watchdog();
1208 at91_add_device_tc();
1209 return 0;
1210}
1211
1212arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index c8988fe5ff70..dee569b1987e 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -6,219 +6,11 @@
6 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2 or later.
7 */ 7 */
8 8
9#include <linux/module.h> 9#include <asm/system_misc.h>
10#include <linux/dma-mapping.h> 10#include <mach/hardware.h>
11#include <linux/clk/at91_pmc.h>
12 11
13#include <asm/irq.h>
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16#include <mach/at91sam9n12.h>
17#include <mach/cpu.h>
18
19#include "board.h"
20#include "soc.h" 12#include "soc.h"
21#include "generic.h" 13#include "generic.h"
22#include "sam9_smc.h"
23
24#if defined(CONFIG_OLD_CLK_AT91)
25#include "clock.h"
26/* --------------------------------------------------------------------
27 * Clocks
28 * -------------------------------------------------------------------- */
29
30/*
31 * The peripheral clocks.
32 */
33static struct clk pioAB_clk = {
34 .name = "pioAB_clk",
35 .pmc_mask = 1 << AT91SAM9N12_ID_PIOAB,
36 .type = CLK_TYPE_PERIPHERAL,
37};
38static struct clk pioCD_clk = {
39 .name = "pioCD_clk",
40 .pmc_mask = 1 << AT91SAM9N12_ID_PIOCD,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk usart0_clk = {
44 .name = "usart0_clk",
45 .pmc_mask = 1 << AT91SAM9N12_ID_USART0,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk usart1_clk = {
49 .name = "usart1_clk",
50 .pmc_mask = 1 << AT91SAM9N12_ID_USART1,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk usart2_clk = {
54 .name = "usart2_clk",
55 .pmc_mask = 1 << AT91SAM9N12_ID_USART2,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk usart3_clk = {
59 .name = "usart3_clk",
60 .pmc_mask = 1 << AT91SAM9N12_ID_USART3,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63static struct clk twi0_clk = {
64 .name = "twi0_clk",
65 .pmc_mask = 1 << AT91SAM9N12_ID_TWI0,
66 .type = CLK_TYPE_PERIPHERAL,
67};
68static struct clk twi1_clk = {
69 .name = "twi1_clk",
70 .pmc_mask = 1 << AT91SAM9N12_ID_TWI1,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk mmc_clk = {
74 .name = "mci_clk",
75 .pmc_mask = 1 << AT91SAM9N12_ID_MCI,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk spi0_clk = {
79 .name = "spi0_clk",
80 .pmc_mask = 1 << AT91SAM9N12_ID_SPI0,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk spi1_clk = {
84 .name = "spi1_clk",
85 .pmc_mask = 1 << AT91SAM9N12_ID_SPI1,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk uart0_clk = {
89 .name = "uart0_clk",
90 .pmc_mask = 1 << AT91SAM9N12_ID_UART0,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk uart1_clk = {
94 .name = "uart1_clk",
95 .pmc_mask = 1 << AT91SAM9N12_ID_UART1,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk tcb_clk = {
99 .name = "tcb_clk",
100 .pmc_mask = 1 << AT91SAM9N12_ID_TCB,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk pwm_clk = {
104 .name = "pwm_clk",
105 .pmc_mask = 1 << AT91SAM9N12_ID_PWM,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk adc_clk = {
109 .name = "adc_clk",
110 .pmc_mask = 1 << AT91SAM9N12_ID_ADC,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk dma_clk = {
114 .name = "dma_clk",
115 .pmc_mask = 1 << AT91SAM9N12_ID_DMA,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk uhp_clk = {
119 .name = "uhp",
120 .pmc_mask = 1 << AT91SAM9N12_ID_UHP,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk udp_clk = {
124 .name = "udp_clk",
125 .pmc_mask = 1 << AT91SAM9N12_ID_UDP,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk lcdc_clk = {
129 .name = "lcdc_clk",
130 .pmc_mask = 1 << AT91SAM9N12_ID_LCDC,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk ssc_clk = {
134 .name = "ssc_clk",
135 .pmc_mask = 1 << AT91SAM9N12_ID_SSC,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138
139static struct clk *periph_clocks[] __initdata = {
140 &pioAB_clk,
141 &pioCD_clk,
142 &usart0_clk,
143 &usart1_clk,
144 &usart2_clk,
145 &usart3_clk,
146 &twi0_clk,
147 &twi1_clk,
148 &mmc_clk,
149 &spi0_clk,
150 &spi1_clk,
151 &lcdc_clk,
152 &uart0_clk,
153 &uart1_clk,
154 &tcb_clk,
155 &pwm_clk,
156 &adc_clk,
157 &dma_clk,
158 &uhp_clk,
159 &udp_clk,
160 &ssc_clk,
161};
162
163static struct clk_lookup periph_clocks_lookups[] = {
164 /* lookup table for DT entries */
165 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
166 CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
167 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
168 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
169 CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
170 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
171 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
172 CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
173 CLKDEV_CON_DEV_ID(NULL, "f0010000.ssc", &ssc_clk),
174 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
175 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
176 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
177 CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
178 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
179 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
180 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
181 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
182 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
183 /* additional fake clock for macb_hclk */
184 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
185 CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
186 CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
187};
188
189/*
190 * The two programmable clocks.
191 * You must configure pin multiplexing to bring these signals out.
192 */
193static struct clk pck0 = {
194 .name = "pck0",
195 .pmc_mask = AT91_PMC_PCK0,
196 .type = CLK_TYPE_PROGRAMMABLE,
197 .id = 0,
198};
199static struct clk pck1 = {
200 .name = "pck1",
201 .pmc_mask = AT91_PMC_PCK1,
202 .type = CLK_TYPE_PROGRAMMABLE,
203 .id = 1,
204};
205
206static void __init at91sam9n12_register_clocks(void)
207{
208 int i;
209
210 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
211 clk_register(periph_clocks[i]);
212 clk_register(&pck0);
213 clk_register(&pck1);
214
215 clkdev_add_table(periph_clocks_lookups,
216 ARRAY_SIZE(periph_clocks_lookups));
217
218}
219#else
220#define at91sam9n12_register_clocks NULL
221#endif
222 14
223/* -------------------------------------------------------------------- 15/* --------------------------------------------------------------------
224 * AT91SAM9N12 processor initialization 16 * AT91SAM9N12 processor initialization
@@ -236,6 +28,5 @@ static void __init at91sam9n12_initialize(void)
236 28
237AT91_SOC_START(at91sam9n12) 29AT91_SOC_START(at91sam9n12)
238 .map_io = at91sam9n12_map_io, 30 .map_io = at91sam9n12_map_io,
239 .register_clocks = at91sam9n12_register_clocks,
240 .init = at91sam9n12_initialize, 31 .init = at91sam9n12_initialize,
241AT91_SOC_END 32AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 028268ff3722..f0d5a69a7237 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -6,317 +6,11 @@
6 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2 or later.
7 */ 7 */
8 8
9#include <linux/module.h> 9#include <asm/system_misc.h>
10#include <linux/dma-mapping.h> 10#include <mach/hardware.h>
11#include <linux/clk/at91_pmc.h>
12 11
13#include <asm/irq.h>
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16#include <mach/at91sam9x5.h>
17#include <mach/cpu.h>
18
19#include "board.h"
20#include "soc.h" 12#include "soc.h"
21#include "generic.h" 13#include "generic.h"
22#include "sam9_smc.h"
23
24#if defined(CONFIG_OLD_CLK_AT91)
25#include "clock.h"
26/* --------------------------------------------------------------------
27 * Clocks
28 * -------------------------------------------------------------------- */
29
30/*
31 * The peripheral clocks.
32 */
33static struct clk pioAB_clk = {
34 .name = "pioAB_clk",
35 .pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
36 .type = CLK_TYPE_PERIPHERAL,
37};
38static struct clk pioCD_clk = {
39 .name = "pioCD_clk",
40 .pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk smd_clk = {
44 .name = "smd_clk",
45 .pmc_mask = 1 << AT91SAM9X5_ID_SMD,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk usart0_clk = {
49 .name = "usart0_clk",
50 .pmc_mask = 1 << AT91SAM9X5_ID_USART0,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk usart1_clk = {
54 .name = "usart1_clk",
55 .pmc_mask = 1 << AT91SAM9X5_ID_USART1,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk usart2_clk = {
59 .name = "usart2_clk",
60 .pmc_mask = 1 << AT91SAM9X5_ID_USART2,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63/* USART3 clock - Only for sam9g25/sam9x25 */
64static struct clk usart3_clk = {
65 .name = "usart3_clk",
66 .pmc_mask = 1 << AT91SAM9X5_ID_USART3,
67 .type = CLK_TYPE_PERIPHERAL,
68};
69static struct clk twi0_clk = {
70 .name = "twi0_clk",
71 .pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
72 .type = CLK_TYPE_PERIPHERAL,
73};
74static struct clk twi1_clk = {
75 .name = "twi1_clk",
76 .pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
77 .type = CLK_TYPE_PERIPHERAL,
78};
79static struct clk twi2_clk = {
80 .name = "twi2_clk",
81 .pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
82 .type = CLK_TYPE_PERIPHERAL,
83};
84static struct clk mmc0_clk = {
85 .name = "mci0_clk",
86 .pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
87 .type = CLK_TYPE_PERIPHERAL,
88};
89static struct clk spi0_clk = {
90 .name = "spi0_clk",
91 .pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
92 .type = CLK_TYPE_PERIPHERAL,
93};
94static struct clk spi1_clk = {
95 .name = "spi1_clk",
96 .pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
97 .type = CLK_TYPE_PERIPHERAL,
98};
99static struct clk uart0_clk = {
100 .name = "uart0_clk",
101 .pmc_mask = 1 << AT91SAM9X5_ID_UART0,
102 .type = CLK_TYPE_PERIPHERAL,
103};
104static struct clk uart1_clk = {
105 .name = "uart1_clk",
106 .pmc_mask = 1 << AT91SAM9X5_ID_UART1,
107 .type = CLK_TYPE_PERIPHERAL,
108};
109static struct clk tcb0_clk = {
110 .name = "tcb0_clk",
111 .pmc_mask = 1 << AT91SAM9X5_ID_TCB,
112 .type = CLK_TYPE_PERIPHERAL,
113};
114static struct clk pwm_clk = {
115 .name = "pwm_clk",
116 .pmc_mask = 1 << AT91SAM9X5_ID_PWM,
117 .type = CLK_TYPE_PERIPHERAL,
118};
119static struct clk adc_clk = {
120 .name = "adc_clk",
121 .pmc_mask = 1 << AT91SAM9X5_ID_ADC,
122 .type = CLK_TYPE_PERIPHERAL,
123};
124static struct clk adc_op_clk = {
125 .name = "adc_op_clk",
126 .type = CLK_TYPE_PERIPHERAL,
127 .rate_hz = 5000000,
128};
129static struct clk dma0_clk = {
130 .name = "dma0_clk",
131 .pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
132 .type = CLK_TYPE_PERIPHERAL,
133};
134static struct clk dma1_clk = {
135 .name = "dma1_clk",
136 .pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
137 .type = CLK_TYPE_PERIPHERAL,
138};
139static struct clk uhphs_clk = {
140 .name = "uhphs",
141 .pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
142 .type = CLK_TYPE_PERIPHERAL,
143};
144static struct clk udphs_clk = {
145 .name = "udphs_clk",
146 .pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
147 .type = CLK_TYPE_PERIPHERAL,
148};
149/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
150static struct clk macb0_clk = {
151 .name = "pclk",
152 .pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
153 .type = CLK_TYPE_PERIPHERAL,
154};
155/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
156static struct clk lcdc_clk = {
157 .name = "lcdc_clk",
158 .pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
159 .type = CLK_TYPE_PERIPHERAL,
160};
161/* isi clock - Only for sam9g25 */
162static struct clk isi_clk = {
163 .name = "isi_clk",
164 .pmc_mask = 1 << AT91SAM9X5_ID_ISI,
165 .type = CLK_TYPE_PERIPHERAL,
166};
167static struct clk mmc1_clk = {
168 .name = "mci1_clk",
169 .pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
170 .type = CLK_TYPE_PERIPHERAL,
171};
172/* emac1 clock - Only for sam9x25 */
173static struct clk macb1_clk = {
174 .name = "pclk",
175 .pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
176 .type = CLK_TYPE_PERIPHERAL,
177};
178static struct clk ssc_clk = {
179 .name = "ssc_clk",
180 .pmc_mask = 1 << AT91SAM9X5_ID_SSC,
181 .type = CLK_TYPE_PERIPHERAL,
182};
183/* can0 clock - Only for sam9x35 */
184static struct clk can0_clk = {
185 .name = "can0_clk",
186 .pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
187 .type = CLK_TYPE_PERIPHERAL,
188};
189/* can1 clock - Only for sam9x35 */
190static struct clk can1_clk = {
191 .name = "can1_clk",
192 .pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
193 .type = CLK_TYPE_PERIPHERAL,
194};
195
196static struct clk *periph_clocks[] __initdata = {
197 &pioAB_clk,
198 &pioCD_clk,
199 &smd_clk,
200 &usart0_clk,
201 &usart1_clk,
202 &usart2_clk,
203 &twi0_clk,
204 &twi1_clk,
205 &twi2_clk,
206 &mmc0_clk,
207 &spi0_clk,
208 &spi1_clk,
209 &uart0_clk,
210 &uart1_clk,
211 &tcb0_clk,
212 &pwm_clk,
213 &adc_clk,
214 &adc_op_clk,
215 &dma0_clk,
216 &dma1_clk,
217 &uhphs_clk,
218 &udphs_clk,
219 &mmc1_clk,
220 &ssc_clk,
221 // irq0
222};
223
224static struct clk_lookup periph_clocks_lookups[] = {
225 /* lookup table for DT entries */
226 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
227 CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
228 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
229 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
230 CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
231 CLKDEV_CON_DEV_ID("usart", "f8040000.serial", &uart0_clk),
232 CLKDEV_CON_DEV_ID("usart", "f8044000.serial", &uart1_clk),
233 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
234 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
235 CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
236 CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
237 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
238 CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
239 CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
240 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
241 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
242 CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
243 CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
244 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
245 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
246 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
247 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
248 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
249 /* additional fake clock for macb_hclk */
250 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
251 CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
252 CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
253 CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
254 CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
255 CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
256 CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
257 CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
258};
259
260/*
261 * The two programmable clocks.
262 * You must configure pin multiplexing to bring these signals out.
263 */
264static struct clk pck0 = {
265 .name = "pck0",
266 .pmc_mask = AT91_PMC_PCK0,
267 .type = CLK_TYPE_PROGRAMMABLE,
268 .id = 0,
269};
270static struct clk pck1 = {
271 .name = "pck1",
272 .pmc_mask = AT91_PMC_PCK1,
273 .type = CLK_TYPE_PROGRAMMABLE,
274 .id = 1,
275};
276
277static void __init at91sam9x5_register_clocks(void)
278{
279 int i;
280
281 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
282 clk_register(periph_clocks[i]);
283
284 clkdev_add_table(periph_clocks_lookups,
285 ARRAY_SIZE(periph_clocks_lookups));
286
287 if (cpu_is_at91sam9g25()
288 || cpu_is_at91sam9x25())
289 clk_register(&usart3_clk);
290
291 if (cpu_is_at91sam9g25()
292 || cpu_is_at91sam9x25()
293 || cpu_is_at91sam9g35()
294 || cpu_is_at91sam9x35())
295 clk_register(&macb0_clk);
296
297 if (cpu_is_at91sam9g15()
298 || cpu_is_at91sam9g35()
299 || cpu_is_at91sam9x35())
300 clk_register(&lcdc_clk);
301
302 if (cpu_is_at91sam9g25())
303 clk_register(&isi_clk);
304
305 if (cpu_is_at91sam9x25())
306 clk_register(&macb1_clk);
307
308 if (cpu_is_at91sam9x25()
309 || cpu_is_at91sam9x35()) {
310 clk_register(&can0_clk);
311 clk_register(&can1_clk);
312 }
313
314 clk_register(&pck0);
315 clk_register(&pck1);
316}
317#else
318#define at91sam9x5_register_clocks NULL
319#endif
320 14
321/* -------------------------------------------------------------------- 15/* --------------------------------------------------------------------
322 * AT91SAM9x5 processor initialization 16 * AT91SAM9x5 processor initialization
@@ -338,6 +32,5 @@ static void __init at91sam9x5_initialize(void)
338 32
339AT91_SOC_START(at91sam9x5) 33AT91_SOC_START(at91sam9x5)
340 .map_io = at91sam9x5_map_io, 34 .map_io = at91sam9x5_map_io,
341 .register_clocks = at91sam9x5_register_clocks,
342 .init = at91sam9x5_initialize, 35 .init = at91sam9x5_initialize,
343AT91_SOC_END 36AT91_SOC_END
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
deleted file mode 100644
index 3f6dbcc34022..000000000000
--- a/arch/arm/mach-at91/board-1arm.c
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-1arm.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/gpio.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27
28#include <mach/hardware.h>
29#include <asm/setup.h>
30#include <asm/mach-types.h>
31#include <asm/irq.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/cpu.h>
38
39#include "at91_aic.h"
40#include "board.h"
41#include "generic.h"
42#include "gpio.h"
43
44static void __init onearm_init_early(void)
45{
46 /* Set cpu type: PQFP */
47 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
48
49 /* Initialize processor: 18.432 MHz crystal */
50 at91_initialize(18432000);
51}
52
53static struct macb_platform_data __initdata onearm_eth_data = {
54 .phy_irq_pin = AT91_PIN_PC4,
55 .is_rmii = 1,
56};
57
58static struct at91_usbh_data __initdata onearm_usbh_data = {
59 .ports = 1,
60 .vbus_pin = {-EINVAL, -EINVAL},
61 .overcurrent_pin= {-EINVAL, -EINVAL},
62};
63
64static struct at91_udc_data __initdata onearm_udc_data = {
65 .vbus_pin = AT91_PIN_PC2,
66 .pullup_pin = AT91_PIN_PC3,
67};
68
69static void __init onearm_board_init(void)
70{
71 /* Serial */
72 /* DBGU on ttyS0. (Rx & Tx only) */
73 at91_register_uart(0, 0, 0);
74
75 /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
76 at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
77
78 /* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
79 at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
80 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
81 | ATMEL_UART_RI);
82 at91_add_device_serial();
83 /* Ethernet */
84 at91_add_device_eth(&onearm_eth_data);
85 /* USB Host */
86 at91_add_device_usbh(&onearm_usbh_data);
87 /* USB Device */
88 at91_add_device_udc(&onearm_udc_data);
89}
90
91MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
92 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
93 .init_time = at91rm9200_timer_init,
94 .map_io = at91_map_io,
95 .handle_irq = at91_aic_handle_irq,
96 .init_early = onearm_init_early,
97 .init_irq = at91_init_irq_default,
98 .init_machine = onearm_board_init,
99MACHINE_END
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
deleted file mode 100644
index 47313d3ee037..000000000000
--- a/arch/arm/mach-at91/board-carmeva.c
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-carmeva.c
3 *
4 * Copyright (c) 2005 Peer Georgi
5 * Conitec Datasystems
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28
29#include <asm/setup.h>
30#include <asm/mach-types.h>
31#include <asm/irq.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/hardware.h>
38
39#include "at91_aic.h"
40#include "board.h"
41#include "generic.h"
42#include "gpio.h"
43
44
45static void __init carmeva_init_early(void)
46{
47 /* Initialize processor: 20.000 MHz crystal */
48 at91_initialize(20000000);
49}
50
51static struct macb_platform_data __initdata carmeva_eth_data = {
52 .phy_irq_pin = AT91_PIN_PC4,
53 .is_rmii = 1,
54};
55
56static struct at91_usbh_data __initdata carmeva_usbh_data = {
57 .ports = 2,
58 .vbus_pin = {-EINVAL, -EINVAL},
59 .overcurrent_pin= {-EINVAL, -EINVAL},
60};
61
62static struct at91_udc_data __initdata carmeva_udc_data = {
63 .vbus_pin = AT91_PIN_PD12,
64 .pullup_pin = AT91_PIN_PD9,
65};
66
67/* FIXME: user dependent */
68// static struct at91_cf_data __initdata carmeva_cf_data = {
69// .det_pin = AT91_PIN_PB0,
70// .rst_pin = AT91_PIN_PC5,
71 // .irq_pin = -EINVAL,
72 // .vcc_pin = -EINVAL,
73// };
74
75static struct mci_platform_data __initdata carmeva_mci0_data = {
76 .slot[0] = {
77 .bus_width = 4,
78 .detect_pin = AT91_PIN_PB10,
79 .wp_pin = AT91_PIN_PC14,
80 },
81};
82
83static struct spi_board_info carmeva_spi_devices[] = {
84 { /* DataFlash chip */
85 .modalias = "mtd_dataflash",
86 .chip_select = 0,
87 .max_speed_hz = 10 * 1000 * 1000,
88 },
89 { /* User accessible spi - cs1 (250KHz) */
90 .modalias = "spi-cs1",
91 .chip_select = 1,
92 .max_speed_hz = 250 * 1000,
93 },
94 { /* User accessible spi - cs2 (1MHz) */
95 .modalias = "spi-cs2",
96 .chip_select = 2,
97 .max_speed_hz = 1 * 1000 * 1000,
98 },
99 { /* User accessible spi - cs3 (10MHz) */
100 .modalias = "spi-cs3",
101 .chip_select = 3,
102 .max_speed_hz = 10 * 1000 * 1000,
103 },
104};
105
106static struct gpio_led carmeva_leds[] = {
107 { /* "user led 1", LED9 */
108 .name = "led9",
109 .gpio = AT91_PIN_PA21,
110 .active_low = 1,
111 .default_trigger = "heartbeat",
112 },
113 { /* "user led 2", LED10 */
114 .name = "led10",
115 .gpio = AT91_PIN_PA25,
116 .active_low = 1,
117 },
118 { /* "user led 3", LED11 */
119 .name = "led11",
120 .gpio = AT91_PIN_PA26,
121 .active_low = 1,
122 },
123 { /* "user led 4", LED12 */
124 .name = "led12",
125 .gpio = AT91_PIN_PA18,
126 .active_low = 1,
127 }
128};
129
130static void __init carmeva_board_init(void)
131{
132 /* Serial */
133 /* DBGU on ttyS0. (Rx & Tx only) */
134 at91_register_uart(0, 0, 0);
135
136 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
137 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
138 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
139 | ATMEL_UART_RI);
140 at91_add_device_serial();
141 /* Ethernet */
142 at91_add_device_eth(&carmeva_eth_data);
143 /* USB Host */
144 at91_add_device_usbh(&carmeva_usbh_data);
145 /* USB Device */
146 at91_add_device_udc(&carmeva_udc_data);
147 /* I2C */
148 at91_add_device_i2c(NULL, 0);
149 /* SPI */
150 at91_add_device_spi(carmeva_spi_devices, ARRAY_SIZE(carmeva_spi_devices));
151 /* Compact Flash */
152// at91_add_device_cf(&carmeva_cf_data);
153 /* MMC */
154 at91_add_device_mci(0, &carmeva_mci0_data);
155 /* LEDs */
156 at91_gpio_leds(carmeva_leds, ARRAY_SIZE(carmeva_leds));
157}
158
159MACHINE_START(CARMEVA, "Carmeva")
160 /* Maintainer: Conitec Datasystems */
161 .init_time = at91rm9200_timer_init,
162 .map_io = at91_map_io,
163 .handle_irq = at91_aic_handle_irq,
164 .init_early = carmeva_init_early,
165 .init_irq = at91_init_irq_default,
166 .init_machine = carmeva_board_init,
167MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
deleted file mode 100644
index c094350c9314..000000000000
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ /dev/null
@@ -1,189 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-cpuat91.c
3 *
4 * Copyright (C) 2009 Eric Benard - eric@eukrea.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/gpio.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/mtd/physmap.h>
28#include <linux/mtd/plat-ram.h>
29
30#include <mach/hardware.h>
31#include <asm/setup.h>
32#include <asm/mach-types.h>
33#include <asm/irq.h>
34
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/irq.h>
38
39#include <mach/at91rm9200_mc.h>
40#include <mach/at91_ramc.h>
41#include <mach/cpu.h>
42
43#include "at91_aic.h"
44#include "board.h"
45#include "generic.h"
46#include "gpio.h"
47
48
49static struct gpio_led cpuat91_leds[] = {
50 {
51 .name = "led1",
52 .default_trigger = "heartbeat",
53 .active_low = 1,
54 .gpio = AT91_PIN_PC0,
55 },
56};
57
58static void __init cpuat91_init_early(void)
59{
60 /* Set cpu type: PQFP */
61 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
62
63 /* Initialize processor: 18.432 MHz crystal */
64 at91_initialize(18432000);
65}
66
67static struct macb_platform_data __initdata cpuat91_eth_data = {
68 .phy_irq_pin = -EINVAL,
69 .is_rmii = 1,
70};
71
72static struct at91_usbh_data __initdata cpuat91_usbh_data = {
73 .ports = 1,
74 .vbus_pin = {-EINVAL, -EINVAL},
75 .overcurrent_pin= {-EINVAL, -EINVAL},
76};
77
78static struct at91_udc_data __initdata cpuat91_udc_data = {
79 .vbus_pin = AT91_PIN_PC15,
80 .pullup_pin = AT91_PIN_PC14,
81};
82
83static struct mci_platform_data __initdata cpuat91_mci0_data = {
84 .slot[0] = {
85 .bus_width = 4,
86 .detect_pin = AT91_PIN_PC2,
87 .wp_pin = -EINVAL,
88 },
89};
90
91static struct physmap_flash_data cpuat91_flash_data = {
92 .width = 2,
93};
94
95static struct resource cpuat91_flash_resource = {
96 .start = AT91_CHIPSELECT_0,
97 .end = AT91_CHIPSELECT_0 + SZ_16M - 1,
98 .flags = IORESOURCE_MEM,
99};
100
101static struct platform_device cpuat91_norflash = {
102 .name = "physmap-flash",
103 .id = 0,
104 .dev = {
105 .platform_data = &cpuat91_flash_data,
106 },
107 .resource = &cpuat91_flash_resource,
108 .num_resources = 1,
109};
110
111#ifdef CONFIG_MTD_PLATRAM
112struct platdata_mtd_ram at91_sram_pdata = {
113 .mapname = "SRAM",
114 .bankwidth = 2,
115};
116
117static struct resource at91_sram_resource[] = {
118 [0] = {
119 .start = AT91RM9200_SRAM_BASE,
120 .end = AT91RM9200_SRAM_BASE + AT91RM9200_SRAM_SIZE - 1,
121 .flags = IORESOURCE_MEM,
122 },
123};
124
125static struct platform_device at91_sram = {
126 .name = "mtd-ram",
127 .id = 0,
128 .resource = at91_sram_resource,
129 .num_resources = ARRAY_SIZE(at91_sram_resource),
130 .dev = {
131 .platform_data = &at91_sram_pdata,
132 },
133};
134#endif /* MTD_PLATRAM */
135
136static struct platform_device *platform_devices[] __initdata = {
137 &cpuat91_norflash,
138#ifdef CONFIG_MTD_PLATRAM
139 &at91_sram,
140#endif /* CONFIG_MTD_PLATRAM */
141};
142
143static void __init cpuat91_board_init(void)
144{
145 /* Serial */
146 /* DBGU on ttyS0. (Rx & Tx only) */
147 at91_register_uart(0, 0, 0);
148
149 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
150 at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS |
151 ATMEL_UART_RTS);
152
153 /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
154 at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS |
155 ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
156 ATMEL_UART_DCD | ATMEL_UART_RI);
157
158 /* USART2 on ttyS3 (Rx, Tx) */
159 at91_register_uart(AT91RM9200_ID_US2, 3, 0);
160
161 /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */
162 at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS |
163 ATMEL_UART_RTS);
164 at91_add_device_serial();
165 /* LEDs. */
166 at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds));
167 /* Ethernet */
168 at91_add_device_eth(&cpuat91_eth_data);
169 /* USB Host */
170 at91_add_device_usbh(&cpuat91_usbh_data);
171 /* USB Device */
172 at91_add_device_udc(&cpuat91_udc_data);
173 /* MMC */
174 at91_add_device_mci(0, &cpuat91_mci0_data);
175 /* I2C */
176 at91_add_device_i2c(NULL, 0);
177 /* Platform devices */
178 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
179}
180
181MACHINE_START(CPUAT91, "Eukrea")
182 /* Maintainer: Eric Benard - EUKREA Electromatique */
183 .init_time = at91rm9200_timer_init,
184 .map_io = at91_map_io,
185 .handle_irq = at91_aic_handle_irq,
186 .init_early = cpuat91_init_early,
187 .init_irq = at91_init_irq_default,
188 .init_machine = cpuat91_board_init,
189MACHINE_END
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
deleted file mode 100644
index 0e35a45cf8d4..000000000000
--- a/arch/arm/mach-at91/board-csb337.c
+++ /dev/null
@@ -1,260 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-csb337.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/gpio.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/spi/spi.h>
28#include <linux/mtd/physmap.h>
29#include <linux/input.h>
30#include <linux/gpio_keys.h>
31
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/irq.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39
40#include <mach/hardware.h>
41
42#include "at91_aic.h"
43#include "board.h"
44#include "generic.h"
45#include "gpio.h"
46
47static void __init csb337_init_early(void)
48{
49 /* Initialize processor: 3.6864 MHz crystal */
50 at91_initialize(3686400);
51}
52
53static struct macb_platform_data __initdata csb337_eth_data = {
54 .phy_irq_pin = AT91_PIN_PC2,
55 .is_rmii = 0,
56 /* The CSB337 bootloader stores the MAC the wrong-way around */
57 .rev_eth_addr = 1,
58};
59
60static struct at91_usbh_data __initdata csb337_usbh_data = {
61 .ports = 2,
62 .vbus_pin = {-EINVAL, -EINVAL},
63 .overcurrent_pin= {-EINVAL, -EINVAL},
64};
65
66static struct at91_udc_data __initdata csb337_udc_data = {
67 .pullup_pin = AT91_PIN_PA24,
68 .vbus_pin = -EINVAL,
69};
70
71static struct i2c_board_info __initdata csb337_i2c_devices[] = {
72 {
73 I2C_BOARD_INFO("ds1307", 0x68),
74 },
75};
76
77static struct at91_cf_data __initdata csb337_cf_data = {
78 /*
79 * connector P4 on the CSB 337 mates to
80 * connector P8 on the CSB 300CF
81 */
82
83 /* CSB337 specific */
84 .det_pin = AT91_PIN_PC3,
85
86 /* CSB300CF specific */
87 .irq_pin = AT91_PIN_PA19,
88 .vcc_pin = AT91_PIN_PD0,
89 .rst_pin = AT91_PIN_PD2,
90};
91
92static struct mci_platform_data __initdata csb337_mci0_data = {
93 .slot[0] = {
94 .bus_width = 4,
95 .detect_pin = AT91_PIN_PD5,
96 .wp_pin = AT91_PIN_PD6,
97 },
98};
99
100static struct spi_board_info csb337_spi_devices[] = {
101 { /* CAN controller */
102 .modalias = "sak82c900",
103 .chip_select = 0,
104 .max_speed_hz = 6 * 1000 * 1000,
105 },
106};
107
108#define CSB_FLASH_BASE AT91_CHIPSELECT_0
109#define CSB_FLASH_SIZE SZ_8M
110
111static struct mtd_partition csb_flash_partitions[] = {
112 {
113 .name = "uMON flash",
114 .offset = 0,
115 .size = MTDPART_SIZ_FULL,
116 .mask_flags = MTD_WRITEABLE, /* read only */
117 }
118};
119
120static struct physmap_flash_data csb_flash_data = {
121 .width = 2,
122 .parts = csb_flash_partitions,
123 .nr_parts = ARRAY_SIZE(csb_flash_partitions),
124};
125
126static struct resource csb_flash_resources[] = {
127 {
128 .start = CSB_FLASH_BASE,
129 .end = CSB_FLASH_BASE + CSB_FLASH_SIZE - 1,
130 .flags = IORESOURCE_MEM,
131 }
132};
133
134static struct platform_device csb_flash = {
135 .name = "physmap-flash",
136 .id = 0,
137 .dev = {
138 .platform_data = &csb_flash_data,
139 },
140 .resource = csb_flash_resources,
141 .num_resources = ARRAY_SIZE(csb_flash_resources),
142};
143
144/*
145 * GPIO Buttons (on CSB300)
146 */
147#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
148static struct gpio_keys_button csb300_buttons[] = {
149 {
150 .gpio = AT91_PIN_PB29,
151 .code = BTN_0,
152 .desc = "sw0",
153 .active_low = 1,
154 .wakeup = 1,
155 },
156 {
157 .gpio = AT91_PIN_PB28,
158 .code = BTN_1,
159 .desc = "sw1",
160 .active_low = 1,
161 .wakeup = 1,
162 },
163 {
164 .gpio = AT91_PIN_PA21,
165 .code = BTN_2,
166 .desc = "sw2",
167 .active_low = 1,
168 .wakeup = 1,
169 }
170};
171
172static struct gpio_keys_platform_data csb300_button_data = {
173 .buttons = csb300_buttons,
174 .nbuttons = ARRAY_SIZE(csb300_buttons),
175};
176
177static struct platform_device csb300_button_device = {
178 .name = "gpio-keys",
179 .id = -1,
180 .num_resources = 0,
181 .dev = {
182 .platform_data = &csb300_button_data,
183 }
184};
185
186static void __init csb300_add_device_buttons(void)
187{
188 at91_set_gpio_input(AT91_PIN_PB29, 1); /* sw0 */
189 at91_set_deglitch(AT91_PIN_PB29, 1);
190 at91_set_gpio_input(AT91_PIN_PB28, 1); /* sw1 */
191 at91_set_deglitch(AT91_PIN_PB28, 1);
192 at91_set_gpio_input(AT91_PIN_PA21, 1); /* sw2 */
193 at91_set_deglitch(AT91_PIN_PA21, 1);
194
195 platform_device_register(&csb300_button_device);
196}
197#else
198static void __init csb300_add_device_buttons(void) {}
199#endif
200
201static struct gpio_led csb_leds[] = {
202 { /* "led0", yellow */
203 .name = "led0",
204 .gpio = AT91_PIN_PB2,
205 .active_low = 1,
206 .default_trigger = "heartbeat",
207 },
208 { /* "led1", green */
209 .name = "led1",
210 .gpio = AT91_PIN_PB1,
211 .active_low = 1,
212 .default_trigger = "mmc0",
213 },
214 { /* "led2", yellow */
215 .name = "led2",
216 .gpio = AT91_PIN_PB0,
217 .active_low = 1,
218 .default_trigger = "ide-disk",
219 }
220};
221
222
223static void __init csb337_board_init(void)
224{
225 /* Serial */
226 /* DBGU on ttyS0 */
227 at91_register_uart(0, 0, 0);
228 at91_add_device_serial();
229 /* Ethernet */
230 at91_add_device_eth(&csb337_eth_data);
231 /* USB Host */
232 at91_add_device_usbh(&csb337_usbh_data);
233 /* USB Device */
234 at91_add_device_udc(&csb337_udc_data);
235 /* I2C */
236 at91_add_device_i2c(csb337_i2c_devices, ARRAY_SIZE(csb337_i2c_devices));
237 /* Compact Flash */
238 at91_set_gpio_input(AT91_PIN_PB22, 1); /* IOIS16 */
239 at91_add_device_cf(&csb337_cf_data);
240 /* SPI */
241 at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices));
242 /* MMC */
243 at91_add_device_mci(0, &csb337_mci0_data);
244 /* NOR flash */
245 platform_device_register(&csb_flash);
246 /* LEDs */
247 at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
248 /* Switches on CSB300 */
249 csb300_add_device_buttons();
250}
251
252MACHINE_START(CSB337, "Cogent CSB337")
253 /* Maintainer: Bill Gatliff */
254 .init_time = at91rm9200_timer_init,
255 .map_io = at91_map_io,
256 .handle_irq = at91_aic_handle_irq,
257 .init_early = csb337_init_early,
258 .init_irq = at91_init_irq_default,
259 .init_machine = csb337_board_init,
260MACHINE_END
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
deleted file mode 100644
index 18d027f529a8..000000000000
--- a/arch/arm/mach-at91/board-csb637.c
+++ /dev/null
@@ -1,142 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-csb637.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/init.h>
23#include <linux/gpio.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/mtd/physmap.h>
28
29#include <asm/setup.h>
30#include <asm/mach-types.h>
31#include <asm/irq.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/hardware.h>
38
39#include "at91_aic.h"
40#include "board.h"
41#include "generic.h"
42#include "gpio.h"
43
44
45static void __init csb637_init_early(void)
46{
47 /* Initialize processor: 3.6864 MHz crystal */
48 at91_initialize(3686400);
49}
50
51static struct macb_platform_data __initdata csb637_eth_data = {
52 .phy_irq_pin = AT91_PIN_PC0,
53 .is_rmii = 0,
54};
55
56static struct at91_usbh_data __initdata csb637_usbh_data = {
57 .ports = 2,
58 .vbus_pin = {-EINVAL, -EINVAL},
59 .overcurrent_pin= {-EINVAL, -EINVAL},
60};
61
62static struct at91_udc_data __initdata csb637_udc_data = {
63 .vbus_pin = AT91_PIN_PB28,
64 .pullup_pin = AT91_PIN_PB1,
65};
66
67#define CSB_FLASH_BASE AT91_CHIPSELECT_0
68#define CSB_FLASH_SIZE SZ_16M
69
70static struct mtd_partition csb_flash_partitions[] = {
71 {
72 .name = "uMON flash",
73 .offset = 0,
74 .size = MTDPART_SIZ_FULL,
75 .mask_flags = MTD_WRITEABLE, /* read only */
76 }
77};
78
79static struct physmap_flash_data csb_flash_data = {
80 .width = 2,
81 .parts = csb_flash_partitions,
82 .nr_parts = ARRAY_SIZE(csb_flash_partitions),
83};
84
85static struct resource csb_flash_resources[] = {
86 {
87 .start = CSB_FLASH_BASE,
88 .end = CSB_FLASH_BASE + CSB_FLASH_SIZE - 1,
89 .flags = IORESOURCE_MEM,
90 }
91};
92
93static struct platform_device csb_flash = {
94 .name = "physmap-flash",
95 .id = 0,
96 .dev = {
97 .platform_data = &csb_flash_data,
98 },
99 .resource = csb_flash_resources,
100 .num_resources = ARRAY_SIZE(csb_flash_resources),
101};
102
103static struct gpio_led csb_leds[] = {
104 { /* "d1", red */
105 .name = "d1",
106 .gpio = AT91_PIN_PB2,
107 .active_low = 1,
108 .default_trigger = "heartbeat",
109 },
110};
111
112static void __init csb637_board_init(void)
113{
114 /* LED(s) */
115 at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
116 /* Serial */
117 /* DBGU on ttyS0. (Rx & Tx only) */
118 at91_register_uart(0, 0, 0);
119 at91_add_device_serial();
120 /* Ethernet */
121 at91_add_device_eth(&csb637_eth_data);
122 /* USB Host */
123 at91_add_device_usbh(&csb637_usbh_data);
124 /* USB Device */
125 at91_add_device_udc(&csb637_udc_data);
126 /* I2C */
127 at91_add_device_i2c(NULL, 0);
128 /* SPI */
129 at91_add_device_spi(NULL, 0);
130 /* NOR flash */
131 platform_device_register(&csb_flash);
132}
133
134MACHINE_START(CSB637, "Cogent CSB637")
135 /* Maintainer: Bill Gatliff */
136 .init_time = at91rm9200_timer_init,
137 .map_io = at91_map_io,
138 .handle_irq = at91_aic_handle_irq,
139 .init_early = csb637_init_early,
140 .init_irq = at91_init_irq_default,
141 .init_machine = csb637_board_init,
142MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 226563f850b8..feeb1a0f258e 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -22,7 +22,6 @@
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
23#include <asm/mach/irq.h> 23#include <asm/mach/irq.h>
24 24
25#include "at91_aic.h"
26#include "generic.h" 25#include "generic.h"
27 26
28static void __init at91rm9200_dt_timer_init(void) 27static void __init at91rm9200_dt_timer_init(void)
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index d3048ccdc41f..67c1bcbf0ed9 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -21,7 +21,6 @@
21#include <asm/mach/map.h> 21#include <asm/mach/map.h>
22#include <asm/mach/irq.h> 22#include <asm/mach/irq.h>
23 23
24#include "at91_aic.h"
25#include "board.h" 24#include "board.h"
26#include "generic.h" 25#include "generic.h"
27 26
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 129e2917506b..8fb9ef5333f1 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -24,7 +24,6 @@
24#include <asm/mach/map.h> 24#include <asm/mach/map.h>
25#include <asm/mach/irq.h> 25#include <asm/mach/irq.h>
26 26
27#include "at91_aic.h"
28#include "generic.h" 27#include "generic.h"
29 28
30static void __init sama5_dt_device_init(void) 29static void __init sama5_dt_device_init(void)
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
deleted file mode 100644
index aa457a8b22f5..000000000000
--- a/arch/arm/mach-at91/board-eb9200.c
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-eb9200.c
3 *
4 * Copyright (C) 2005 SAN People, adapted for ATEB9200 from Embest
5 * by Andrew Patrikalakis
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/device.h>
28
29#include <mach/hardware.h>
30#include <asm/setup.h>
31#include <asm/mach-types.h>
32#include <asm/irq.h>
33
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36#include <asm/mach/irq.h>
37
38#include "at91_aic.h"
39#include "board.h"
40#include "generic.h"
41#include "gpio.h"
42
43
44static void __init eb9200_init_early(void)
45{
46 /* Initialize processor: 18.432 MHz crystal */
47 at91_initialize(18432000);
48}
49
50static struct macb_platform_data __initdata eb9200_eth_data = {
51 .phy_irq_pin = AT91_PIN_PC4,
52 .is_rmii = 1,
53};
54
55static struct at91_usbh_data __initdata eb9200_usbh_data = {
56 .ports = 2,
57 .vbus_pin = {-EINVAL, -EINVAL},
58 .overcurrent_pin= {-EINVAL, -EINVAL},
59};
60
61static struct at91_udc_data __initdata eb9200_udc_data = {
62 .vbus_pin = AT91_PIN_PD4,
63 .pullup_pin = AT91_PIN_PD5,
64};
65
66static struct at91_cf_data __initdata eb9200_cf_data = {
67 .irq_pin = -EINVAL,
68 .det_pin = AT91_PIN_PB0,
69 .vcc_pin = -EINVAL,
70 .rst_pin = AT91_PIN_PC5,
71};
72
73static struct mci_platform_data __initdata eb9200_mci0_data = {
74 .slot[0] = {
75 .bus_width = 4,
76 .detect_pin = -EINVAL,
77 .wp_pin = -EINVAL,
78 },
79};
80
81static struct i2c_board_info __initdata eb9200_i2c_devices[] = {
82 {
83 I2C_BOARD_INFO("24c512", 0x50),
84 },
85};
86
87
88static void __init eb9200_board_init(void)
89{
90 /* Serial */
91 /* DBGU on ttyS0. (Rx & Tx only) */
92 at91_register_uart(0, 0, 0);
93
94 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
95 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
96 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
97 | ATMEL_UART_RI);
98
99 /* USART2 on ttyS2. (Rx, Tx) - IRDA */
100 at91_register_uart(AT91RM9200_ID_US2, 2, 0);
101 at91_add_device_serial();
102 /* Ethernet */
103 at91_add_device_eth(&eb9200_eth_data);
104 /* USB Host */
105 at91_add_device_usbh(&eb9200_usbh_data);
106 /* USB Device */
107 at91_add_device_udc(&eb9200_udc_data);
108 /* I2C */
109 at91_add_device_i2c(eb9200_i2c_devices, ARRAY_SIZE(eb9200_i2c_devices));
110 /* Compact Flash */
111 at91_add_device_cf(&eb9200_cf_data);
112 /* SPI */
113 at91_add_device_spi(NULL, 0);
114 /* MMC */
115 /* only supports 1 or 4 bit interface, not wired through to SPI */
116 at91_add_device_mci(0, &eb9200_mci0_data);
117}
118
119MACHINE_START(ATEB9200, "Embest ATEB9200")
120 .init_time = at91rm9200_timer_init,
121 .map_io = at91_map_io,
122 .handle_irq = at91_aic_handle_irq,
123 .init_early = eb9200_init_early,
124 .init_irq = at91_init_irq_default,
125 .init_machine = eb9200_board_init,
126MACHINE_END
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
deleted file mode 100644
index ede1373ccaba..000000000000
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ /dev/null
@@ -1,191 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91rm9200/board-ecbat91.c
3 * Copyright (C) 2007 emQbit.com.
4 *
5 * We started from board-dk.c, which is Copyright (C) 2005 SAN People.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/flash.h>
30
31#include <mach/hardware.h>
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/irq.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39
40#include <mach/cpu.h>
41
42#include "at91_aic.h"
43#include "board.h"
44#include "generic.h"
45#include "gpio.h"
46
47
48static void __init ecb_at91init_early(void)
49{
50 /* Set cpu type: PQFP */
51 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
52
53 /* Initialize processor: 18.432 MHz crystal */
54 at91_initialize(18432000);
55}
56
57static struct macb_platform_data __initdata ecb_at91eth_data = {
58 .phy_irq_pin = AT91_PIN_PC4,
59 .is_rmii = 0,
60};
61
62static struct at91_usbh_data __initdata ecb_at91usbh_data = {
63 .ports = 1,
64 .vbus_pin = {-EINVAL, -EINVAL},
65 .overcurrent_pin= {-EINVAL, -EINVAL},
66};
67
68static struct mci_platform_data __initdata ecbat91_mci0_data = {
69 .slot[0] = {
70 .bus_width = 4,
71 .detect_pin = -EINVAL,
72 .wp_pin = -EINVAL,
73 },
74};
75
76
77#if defined(CONFIG_MTD_DATAFLASH)
78static struct mtd_partition __initdata my_flash0_partitions[] =
79{
80 { /* 0x8400 */
81 .name = "Darrell-loader",
82 .offset = 0,
83 .size = 12 * 1056,
84 },
85 {
86 .name = "U-boot",
87 .offset = MTDPART_OFS_NXTBLK,
88 .size = 110 * 1056,
89 },
90 { /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
91 .name = "UBoot-env",
92 .offset = MTDPART_OFS_NXTBLK,
93 .size = 8 * 1056,
94 },
95 { /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
96 .name = "Kernel",
97 .offset = MTDPART_OFS_NXTBLK,
98 .size = 1534 * 1056,
99 },
100 { /* 190200 - jffs2 root filesystem */
101 .name = "Filesystem",
102 .offset = MTDPART_OFS_NXTBLK,
103 .size = MTDPART_SIZ_FULL, /* 26 sectors */
104 }
105};
106
107static struct flash_platform_data __initdata my_flash0_platform = {
108 .name = "Removable flash card",
109 .parts = my_flash0_partitions,
110 .nr_parts = ARRAY_SIZE(my_flash0_partitions)
111};
112
113#endif
114
115static struct spi_board_info __initdata ecb_at91spi_devices[] = {
116 { /* DataFlash chip */
117 .modalias = "mtd_dataflash",
118 .chip_select = 0,
119 .max_speed_hz = 10 * 1000 * 1000,
120 .bus_num = 0,
121#if defined(CONFIG_MTD_DATAFLASH)
122 .platform_data = &my_flash0_platform,
123#endif
124 },
125 { /* User accessible spi - cs1 (250KHz) */
126 .modalias = "spi-cs1",
127 .chip_select = 1,
128 .max_speed_hz = 250 * 1000,
129 },
130 { /* User accessible spi - cs2 (1MHz) */
131 .modalias = "spi-cs2",
132 .chip_select = 2,
133 .max_speed_hz = 1 * 1000 * 1000,
134 },
135 { /* User accessible spi - cs3 (10MHz) */
136 .modalias = "spi-cs3",
137 .chip_select = 3,
138 .max_speed_hz = 10 * 1000 * 1000,
139 },
140};
141
142/*
143 * LEDs
144 */
145static struct gpio_led ecb_leds[] = {
146 { /* D1 */
147 .name = "led1",
148 .gpio = AT91_PIN_PC7,
149 .active_low = 1,
150 .default_trigger = "heartbeat",
151 }
152};
153
154static void __init ecb_at91board_init(void)
155{
156 /* Serial */
157 /* DBGU on ttyS0. (Rx & Tx only) */
158 at91_register_uart(0, 0, 0);
159
160 /* USART0 on ttyS1. (Rx & Tx only) */
161 at91_register_uart(AT91RM9200_ID_US0, 1, 0);
162 at91_add_device_serial();
163
164 /* Ethernet */
165 at91_add_device_eth(&ecb_at91eth_data);
166
167 /* USB Host */
168 at91_add_device_usbh(&ecb_at91usbh_data);
169
170 /* I2C */
171 at91_add_device_i2c(NULL, 0);
172
173 /* MMC */
174 at91_add_device_mci(0, &ecbat91_mci0_data);
175
176 /* SPI */
177 at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
178
179 /* LEDs */
180 at91_gpio_leds(ecb_leds, ARRAY_SIZE(ecb_leds));
181}
182
183MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
184 /* Maintainer: emQbit.com */
185 .init_time = at91rm9200_timer_init,
186 .map_io = at91_map_io,
187 .handle_irq = at91_aic_handle_irq,
188 .init_early = ecb_at91init_early,
189 .init_irq = at91_init_irq_default,
190 .init_machine = ecb_at91board_init,
191MACHINE_END
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
deleted file mode 100644
index 4e75321a8f2a..000000000000
--- a/arch/arm/mach-at91/board-eco920.c
+++ /dev/null
@@ -1,160 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
20#include <linux/gpio.h>
21
22#include <asm/mach-types.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26
27#include <mach/at91rm9200_mc.h>
28#include <mach/at91_ramc.h>
29#include <mach/cpu.h>
30
31#include "at91_aic.h"
32#include "board.h"
33#include "generic.h"
34#include "gpio.h"
35
36
37static void __init eco920_init_early(void)
38{
39 /* Set cpu type: PQFP */
40 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
41
42 at91_initialize(18432000);
43}
44
45static struct macb_platform_data __initdata eco920_eth_data = {
46 .phy_irq_pin = AT91_PIN_PC2,
47 .is_rmii = 1,
48};
49
50static struct at91_usbh_data __initdata eco920_usbh_data = {
51 .ports = 1,
52 .vbus_pin = {-EINVAL, -EINVAL},
53 .overcurrent_pin= {-EINVAL, -EINVAL},
54};
55
56static struct at91_udc_data __initdata eco920_udc_data = {
57 .vbus_pin = AT91_PIN_PB12,
58 .pullup_pin = AT91_PIN_PB13,
59};
60
61static struct mci_platform_data __initdata eco920_mci0_data = {
62 .slot[0] = {
63 .bus_width = 1,
64 .detect_pin = -EINVAL,
65 .wp_pin = -EINVAL,
66 },
67};
68
69static struct physmap_flash_data eco920_flash_data = {
70 .width = 2,
71};
72
73static struct resource eco920_flash_resource = {
74 .start = 0x11000000,
75 .end = 0x11ffffff,
76 .flags = IORESOURCE_MEM,
77};
78
79static struct platform_device eco920_flash = {
80 .name = "physmap-flash",
81 .id = 0,
82 .dev = {
83 .platform_data = &eco920_flash_data,
84 },
85 .resource = &eco920_flash_resource,
86 .num_resources = 1,
87};
88
89static struct spi_board_info eco920_spi_devices[] = {
90 { /* CAN controller */
91 .modalias = "tlv5638",
92 .chip_select = 3,
93 .max_speed_hz = 20 * 1000 * 1000,
94 .mode = SPI_CPHA,
95 },
96};
97
98/*
99 * LEDs
100 */
101static struct gpio_led eco920_leds[] = {
102 { /* D1 */
103 .name = "led1",
104 .gpio = AT91_PIN_PB0,
105 .active_low = 1,
106 .default_trigger = "heartbeat",
107 },
108 { /* D2 */
109 .name = "led2",
110 .gpio = AT91_PIN_PB1,
111 .active_low = 1,
112 .default_trigger = "timer",
113 }
114};
115
116static void __init eco920_board_init(void)
117{
118 /* DBGU on ttyS0. (Rx & Tx only */
119 at91_register_uart(0, 0, 0);
120 at91_add_device_serial();
121 at91_add_device_eth(&eco920_eth_data);
122 at91_add_device_usbh(&eco920_usbh_data);
123 at91_add_device_udc(&eco920_udc_data);
124
125 at91_add_device_mci(0, &eco920_mci0_data);
126 platform_device_register(&eco920_flash);
127
128 at91_ramc_write(0, AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
129 | AT91_SMC_RWSETUP_(1)
130 | AT91_SMC_DBW_8
131 | AT91_SMC_WSEN
132 | AT91_SMC_NWS_(15));
133
134 at91_set_A_periph(AT91_PIN_PC6, 1);
135
136 at91_set_gpio_input(AT91_PIN_PA23, 0);
137 at91_set_deglitch(AT91_PIN_PA23, 1);
138
139/* Initialization of the Static Memory Controller for Chip Select 3 */
140 at91_ramc_write(0, AT91_SMC_CSR(3),
141 AT91_SMC_DBW_16 | /* 16 bit */
142 AT91_SMC_WSEN |
143 AT91_SMC_NWS_(5) | /* wait states */
144 AT91_SMC_TDF_(1) /* float time */
145 );
146
147 at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));
148 /* LEDs */
149 at91_gpio_leds(eco920_leds, ARRAY_SIZE(eco920_leds));
150}
151
152MACHINE_START(ECO920, "eco920")
153 /* Maintainer: Sascha Hauer */
154 .init_time = at91rm9200_timer_init,
155 .map_io = at91_map_io,
156 .handle_irq = at91_aic_handle_irq,
157 .init_early = eco920_init_early,
158 .init_irq = at91_init_irq_default,
159 .init_machine = eco920_board_init,
160MACHINE_END
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
deleted file mode 100644
index 93b1df42f639..000000000000
--- a/arch/arm/mach-at91/board-kafa.c
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-kafa.c
3 *
4 * Copyright (C) 2006 Sperry-Sun
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/gpio.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27
28#include <mach/hardware.h>
29#include <asm/setup.h>
30#include <asm/mach-types.h>
31#include <asm/irq.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/cpu.h>
38
39#include "at91_aic.h"
40#include "board.h"
41#include "generic.h"
42#include "gpio.h"
43
44
45static void __init kafa_init_early(void)
46{
47 /* Set cpu type: PQFP */
48 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
49
50 /* Initialize processor: 18.432 MHz crystal */
51 at91_initialize(18432000);
52}
53
54static struct macb_platform_data __initdata kafa_eth_data = {
55 .phy_irq_pin = AT91_PIN_PC4,
56 .is_rmii = 0,
57};
58
59static struct at91_usbh_data __initdata kafa_usbh_data = {
60 .ports = 1,
61 .vbus_pin = {-EINVAL, -EINVAL},
62 .overcurrent_pin= {-EINVAL, -EINVAL},
63};
64
65static struct at91_udc_data __initdata kafa_udc_data = {
66 .vbus_pin = AT91_PIN_PB6,
67 .pullup_pin = AT91_PIN_PB7,
68};
69
70/*
71 * LEDs
72 */
73static struct gpio_led kafa_leds[] = {
74 { /* D1 */
75 .name = "led1",
76 .gpio = AT91_PIN_PB4,
77 .active_low = 1,
78 .default_trigger = "heartbeat",
79 },
80};
81
82static void __init kafa_board_init(void)
83{
84 /* Serial */
85 /* DBGU on ttyS0. (Rx & Tx only) */
86 at91_register_uart(0, 0, 0);
87
88 /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
89 at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
90 at91_add_device_serial();
91 /* Ethernet */
92 at91_add_device_eth(&kafa_eth_data);
93 /* USB Host */
94 at91_add_device_usbh(&kafa_usbh_data);
95 /* USB Device */
96 at91_add_device_udc(&kafa_udc_data);
97 /* I2C */
98 at91_add_device_i2c(NULL, 0);
99 /* SPI */
100 at91_add_device_spi(NULL, 0);
101 /* LEDs */
102 at91_gpio_leds(kafa_leds, ARRAY_SIZE(kafa_leds));
103}
104
105MACHINE_START(KAFA, "Sperry-Sun KAFA")
106 /* Maintainer: Sergei Sharonov */
107 .init_time = at91rm9200_timer_init,
108 .map_io = at91_map_io,
109 .handle_irq = at91_aic_handle_irq,
110 .init_early = kafa_init_early,
111 .init_irq = at91_init_irq_default,
112 .init_machine = kafa_board_init,
113MACHINE_END
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
deleted file mode 100644
index d58d36225e08..000000000000
--- a/arch/arm/mach-at91/board-kb9202.c
+++ /dev/null
@@ -1,159 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-kb9202.c
3 *
4 * Copyright (c) 2005 kb_admin
5 * KwikByte, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28
29#include <mach/hardware.h>
30#include <asm/setup.h>
31#include <asm/mach-types.h>
32#include <asm/irq.h>
33
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36#include <asm/mach/irq.h>
37
38#include <mach/cpu.h>
39#include <mach/at91rm9200_mc.h>
40#include <mach/at91_ramc.h>
41
42#include "at91_aic.h"
43#include "board.h"
44#include "generic.h"
45#include "gpio.h"
46
47
48static void __init kb9202_init_early(void)
49{
50 /* Set cpu type: PQFP */
51 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
52
53 /* Initialize processor: 10 MHz crystal */
54 at91_initialize(10000000);
55}
56
57static struct macb_platform_data __initdata kb9202_eth_data = {
58 .phy_irq_pin = AT91_PIN_PB29,
59 .is_rmii = 0,
60};
61
62static struct at91_usbh_data __initdata kb9202_usbh_data = {
63 .ports = 1,
64 .vbus_pin = {-EINVAL, -EINVAL},
65 .overcurrent_pin= {-EINVAL, -EINVAL},
66};
67
68static struct at91_udc_data __initdata kb9202_udc_data = {
69 .vbus_pin = AT91_PIN_PB24,
70 .pullup_pin = AT91_PIN_PB22,
71};
72
73static struct mci_platform_data __initdata kb9202_mci0_data = {
74 .slot[0] = {
75 .bus_width = 4,
76 .detect_pin = AT91_PIN_PB2,
77 .wp_pin = -EINVAL,
78 },
79};
80
81static struct mtd_partition __initdata kb9202_nand_partition[] = {
82 {
83 .name = "nand_fs",
84 .offset = 0,
85 .size = MTDPART_SIZ_FULL,
86 },
87};
88
89static struct atmel_nand_data __initdata kb9202_nand_data = {
90 .ale = 22,
91 .cle = 21,
92 .det_pin = -EINVAL,
93 .rdy_pin = AT91_PIN_PC29,
94 .enable_pin = AT91_PIN_PC28,
95 .ecc_mode = NAND_ECC_SOFT,
96 .parts = kb9202_nand_partition,
97 .num_parts = ARRAY_SIZE(kb9202_nand_partition),
98};
99
100/*
101 * LEDs
102 */
103static struct gpio_led kb9202_leds[] = {
104 { /* D1 */
105 .name = "led1",
106 .gpio = AT91_PIN_PC19,
107 .active_low = 1,
108 .default_trigger = "heartbeat",
109 },
110 { /* D2 */
111 .name = "led2",
112 .gpio = AT91_PIN_PC18,
113 .active_low = 1,
114 .default_trigger = "timer",
115 }
116};
117
118static void __init kb9202_board_init(void)
119{
120 /* Serial */
121 /* DBGU on ttyS0. (Rx & Tx only) */
122 at91_register_uart(0, 0, 0);
123
124 /* USART0 on ttyS1 (Rx & Tx only) */
125 at91_register_uart(AT91RM9200_ID_US0, 1, 0);
126
127 /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
128 at91_register_uart(AT91RM9200_ID_US1, 2, 0);
129
130 /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
131 at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
132 at91_add_device_serial();
133 /* Ethernet */
134 at91_add_device_eth(&kb9202_eth_data);
135 /* USB Host */
136 at91_add_device_usbh(&kb9202_usbh_data);
137 /* USB Device */
138 at91_add_device_udc(&kb9202_udc_data);
139 /* MMC */
140 at91_add_device_mci(0, &kb9202_mci0_data);
141 /* I2C */
142 at91_add_device_i2c(NULL, 0);
143 /* SPI */
144 at91_add_device_spi(NULL, 0);
145 /* NAND */
146 at91_add_device_nand(&kb9202_nand_data);
147 /* LEDs */
148 at91_gpio_leds(kb9202_leds, ARRAY_SIZE(kb9202_leds));
149}
150
151MACHINE_START(KB9200, "KB920x")
152 /* Maintainer: KwikByte, Inc. */
153 .init_time = at91rm9200_timer_init,
154 .map_io = at91_map_io,
155 .handle_irq = at91_aic_handle_irq,
156 .init_early = kb9202_init_early,
157 .init_irq = at91_init_irq_default,
158 .init_machine = kb9202_board_init,
159MACHINE_END
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
deleted file mode 100644
index 2c0f2d554d84..000000000000
--- a/arch/arm/mach-at91/board-picotux200.c
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-picotux200.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Kleinhenz Elektronik GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/mtd/physmap.h>
30
31#include <mach/hardware.h>
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/irq.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39
40#include <mach/at91rm9200_mc.h>
41#include <mach/at91_ramc.h>
42
43#include "at91_aic.h"
44#include "board.h"
45#include "generic.h"
46#include "gpio.h"
47
48
49static void __init picotux200_init_early(void)
50{
51 /* Initialize processor: 18.432 MHz crystal */
52 at91_initialize(18432000);
53}
54
55static struct macb_platform_data __initdata picotux200_eth_data = {
56 .phy_irq_pin = AT91_PIN_PC4,
57 .is_rmii = 1,
58};
59
60static struct at91_usbh_data __initdata picotux200_usbh_data = {
61 .ports = 1,
62 .vbus_pin = {-EINVAL, -EINVAL},
63 .overcurrent_pin= {-EINVAL, -EINVAL},
64};
65
66static struct mci_platform_data __initdata picotux200_mci0_data = {
67 .slot[0] = {
68 .bus_width = 4,
69 .detect_pin = AT91_PIN_PB27,
70 .wp_pin = AT91_PIN_PA17,
71 },
72};
73
74#define PICOTUX200_FLASH_BASE AT91_CHIPSELECT_0
75#define PICOTUX200_FLASH_SIZE SZ_4M
76
77static struct physmap_flash_data picotux200_flash_data = {
78 .width = 2,
79};
80
81static struct resource picotux200_flash_resource = {
82 .start = PICOTUX200_FLASH_BASE,
83 .end = PICOTUX200_FLASH_BASE + PICOTUX200_FLASH_SIZE - 1,
84 .flags = IORESOURCE_MEM,
85};
86
87static struct platform_device picotux200_flash = {
88 .name = "physmap-flash",
89 .id = 0,
90 .dev = {
91 .platform_data = &picotux200_flash_data,
92 },
93 .resource = &picotux200_flash_resource,
94 .num_resources = 1,
95};
96
97static void __init picotux200_board_init(void)
98{
99 /* Serial */
100 /* DBGU on ttyS0. (Rx & Tx only) */
101 at91_register_uart(0, 0, 0);
102
103 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
104 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
105 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
106 | ATMEL_UART_RI);
107 at91_add_device_serial();
108 /* Ethernet */
109 at91_add_device_eth(&picotux200_eth_data);
110 /* USB Host */
111 at91_add_device_usbh(&picotux200_usbh_data);
112 /* I2C */
113 at91_add_device_i2c(NULL, 0);
114 /* MMC */
115 at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
116 at91_add_device_mci(0, &picotux200_mci0_data);
117 /* NOR Flash */
118 platform_device_register(&picotux200_flash);
119}
120
121MACHINE_START(PICOTUX2XX, "picotux 200")
122 /* Maintainer: Kleinhenz Elektronik GmbH */
123 .init_time = at91rm9200_timer_init,
124 .map_io = at91_map_io,
125 .handle_irq = at91_aic_handle_irq,
126 .init_early = picotux200_init_early,
127 .init_irq = at91_init_irq_default,
128 .init_machine = picotux200_board_init,
129MACHINE_END
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
deleted file mode 100644
index 953cea416754..000000000000
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ /dev/null
@@ -1,196 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-rm9200ek.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * Epson S1D framebuffer glue code is:
7 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/types.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/mm.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/spi/spi.h>
31#include <linux/mtd/physmap.h>
32
33#include <asm/setup.h>
34#include <asm/mach-types.h>
35#include <asm/irq.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40
41#include <mach/hardware.h>
42#include <mach/at91rm9200_mc.h>
43#include <mach/at91_ramc.h>
44
45#include "at91_aic.h"
46#include "board.h"
47#include "generic.h"
48#include "gpio.h"
49
50
51static void __init ek_init_early(void)
52{
53 /* Initialize processor: 18.432 MHz crystal */
54 at91_initialize(18432000);
55}
56
57static struct macb_platform_data __initdata ek_eth_data = {
58 .phy_irq_pin = AT91_PIN_PC4,
59 .is_rmii = 1,
60};
61
62static struct at91_usbh_data __initdata ek_usbh_data = {
63 .ports = 2,
64 .vbus_pin = {-EINVAL, -EINVAL},
65 .overcurrent_pin= {-EINVAL, -EINVAL},
66};
67
68static struct at91_udc_data __initdata ek_udc_data = {
69 .vbus_pin = AT91_PIN_PD4,
70 .pullup_pin = AT91_PIN_PD5,
71};
72
73#ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
74static struct mci_platform_data __initdata ek_mci0_data = {
75 .slot[0] = {
76 .bus_width = 4,
77 .detect_pin = AT91_PIN_PB27,
78 .wp_pin = AT91_PIN_PA17,
79 }
80};
81#endif
82
83static struct spi_board_info ek_spi_devices[] = {
84 { /* DataFlash chip */
85 .modalias = "mtd_dataflash",
86 .chip_select = 0,
87 .max_speed_hz = 15 * 1000 * 1000,
88 },
89#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
90 { /* DataFlash card */
91 .modalias = "mtd_dataflash",
92 .chip_select = 3,
93 .max_speed_hz = 15 * 1000 * 1000,
94 },
95#endif
96};
97
98static struct i2c_board_info __initdata ek_i2c_devices[] = {
99 {
100 I2C_BOARD_INFO("ics1523", 0x26),
101 },
102 {
103 I2C_BOARD_INFO("dac3550", 0x4d),
104 }
105};
106
107#define EK_FLASH_BASE AT91_CHIPSELECT_0
108#define EK_FLASH_SIZE SZ_8M
109
110static struct physmap_flash_data ek_flash_data = {
111 .width = 2,
112};
113
114static struct resource ek_flash_resource = {
115 .start = EK_FLASH_BASE,
116 .end = EK_FLASH_BASE + EK_FLASH_SIZE - 1,
117 .flags = IORESOURCE_MEM,
118};
119
120static struct platform_device ek_flash = {
121 .name = "physmap-flash",
122 .id = 0,
123 .dev = {
124 .platform_data = &ek_flash_data,
125 },
126 .resource = &ek_flash_resource,
127 .num_resources = 1,
128};
129
130static struct gpio_led ek_leds[] = {
131 { /* "user led 1", DS2 */
132 .name = "green",
133 .gpio = AT91_PIN_PB0,
134 .active_low = 1,
135 .default_trigger = "mmc0",
136 },
137 { /* "user led 2", DS4 */
138 .name = "yellow",
139 .gpio = AT91_PIN_PB1,
140 .active_low = 1,
141 .default_trigger = "heartbeat",
142 },
143 { /* "user led 3", DS6 */
144 .name = "red",
145 .gpio = AT91_PIN_PB2,
146 .active_low = 1,
147 }
148};
149
150static void __init ek_board_init(void)
151{
152 /* Serial */
153 /* DBGU on ttyS0. (Rx & Tx only) */
154 at91_register_uart(0, 0, 0);
155
156 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
157 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
158 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
159 | ATMEL_UART_RI);
160 at91_add_device_serial();
161 /* Ethernet */
162 at91_add_device_eth(&ek_eth_data);
163 /* USB Host */
164 at91_add_device_usbh(&ek_usbh_data);
165 /* USB Device */
166 at91_add_device_udc(&ek_udc_data);
167 at91_set_multi_drive(ek_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */
168 /* I2C */
169 at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
170 /* SPI */
171 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
172#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
173 /* DataFlash card */
174 at91_set_gpio_output(AT91_PIN_PB22, 0);
175#else
176 /* MMC */
177 at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
178 at91_add_device_mci(0, &ek_mci0_data);
179#endif
180 /* NOR Flash */
181 platform_device_register(&ek_flash);
182 /* LEDs */
183 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
184 /* VGA */
185// ek_add_device_video();
186}
187
188MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
189 /* Maintainer: SAN People/Atmel */
190 .init_time = at91rm9200_timer_init,
191 .map_io = at91_map_io,
192 .handle_irq = at91_aic_handle_irq,
193 .init_early = ek_init_early,
194 .init_irq = at91_init_irq_default,
195 .init_machine = ek_board_init,
196MACHINE_END
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
deleted file mode 100644
index 46fdb0c68a68..000000000000
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ /dev/null
@@ -1,597 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-yl-9200.c
3 *
4 * Adapted from various board files in arch/arm/mach-at91
5 *
6 * Modifications for YL-9200 platform:
7 * Copyright (C) 2007 S. Birtles
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/types.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/mm.h>
28#include <linux/module.h>
29#include <linux/dma-mapping.h>
30#include <linux/platform_device.h>
31#include <linux/spi/spi.h>
32#include <linux/spi/ads7846.h>
33#include <linux/mtd/physmap.h>
34#include <linux/gpio_keys.h>
35#include <linux/input.h>
36
37#include <asm/setup.h>
38#include <asm/mach-types.h>
39#include <asm/irq.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43#include <asm/mach/irq.h>
44
45#include <mach/hardware.h>
46#include <mach/at91rm9200_mc.h>
47#include <mach/at91_ramc.h>
48#include <mach/cpu.h>
49
50#include "at91_aic.h"
51#include "board.h"
52#include "generic.h"
53#include "gpio.h"
54
55
56static void __init yl9200_init_early(void)
57{
58 /* Set cpu type: PQFP */
59 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
60
61 /* Initialize processor: 18.432 MHz crystal */
62 at91_initialize(18432000);
63}
64
65/*
66 * LEDs
67 */
68static struct gpio_led yl9200_leds[] = {
69 { /* D2 */
70 .name = "led2",
71 .gpio = AT91_PIN_PB17,
72 .active_low = 1,
73 .default_trigger = "timer",
74 },
75 { /* D3 */
76 .name = "led3",
77 .gpio = AT91_PIN_PB16,
78 .active_low = 1,
79 .default_trigger = "heartbeat",
80 },
81 { /* D4 */
82 .name = "led4",
83 .gpio = AT91_PIN_PB15,
84 .active_low = 1,
85 },
86 { /* D5 */
87 .name = "led5",
88 .gpio = AT91_PIN_PB8,
89 .active_low = 1,
90 }
91};
92
93/*
94 * Ethernet
95 */
96static struct macb_platform_data __initdata yl9200_eth_data = {
97 .phy_irq_pin = AT91_PIN_PB28,
98 .is_rmii = 1,
99};
100
101/*
102 * USB Host
103 */
104static struct at91_usbh_data __initdata yl9200_usbh_data = {
105 .ports = 1, /* PQFP version of AT91RM9200 */
106 .vbus_pin = {-EINVAL, -EINVAL},
107 .overcurrent_pin= {-EINVAL, -EINVAL},
108};
109
110/*
111 * USB Device
112 */
113static struct at91_udc_data __initdata yl9200_udc_data = {
114 .pullup_pin = AT91_PIN_PC4,
115 .vbus_pin = AT91_PIN_PC5,
116 .pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */
117
118};
119
120/*
121 * MMC
122 */
123static struct mci_platform_data __initdata yl9200_mci0_data = {
124 .slot[0] = {
125 .bus_width = 4,
126 .detect_pin = AT91_PIN_PB9,
127 .wp_pin = -EINVAL,
128 },
129};
130
131/*
132 * NAND Flash
133 */
134static struct mtd_partition __initdata yl9200_nand_partition[] = {
135 {
136 .name = "AT91 NAND partition 1, boot",
137 .offset = 0,
138 .size = SZ_256K
139 },
140 {
141 .name = "AT91 NAND partition 2, kernel",
142 .offset = MTDPART_OFS_NXTBLK,
143 .size = (2 * SZ_1M) - SZ_256K
144 },
145 {
146 .name = "AT91 NAND partition 3, filesystem",
147 .offset = MTDPART_OFS_NXTBLK,
148 .size = 14 * SZ_1M
149 },
150 {
151 .name = "AT91 NAND partition 4, storage",
152 .offset = MTDPART_OFS_NXTBLK,
153 .size = SZ_16M
154 },
155 {
156 .name = "AT91 NAND partition 5, ext-fs",
157 .offset = MTDPART_OFS_NXTBLK,
158 .size = SZ_32M
159 }
160};
161
162static struct atmel_nand_data __initdata yl9200_nand_data = {
163 .ale = 6,
164 .cle = 7,
165 .det_pin = -EINVAL,
166 .rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
167 .enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
168 .ecc_mode = NAND_ECC_SOFT,
169 .parts = yl9200_nand_partition,
170 .num_parts = ARRAY_SIZE(yl9200_nand_partition),
171};
172
173/*
174 * NOR Flash
175 */
176#define YL9200_FLASH_BASE AT91_CHIPSELECT_0
177#define YL9200_FLASH_SIZE SZ_16M
178
179static struct mtd_partition yl9200_flash_partitions[] = {
180 {
181 .name = "Bootloader",
182 .offset = 0,
183 .size = SZ_256K,
184 .mask_flags = MTD_WRITEABLE, /* force read-only */
185 },
186 {
187 .name = "Kernel",
188 .offset = MTDPART_OFS_NXTBLK,
189 .size = (2 * SZ_1M) - SZ_256K
190 },
191 {
192 .name = "Filesystem",
193 .offset = MTDPART_OFS_NXTBLK,
194 .size = MTDPART_SIZ_FULL
195 }
196};
197
198static struct physmap_flash_data yl9200_flash_data = {
199 .width = 2,
200 .parts = yl9200_flash_partitions,
201 .nr_parts = ARRAY_SIZE(yl9200_flash_partitions),
202};
203
204static struct resource yl9200_flash_resources[] = {
205 {
206 .start = YL9200_FLASH_BASE,
207 .end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
208 .flags = IORESOURCE_MEM,
209 }
210};
211
212static struct platform_device yl9200_flash = {
213 .name = "physmap-flash",
214 .id = 0,
215 .dev = {
216 .platform_data = &yl9200_flash_data,
217 },
218 .resource = yl9200_flash_resources,
219 .num_resources = ARRAY_SIZE(yl9200_flash_resources),
220};
221
222/*
223 * I2C (TWI)
224 */
225static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
226 { /* EEPROM */
227 I2C_BOARD_INFO("24c128", 0x50),
228 }
229};
230
231/*
232 * GPIO Buttons
233*/
234#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
235static struct gpio_keys_button yl9200_buttons[] = {
236 {
237 .gpio = AT91_PIN_PA24,
238 .code = BTN_2,
239 .desc = "SW2",
240 .active_low = 1,
241 .wakeup = 1,
242 },
243 {
244 .gpio = AT91_PIN_PB1,
245 .code = BTN_3,
246 .desc = "SW3",
247 .active_low = 1,
248 .wakeup = 1,
249 },
250 {
251 .gpio = AT91_PIN_PB2,
252 .code = BTN_4,
253 .desc = "SW4",
254 .active_low = 1,
255 .wakeup = 1,
256 },
257 {
258 .gpio = AT91_PIN_PB6,
259 .code = BTN_5,
260 .desc = "SW5",
261 .active_low = 1,
262 .wakeup = 1,
263 }
264};
265
266static struct gpio_keys_platform_data yl9200_button_data = {
267 .buttons = yl9200_buttons,
268 .nbuttons = ARRAY_SIZE(yl9200_buttons),
269};
270
271static struct platform_device yl9200_button_device = {
272 .name = "gpio-keys",
273 .id = -1,
274 .num_resources = 0,
275 .dev = {
276 .platform_data = &yl9200_button_data,
277 }
278};
279
280static void __init yl9200_add_device_buttons(void)
281{
282 at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */
283 at91_set_deglitch(AT91_PIN_PA24, 1);
284 at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */
285 at91_set_deglitch(AT91_PIN_PB1, 1);
286 at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */
287 at91_set_deglitch(AT91_PIN_PB2, 1);
288 at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */
289 at91_set_deglitch(AT91_PIN_PB6, 1);
290
291 /* Enable buttons (Sheet 5) */
292 at91_set_gpio_output(AT91_PIN_PB7, 1);
293
294 platform_device_register(&yl9200_button_device);
295}
296#else
297static void __init yl9200_add_device_buttons(void) {}
298#endif
299
300/*
301 * Touchscreen
302 */
303#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
304static int ads7843_pendown_state(void)
305{
306 return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
307}
308
309static struct ads7846_platform_data ads_info = {
310 .model = 7843,
311 .x_min = 150,
312 .x_max = 3830,
313 .y_min = 190,
314 .y_max = 3830,
315 .vref_delay_usecs = 100,
316
317 /* For a 8" touch-screen */
318 // .x_plate_ohms = 603,
319 // .y_plate_ohms = 332,
320
321 /* For a 10.4" touch-screen */
322 // .x_plate_ohms = 611,
323 // .y_plate_ohms = 325,
324
325 .x_plate_ohms = 576,
326 .y_plate_ohms = 366,
327
328 .pressure_max = 15000, /* generally nonsense on the 7843 */
329 .debounce_max = 1,
330 .debounce_rep = 0,
331 .debounce_tol = (~0),
332 .get_pendown_state = ads7843_pendown_state,
333};
334
335static void __init yl9200_add_device_ts(void)
336{
337 at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
338 at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
339}
340#else
341static void __init yl9200_add_device_ts(void) {}
342#endif
343
344/*
345 * SPI devices
346 */
347static struct spi_board_info yl9200_spi_devices[] = {
348#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
349 { /* Touchscreen */
350 .modalias = "ads7846",
351 .chip_select = 0,
352 .max_speed_hz = 5000 * 26,
353 .platform_data = &ads_info,
354 .irq = AT91_PIN_PB11,
355 },
356#endif
357 { /* CAN */
358 .modalias = "mcp2510",
359 .chip_select = 1,
360 .max_speed_hz = 25000 * 26,
361 .irq = AT91_PIN_PC0,
362 }
363};
364
365/*
366 * LCD / VGA
367 *
368 * EPSON S1D13806 FB (discontinued chip)
369 * EPSON S1D13506 FB
370 */
371#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
372#include <video/s1d13xxxfb.h>
373
374
375static void yl9200_init_video(void)
376{
377 /* NWAIT Signal */
378 at91_set_A_periph(AT91_PIN_PC6, 0);
379
380 /* Initialization of the Static Memory Controller for Chip Select 2 */
381 at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
382 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
383 | AT91_SMC_TDF_(0x100) /* float time */
384 );
385}
386
387static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
388{
389 {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
390 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
391 {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
392 {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
393 {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
394 {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
395 {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
396 {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
397 {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
398 {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
399 {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
400 {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
401 {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
402 {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
403 {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
404 {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
405 {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
406 {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
407 {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
408 {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
409 {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
410 {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
411 {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
412 {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
413 {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
414 {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
415 {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
416 {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
417 {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
418 {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
419 {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
420 {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
421 {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
422 {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
423 {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
424 {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
425 {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
426 {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
427 {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
428 {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
429 {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
430 {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
431 {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
432 {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
433 {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
434 {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
435 {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
436 {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
437 {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
438 {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
439 {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
440 {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
441 {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
442 {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
443 {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
444 {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
445 {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
446 {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
447 {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
448 {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
449 {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
450 {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
451 {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
452 {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
453 {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
454 {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
455 {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
456 {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
457 {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
458 {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
459 {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
460 {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
461 {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
462 {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
463 {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
464 {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
465 {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
466 {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
467 {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
468 {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
469 {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
470 {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
471 {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
472 {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
473 {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
474 {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
475 {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
476 {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
477 {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
478 {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
479 {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
480 {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
481 {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
482 {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
483 {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
484 {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
485 {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
486 {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
487 {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
488 {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
489 {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
490 {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
491 {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
492 {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
493 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
494};
495
496static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
497 .initregs = yl9200_s1dfb_initregs,
498 .initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs),
499 .platform_init_video = yl9200_init_video,
500};
501
502#define YL9200_FB_REG_BASE AT91_CHIPSELECT_7
503#define YL9200_FB_VMEM_BASE YL9200_FB_REG_BASE + SZ_2M
504#define YL9200_FB_VMEM_SIZE SZ_2M
505
506static struct resource yl9200_s1dfb_resource[] = {
507 [0] = { /* video mem */
508 .name = "s1d13xxxfb memory",
509 .start = YL9200_FB_VMEM_BASE,
510 .end = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
511 .flags = IORESOURCE_MEM,
512 },
513 [1] = { /* video registers */
514 .name = "s1d13xxxfb registers",
515 .start = YL9200_FB_REG_BASE,
516 .end = YL9200_FB_REG_BASE + SZ_512 -1,
517 .flags = IORESOURCE_MEM,
518 },
519};
520
521static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
522
523static struct platform_device yl9200_s1dfb_device = {
524 .name = "s1d13806fb",
525 .id = -1,
526 .dev = {
527 .dma_mask = &s1dfb_dmamask,
528 .coherent_dma_mask = DMA_BIT_MASK(32),
529 .platform_data = &yl9200_s1dfb_pdata,
530 },
531 .resource = yl9200_s1dfb_resource,
532 .num_resources = ARRAY_SIZE(yl9200_s1dfb_resource),
533};
534
535void __init yl9200_add_device_video(void)
536{
537 platform_device_register(&yl9200_s1dfb_device);
538}
539#else
540void __init yl9200_add_device_video(void) {}
541#endif
542
543
544static void __init yl9200_board_init(void)
545{
546 /* Serial */
547 /* DBGU on ttyS0. (Rx & Tx only) */
548 at91_register_uart(0, 0, 0);
549
550 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
551 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
552 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
553 | ATMEL_UART_RI);
554
555 /* USART0 on ttyS2. (Rx & Tx only to JP3) */
556 at91_register_uart(AT91RM9200_ID_US0, 2, 0);
557
558 /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
559 at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
560 at91_add_device_serial();
561 /* Ethernet */
562 at91_add_device_eth(&yl9200_eth_data);
563 /* USB Host */
564 at91_add_device_usbh(&yl9200_usbh_data);
565 /* USB Device */
566 at91_add_device_udc(&yl9200_udc_data);
567 /* I2C */
568 at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
569 /* MMC */
570 at91_add_device_mci(0, &yl9200_mci0_data);
571 /* NAND */
572 at91_add_device_nand(&yl9200_nand_data);
573 /* NOR Flash */
574 platform_device_register(&yl9200_flash);
575#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
576 /* SPI */
577 at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
578 /* Touchscreen */
579 yl9200_add_device_ts();
580#endif
581 /* LEDs. */
582 at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
583 /* Push Buttons */
584 yl9200_add_device_buttons();
585 /* VGA */
586 yl9200_add_device_video();
587}
588
589MACHINE_START(YL9200, "uCdragon YL-9200")
590 /* Maintainer: S.Birtles */
591 .init_time = at91rm9200_timer_init,
592 .map_io = at91_map_io,
593 .handle_irq = at91_aic_handle_irq,
594 .init_early = yl9200_init_early,
595 .init_irq = at91_init_irq_default,
596 .init_machine = yl9200_board_init,
597MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
deleted file mode 100644
index d66f102c352a..000000000000
--- a/arch/arm/mach-at91/clock.c
+++ /dev/null
@@ -1,977 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/clock.c
3 *
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/fs.h>
17#include <linux/debugfs.h>
18#include <linux/seq_file.h>
19#include <linux/list.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <linux/spinlock.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26#include <linux/of_address.h>
27#include <linux/clk/at91_pmc.h>
28
29#include <mach/hardware.h>
30#include <mach/cpu.h>
31
32#include <asm/proc-fns.h>
33
34#include "clock.h"
35#include "generic.h"
36
37void __iomem *at91_pmc_base;
38EXPORT_SYMBOL_GPL(at91_pmc_base);
39
40/*
41 * There's a lot more which can be done with clocks, including cpufreq
42 * integration, slow clock mode support (for system suspend), letting
43 * PLLB be used at other rates (on boards that don't need USB), etc.
44 */
45
46#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
47#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
48#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
49#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
50
51
52/*
53 * Chips have some kind of clocks : group them by functionality
54 */
55#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
56 || cpu_is_at91sam9g45() \
57 || cpu_is_at91sam9x5() \
58 || cpu_is_sama5d3())
59
60#define cpu_has_1056M_plla() (cpu_is_sama5d3())
61
62#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
63 || cpu_is_at91sam9g45() \
64 || cpu_is_at91sam9x5() \
65 || cpu_is_at91sam9n12())
66
67#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
68
69#define cpu_has_240M_plla() (cpu_is_at91sam9261() \
70 || cpu_is_at91sam9263() \
71 || cpu_is_at91sam9rl())
72
73#define cpu_has_210M_plla() (cpu_is_at91sam9260())
74
75#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
76 || cpu_is_at91sam9g45() \
77 || cpu_is_at91sam9x5() \
78 || cpu_is_sama5d3()))
79
80#define cpu_has_upll() (cpu_is_at91sam9g45() \
81 || cpu_is_at91sam9x5() \
82 || cpu_is_sama5d3())
83
84/* USB host HS & FS */
85#define cpu_has_uhp() (!cpu_is_at91sam9rl())
86
87/* USB device FS only */
88#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
89 || cpu_is_at91sam9g45() \
90 || cpu_is_at91sam9x5() \
91 || cpu_is_sama5d3()))
92
93#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
94 || cpu_is_at91sam9x5() \
95 || cpu_is_at91sam9n12() \
96 || cpu_is_sama5d3())
97
98#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
99 || cpu_is_at91sam9x5() \
100 || cpu_is_at91sam9n12() \
101 || cpu_is_sama5d3())
102
103#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
104 || cpu_is_at91sam9n12() \
105 || cpu_is_sama5d3())
106
107static LIST_HEAD(clocks);
108static DEFINE_SPINLOCK(clk_lock);
109
110static u32 at91_pllb_usb_init;
111
112/*
113 * Four primary clock sources: two crystal oscillators (32K, main), and
114 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
115 * 48 MHz (unless no USB function clocks are needed). The main clock and
116 * both PLLs are turned off to run in "slow clock mode" (system suspend).
117 */
118static struct clk clk32k = {
119 .name = "clk32k",
120 .rate_hz = AT91_SLOW_CLOCK,
121 .users = 1, /* always on */
122 .id = 0,
123 .type = CLK_TYPE_PRIMARY,
124};
125static struct clk main_clk = {
126 .name = "main",
127 .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
128 .id = 1,
129 .type = CLK_TYPE_PRIMARY,
130};
131static struct clk plla = {
132 .name = "plla",
133 .parent = &main_clk,
134 .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
135 .id = 2,
136 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
137};
138
139static void pllb_mode(struct clk *clk, int is_on)
140{
141 u32 value;
142
143 if (is_on) {
144 is_on = AT91_PMC_LOCKB;
145 value = at91_pllb_usb_init;
146 } else
147 value = 0;
148
149 // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
150 at91_pmc_write(AT91_CKGR_PLLBR, value);
151
152 do {
153 cpu_relax();
154 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
155}
156
157static struct clk pllb = {
158 .name = "pllb",
159 .parent = &main_clk,
160 .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
161 .mode = pllb_mode,
162 .id = 3,
163 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
164};
165
166static void pmc_sys_mode(struct clk *clk, int is_on)
167{
168 if (is_on)
169 at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
170 else
171 at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
172}
173
174static void pmc_uckr_mode(struct clk *clk, int is_on)
175{
176 unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
177
178 if (is_on) {
179 is_on = AT91_PMC_LOCKU;
180 at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
181 } else
182 at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
183
184 do {
185 cpu_relax();
186 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
187}
188
189/* USB function clocks (PLLB must be 48 MHz) */
190static struct clk udpck = {
191 .name = "udpck",
192 .parent = &pllb,
193 .mode = pmc_sys_mode,
194};
195struct clk utmi_clk = {
196 .name = "utmi_clk",
197 .parent = &main_clk,
198 .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
199 .mode = pmc_uckr_mode,
200 .type = CLK_TYPE_PLL,
201};
202static struct clk uhpck = {
203 .name = "uhpck",
204 /*.parent = ... we choose parent at runtime */
205 .mode = pmc_sys_mode,
206};
207
208
209/*
210 * The master clock is divided from the CPU clock (by 1-4). It's used for
211 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
212 * (e.g baud rate generation). It's sourced from one of the primary clocks.
213 */
214struct clk mck = {
215 .name = "mck",
216 .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
217};
218
219static void pmc_periph_mode(struct clk *clk, int is_on)
220{
221 u32 regval = 0;
222
223 /*
224 * With sama5d3 devices, we are managing clock division so we have to
225 * use the Peripheral Control Register introduced from at91sam9x5
226 * devices.
227 */
228 if (cpu_is_sama5d3()) {
229 regval |= AT91_PMC_PCR_CMD; /* write command */
230 regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
231 regval |= AT91_PMC_PCR_DIV(clk->div);
232 if (is_on)
233 regval |= AT91_PMC_PCR_EN; /* enable clock */
234 at91_pmc_write(AT91_PMC_PCR, regval);
235 } else {
236 if (is_on)
237 at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
238 else
239 at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
240 }
241}
242
243static struct clk __init *at91_css_to_clk(unsigned long css)
244{
245 switch (css) {
246 case AT91_PMC_CSS_SLOW:
247 return &clk32k;
248 case AT91_PMC_CSS_MAIN:
249 return &main_clk;
250 case AT91_PMC_CSS_PLLA:
251 return &plla;
252 case AT91_PMC_CSS_PLLB:
253 if (cpu_has_upll())
254 /* CSS_PLLB == CSS_UPLL */
255 return &utmi_clk;
256 else if (cpu_has_pllb())
257 return &pllb;
258 break;
259 /* alternate PMC: can use master clock */
260 case AT91_PMC_CSS_MASTER:
261 return &mck;
262 }
263
264 return NULL;
265}
266
267static int pmc_prescaler_divider(u32 reg)
268{
269 if (cpu_has_alt_prescaler()) {
270 return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
271 } else {
272 return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
273 }
274}
275
276static void __clk_enable(struct clk *clk)
277{
278 if (clk->parent)
279 __clk_enable(clk->parent);
280 if (clk->users++ == 0 && clk->mode)
281 clk->mode(clk, 1);
282}
283
284int clk_enable(struct clk *clk)
285{
286 unsigned long flags;
287
288 spin_lock_irqsave(&clk_lock, flags);
289 __clk_enable(clk);
290 spin_unlock_irqrestore(&clk_lock, flags);
291 return 0;
292}
293EXPORT_SYMBOL(clk_enable);
294
295static void __clk_disable(struct clk *clk)
296{
297 BUG_ON(clk->users == 0);
298 if (--clk->users == 0 && clk->mode)
299 clk->mode(clk, 0);
300 if (clk->parent)
301 __clk_disable(clk->parent);
302}
303
304void clk_disable(struct clk *clk)
305{
306 unsigned long flags;
307
308 spin_lock_irqsave(&clk_lock, flags);
309 __clk_disable(clk);
310 spin_unlock_irqrestore(&clk_lock, flags);
311}
312EXPORT_SYMBOL(clk_disable);
313
314unsigned long clk_get_rate(struct clk *clk)
315{
316 unsigned long flags;
317 unsigned long rate;
318
319 spin_lock_irqsave(&clk_lock, flags);
320 for (;;) {
321 rate = clk->rate_hz;
322 if (rate || !clk->parent)
323 break;
324 clk = clk->parent;
325 }
326 spin_unlock_irqrestore(&clk_lock, flags);
327 return rate;
328}
329EXPORT_SYMBOL(clk_get_rate);
330
331/*------------------------------------------------------------------------*/
332
333/*
334 * For now, only the programmable clocks support reparenting (MCK could
335 * do this too, with care) or rate changing (the PLLs could do this too,
336 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
337 * a better rate match; we don't.
338 */
339
340long clk_round_rate(struct clk *clk, unsigned long rate)
341{
342 unsigned long flags;
343 unsigned prescale;
344 unsigned long actual;
345 unsigned long prev = ULONG_MAX;
346
347 if (!clk_is_programmable(clk))
348 return -EINVAL;
349 spin_lock_irqsave(&clk_lock, flags);
350
351 actual = clk->parent->rate_hz;
352 for (prescale = 0; prescale < 7; prescale++) {
353 if (actual > rate)
354 prev = actual;
355
356 if (actual && actual <= rate) {
357 if ((prev - rate) < (rate - actual)) {
358 actual = prev;
359 prescale--;
360 }
361 break;
362 }
363 actual >>= 1;
364 }
365
366 spin_unlock_irqrestore(&clk_lock, flags);
367 return (prescale < 7) ? actual : -ENOENT;
368}
369EXPORT_SYMBOL(clk_round_rate);
370
371int clk_set_rate(struct clk *clk, unsigned long rate)
372{
373 unsigned long flags;
374 unsigned prescale;
375 unsigned long prescale_offset, css_mask;
376 unsigned long actual;
377
378 if (!clk_is_programmable(clk))
379 return -EINVAL;
380 if (clk->users)
381 return -EBUSY;
382
383 if (cpu_has_alt_prescaler()) {
384 prescale_offset = PMC_ALT_PRES_OFFSET;
385 css_mask = AT91_PMC_ALT_PCKR_CSS;
386 } else {
387 prescale_offset = PMC_PRES_OFFSET;
388 css_mask = AT91_PMC_CSS;
389 }
390
391 spin_lock_irqsave(&clk_lock, flags);
392
393 actual = clk->parent->rate_hz;
394 for (prescale = 0; prescale < 7; prescale++) {
395 if (actual && actual <= rate) {
396 u32 pckr;
397
398 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
399 pckr &= css_mask; /* keep clock selection */
400 pckr |= prescale << prescale_offset;
401 at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
402 clk->rate_hz = actual;
403 break;
404 }
405 actual >>= 1;
406 }
407
408 spin_unlock_irqrestore(&clk_lock, flags);
409 return (prescale < 7) ? actual : -ENOENT;
410}
411EXPORT_SYMBOL(clk_set_rate);
412
413struct clk *clk_get_parent(struct clk *clk)
414{
415 return clk->parent;
416}
417EXPORT_SYMBOL(clk_get_parent);
418
419int clk_set_parent(struct clk *clk, struct clk *parent)
420{
421 unsigned long flags;
422
423 if (clk->users)
424 return -EBUSY;
425 if (!clk_is_primary(parent) || !clk_is_programmable(clk))
426 return -EINVAL;
427
428 if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
429 return -EINVAL;
430
431 spin_lock_irqsave(&clk_lock, flags);
432
433 clk->rate_hz = parent->rate_hz;
434 clk->parent = parent;
435 at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
436
437 spin_unlock_irqrestore(&clk_lock, flags);
438 return 0;
439}
440EXPORT_SYMBOL(clk_set_parent);
441
442/* establish PCK0..PCKN parentage and rate */
443static void __init init_programmable_clock(struct clk *clk)
444{
445 struct clk *parent;
446 u32 pckr;
447 unsigned int css_mask;
448
449 if (cpu_has_alt_prescaler())
450 css_mask = AT91_PMC_ALT_PCKR_CSS;
451 else
452 css_mask = AT91_PMC_CSS;
453
454 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
455 parent = at91_css_to_clk(pckr & css_mask);
456 clk->parent = parent;
457 clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
458}
459
460/*------------------------------------------------------------------------*/
461
462#ifdef CONFIG_DEBUG_FS
463
464static int at91_clk_show(struct seq_file *s, void *unused)
465{
466 u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
467 struct clk *clk;
468
469 scsr = at91_pmc_read(AT91_PMC_SCSR);
470 pcsr = at91_pmc_read(AT91_PMC_PCSR);
471 if (cpu_is_sama5d3())
472 pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
473 sr = at91_pmc_read(AT91_PMC_SR);
474 seq_printf(s, "SCSR = %8x\n", scsr);
475 seq_printf(s, "PCSR = %8x\n", pcsr);
476 if (cpu_is_sama5d3())
477 seq_printf(s, "PCSR1 = %8x\n", pcsr1);
478 seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
479 seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
480 seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
481 if (cpu_has_pllb())
482 seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
483 if (cpu_has_utmi()) {
484 uckr = at91_pmc_read(AT91_CKGR_UCKR);
485 seq_printf(s, "UCKR = %8x\n", uckr);
486 }
487 seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
488 if (cpu_has_upll() || cpu_is_at91sam9n12())
489 seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
490 seq_printf(s, "SR = %8x\n", sr);
491
492 seq_printf(s, "\n");
493
494 list_for_each_entry(clk, &clocks, node) {
495 char *state;
496
497 if (clk->mode == pmc_sys_mode) {
498 state = (scsr & clk->pmc_mask) ? "on" : "off";
499 } else if (clk->mode == pmc_periph_mode) {
500 if (cpu_is_sama5d3()) {
501 u32 pmc_mask = 1 << (clk->pid % 32);
502
503 if (clk->pid > 31)
504 state = (pcsr1 & pmc_mask) ? "on" : "off";
505 else
506 state = (pcsr & pmc_mask) ? "on" : "off";
507 } else {
508 state = (pcsr & clk->pmc_mask) ? "on" : "off";
509 }
510 } else if (clk->mode == pmc_uckr_mode) {
511 state = (uckr & clk->pmc_mask) ? "on" : "off";
512 } else if (clk->pmc_mask) {
513 state = (sr & clk->pmc_mask) ? "on" : "off";
514 } else if (clk == &clk32k || clk == &main_clk) {
515 state = "on";
516 } else {
517 state = "";
518 }
519
520 seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
521 clk->name, clk->users, state, clk_get_rate(clk),
522 clk->parent ? clk->parent->name : "");
523 }
524 return 0;
525}
526
527static int at91_clk_open(struct inode *inode, struct file *file)
528{
529 return single_open(file, at91_clk_show, NULL);
530}
531
532static const struct file_operations at91_clk_operations = {
533 .open = at91_clk_open,
534 .read = seq_read,
535 .llseek = seq_lseek,
536 .release = single_release,
537};
538
539static int __init at91_clk_debugfs_init(void)
540{
541 /* /sys/kernel/debug/at91_clk */
542 (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
543
544 return 0;
545}
546postcore_initcall(at91_clk_debugfs_init);
547
548#endif
549
550/*------------------------------------------------------------------------*/
551
552/* Register a new clock */
553static void __init at91_clk_add(struct clk *clk)
554{
555 list_add_tail(&clk->node, &clocks);
556
557 clk->cl.con_id = clk->name;
558 clk->cl.clk = clk;
559 clkdev_add(&clk->cl);
560}
561
562int __init clk_register(struct clk *clk)
563{
564 if (clk_is_peripheral(clk)) {
565 if (!clk->parent)
566 clk->parent = &mck;
567 if (cpu_is_sama5d3())
568 clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
569 1 << clk->div);
570 clk->mode = pmc_periph_mode;
571 }
572 else if (clk_is_sys(clk)) {
573 clk->parent = &mck;
574 clk->mode = pmc_sys_mode;
575 }
576 else if (clk_is_programmable(clk)) {
577 clk->mode = pmc_sys_mode;
578 init_programmable_clock(clk);
579 }
580
581 at91_clk_add(clk);
582
583 return 0;
584}
585
586/*------------------------------------------------------------------------*/
587
588static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
589{
590 unsigned mul, div;
591
592 div = reg & 0xff;
593 if (cpu_is_sama5d3())
594 mul = AT91_PMC3_MUL_GET(reg);
595 else
596 mul = AT91_PMC_MUL_GET(reg);
597
598 if (div && mul) {
599 freq /= div;
600 freq *= mul + 1;
601 } else
602 freq = 0;
603
604 return freq;
605}
606
607static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
608{
609 if (pll == &pllb && (reg & AT91_PMC_USB96M))
610 return freq / 2;
611 else if (pll == &utmi_clk || cpu_is_at91sam9n12())
612 return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
613 else
614 return freq;
615}
616
617static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
618{
619 unsigned i, div = 0, mul = 0, diff = 1 << 30;
620 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
621
622 /* PLL output max 240 MHz (or 180 MHz per errata) */
623 if (out_freq > 240000000)
624 goto fail;
625
626 for (i = 1; i < 256; i++) {
627 int diff1;
628 unsigned input, mul1;
629
630 /*
631 * PLL input between 1MHz and 32MHz per spec, but lower
632 * frequences seem necessary in some cases so allow 100K.
633 * Warning: some newer products need 2MHz min.
634 */
635 input = main_freq / i;
636 if (cpu_is_at91sam9g20() && input < 2000000)
637 continue;
638 if (input < 100000)
639 continue;
640 if (input > 32000000)
641 continue;
642
643 mul1 = out_freq / input;
644 if (cpu_is_at91sam9g20() && mul > 63)
645 continue;
646 if (mul1 > 2048)
647 continue;
648 if (mul1 < 2)
649 goto fail;
650
651 diff1 = out_freq - input * mul1;
652 if (diff1 < 0)
653 diff1 = -diff1;
654 if (diff > diff1) {
655 diff = diff1;
656 div = i;
657 mul = mul1;
658 if (diff == 0)
659 break;
660 }
661 }
662 if (i == 256 && diff > (out_freq >> 5))
663 goto fail;
664 return ret | ((mul - 1) << 16) | div;
665fail:
666 return 0;
667}
668
669static struct clk *const standard_pmc_clocks[] __initconst = {
670 /* four primary clocks */
671 &clk32k,
672 &main_clk,
673 &plla,
674
675 /* MCK */
676 &mck
677};
678
679/* PLLB generated USB full speed clock init */
680static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
681{
682 unsigned int reg;
683
684 /*
685 * USB clock init: choose 48 MHz PLLB value,
686 * disable 48MHz clock during usb peripheral suspend.
687 *
688 * REVISIT: assumes MCK doesn't derive from PLLB!
689 */
690 uhpck.parent = &pllb;
691
692 reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
693 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
694 if (cpu_is_at91rm9200()) {
695 reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
696 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
697 udpck.pmc_mask = AT91RM9200_PMC_UDP;
698 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
699 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
700 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
701 cpu_is_at91sam9g10()) {
702 reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
703 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
704 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
705 } else if (cpu_is_at91sam9n12()) {
706 /* Divider for USB clock is in USB clock register for 9n12 */
707 reg = AT91_PMC_USBS_PLLB;
708
709 /* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
710 reg |= AT91_PMC_OHCIUSBDIV_2;
711 at91_pmc_write(AT91_PMC_USB, reg);
712
713 /* Still setup masks */
714 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
715 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
716 }
717 at91_pmc_write(AT91_CKGR_PLLBR, 0);
718
719 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
720 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
721}
722
723/* UPLL generated USB full speed clock init */
724static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
725{
726 /*
727 * USB clock init: choose 480 MHz from UPLL,
728 */
729 unsigned int usbr = AT91_PMC_USBS_UPLL;
730
731 /* Setup divider by 10 to reach 48 MHz */
732 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
733
734 at91_pmc_write(AT91_PMC_USB, usbr);
735
736 /* Now set uhpck values */
737 uhpck.parent = &utmi_clk;
738 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
739 uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
740}
741
742static int __init at91_pmc_init(unsigned long main_clock)
743{
744 unsigned tmp, freq, mckr;
745 int i;
746 int pll_overclock = false;
747
748 /*
749 * When the bootloader initialized the main oscillator correctly,
750 * there's no problem using the cycle counter. But if it didn't,
751 * or when using oscillator bypass mode, we must be told the speed
752 * of the main clock.
753 */
754 if (!main_clock) {
755 do {
756 tmp = at91_pmc_read(AT91_CKGR_MCFR);
757 } while (!(tmp & AT91_PMC_MAINRDY));
758 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
759 }
760 main_clk.rate_hz = main_clock;
761
762 /* report if PLLA is more than mildly overclocked */
763 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
764 if (cpu_has_1056M_plla()) {
765 if (plla.rate_hz > 1056000000)
766 pll_overclock = true;
767 } else if (cpu_has_800M_plla()) {
768 if (plla.rate_hz > 800000000)
769 pll_overclock = true;
770 } else if (cpu_has_300M_plla()) {
771 if (plla.rate_hz > 300000000)
772 pll_overclock = true;
773 } else if (cpu_has_240M_plla()) {
774 if (plla.rate_hz > 240000000)
775 pll_overclock = true;
776 } else if (cpu_has_210M_plla()) {
777 if (plla.rate_hz > 210000000)
778 pll_overclock = true;
779 } else {
780 if (plla.rate_hz > 209000000)
781 pll_overclock = true;
782 }
783 if (pll_overclock)
784 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
785
786 if (cpu_has_plladiv2()) {
787 mckr = at91_pmc_read(AT91_PMC_MCKR);
788 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
789 }
790
791 if (!cpu_has_pllb() && cpu_has_upll()) {
792 /* setup UTMI clock as the fourth primary clock
793 * (instead of pllb) */
794 utmi_clk.type |= CLK_TYPE_PRIMARY;
795 utmi_clk.id = 3;
796 }
797
798
799 /*
800 * USB HS clock init
801 */
802 if (cpu_has_utmi()) {
803 /*
804 * multiplier is hard-wired to 40
805 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
806 */
807 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
808
809 /* UTMI bias and PLL are managed at the same time */
810 if (cpu_has_upll())
811 utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
812 }
813
814 /*
815 * USB FS clock init
816 */
817 if (cpu_has_pllb())
818 at91_pllb_usbfs_clock_init(main_clock);
819 if (cpu_has_upll())
820 /* assumes that we choose UPLL for USB and not PLLA */
821 at91_upll_usbfs_clock_init(main_clock);
822
823 /*
824 * MCK and CPU derive from one of those primary clocks.
825 * For now, assume this parentage won't change.
826 */
827 mckr = at91_pmc_read(AT91_PMC_MCKR);
828 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
829 freq = mck.parent->rate_hz;
830 freq /= pmc_prescaler_divider(mckr); /* prescale */
831 if (cpu_is_at91rm9200()) {
832 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
833 } else if (cpu_is_at91sam9g20()) {
834 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
835 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
836 if (mckr & AT91_PMC_PDIV)
837 freq /= 2; /* processor clock division */
838 } else if (cpu_has_mdiv3()) {
839 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
840 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
841 } else {
842 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
843 }
844
845 if (cpu_has_alt_prescaler()) {
846 /* Programmable clocks can use MCK */
847 mck.type |= CLK_TYPE_PRIMARY;
848 mck.id = 4;
849 }
850
851 /* Register the PMC's standard clocks */
852 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
853 at91_clk_add(standard_pmc_clocks[i]);
854
855 if (cpu_has_pllb())
856 at91_clk_add(&pllb);
857
858 if (cpu_has_uhp())
859 at91_clk_add(&uhpck);
860
861 if (cpu_has_udpfs())
862 at91_clk_add(&udpck);
863
864 if (cpu_has_utmi())
865 at91_clk_add(&utmi_clk);
866
867 /* MCK and CPU clock are "always on" */
868 clk_enable(&mck);
869
870 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
871 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
872 (unsigned) main_clock / 1000000,
873 ((unsigned) main_clock % 1000000) / 1000);
874
875 return 0;
876}
877
878#if defined(CONFIG_OF)
879static struct of_device_id pmc_ids[] = {
880 { .compatible = "atmel,at91rm9200-pmc" },
881 { .compatible = "atmel,at91sam9260-pmc" },
882 { .compatible = "atmel,at91sam9g45-pmc" },
883 { .compatible = "atmel,at91sam9n12-pmc" },
884 { .compatible = "atmel,at91sam9x5-pmc" },
885 { .compatible = "atmel,sama5d3-pmc" },
886 { /*sentinel*/ }
887};
888
889static struct of_device_id osc_ids[] = {
890 { .compatible = "atmel,osc" },
891 { /*sentinel*/ }
892};
893
894int __init at91_dt_clock_init(void)
895{
896 struct device_node *np;
897 u32 main_clock = 0;
898
899 np = of_find_matching_node(NULL, pmc_ids);
900 if (!np)
901 panic("unable to find compatible pmc node in dtb\n");
902
903 at91_pmc_base = of_iomap(np, 0);
904 if (!at91_pmc_base)
905 panic("unable to map pmc cpu registers\n");
906
907 of_node_put(np);
908
909 /* retrieve the freqency of fixed clocks from device tree */
910 np = of_find_matching_node(NULL, osc_ids);
911 if (np) {
912 u32 rate;
913 if (!of_property_read_u32(np, "clock-frequency", &rate))
914 main_clock = rate;
915 }
916
917 of_node_put(np);
918
919 return at91_pmc_init(main_clock);
920}
921#endif
922
923int __init at91_clock_init(unsigned long main_clock)
924{
925 at91_pmc_base = ioremap(AT91_PMC, 256);
926 if (!at91_pmc_base)
927 panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
928
929 return at91_pmc_init(main_clock);
930}
931
932/*
933 * Several unused clocks may be active. Turn them off.
934 */
935static int __init at91_clock_reset(void)
936{
937 unsigned long pcdr = 0;
938 unsigned long pcdr1 = 0;
939 unsigned long scdr = 0;
940 struct clk *clk;
941
942 list_for_each_entry(clk, &clocks, node) {
943 if (clk->users > 0)
944 continue;
945
946 if (clk->mode == pmc_periph_mode) {
947 if (cpu_is_sama5d3()) {
948 u32 pmc_mask = 1 << (clk->pid % 32);
949
950 if (clk->pid > 31)
951 pcdr1 |= pmc_mask;
952 else
953 pcdr |= pmc_mask;
954 } else
955 pcdr |= clk->pmc_mask;
956 }
957
958 if (clk->mode == pmc_sys_mode)
959 scdr |= clk->pmc_mask;
960
961 pr_debug("Clocks: disable unused %s\n", clk->name);
962 }
963
964 at91_pmc_write(AT91_PMC_SCDR, scdr);
965 at91_pmc_write(AT91_PMC_PCDR, pcdr);
966 if (cpu_is_sama5d3())
967 at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
968
969 return 0;
970}
971late_initcall(at91_clock_reset);
972
973void at91sam9_idle(void)
974{
975 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
976 cpu_do_idle();
977}
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
deleted file mode 100644
index a98a39bbd883..000000000000
--- a/arch/arm/mach-at91/clock.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/clock.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clkdev.h>
10
11#define CLK_TYPE_PRIMARY 0x1
12#define CLK_TYPE_PLL 0x2
13#define CLK_TYPE_PROGRAMMABLE 0x4
14#define CLK_TYPE_PERIPHERAL 0x8
15#define CLK_TYPE_SYSTEM 0x10
16
17
18struct clk {
19 struct list_head node;
20 const char *name; /* unique clock name */
21 struct clk_lookup cl;
22 unsigned long rate_hz;
23 unsigned div; /* parent clock divider */
24 struct clk *parent;
25 unsigned pid; /* peripheral ID */
26 u32 pmc_mask;
27 void (*mode)(struct clk *, int);
28 unsigned id:3; /* PCK0..4, or 32k/main/a/b */
29 unsigned type; /* clock type */
30 u16 users;
31};
32
33
34extern int __init clk_register(struct clk *clk);
35extern struct clk mck;
36extern struct clk utmi_clk;
37
38#define CLKDEV_CON_ID(_id, _clk) \
39 { \
40 .con_id = _id, \
41 .clk = _clk, \
42 }
43
44#define CLKDEV_CON_DEV_ID(_con_id, _dev_id, _clk) \
45 { \
46 .con_id = _con_id, \
47 .dev_id = _dev_id, \
48 .clk = _clk, \
49 }
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 464b08e9830a..eb81940f9848 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -11,7 +11,6 @@
11#ifndef _AT91_GENERIC_H 11#ifndef _AT91_GENERIC_H
12#define _AT91_GENERIC_H 12#define _AT91_GENERIC_H
13 13
14#include <linux/clkdev.h>
15#include <linux/of.h> 14#include <linux/of.h>
16#include <linux/reboot.h> 15#include <linux/reboot.h>
17 16
@@ -30,12 +29,6 @@ extern void __init at91_dt_initialize(void);
30 /* Interrupts */ 29 /* Interrupts */
31extern void __init at91_init_irq_default(void); 30extern void __init at91_init_irq_default(void);
32extern void __init at91_init_interrupts(unsigned int priority[]); 31extern void __init at91_init_interrupts(unsigned int priority[]);
33extern void __init at91_aic_init(unsigned int priority[],
34 unsigned int ext_irq_mask);
35extern int __init at91_aic_of_init(struct device_node *node,
36 struct device_node *parent);
37extern int __init at91_aic5_of_init(struct device_node *node,
38 struct device_node *parent);
39extern void __init at91_sysirq_mask_rtc(u32 rtc_base); 32extern void __init at91_sysirq_mask_rtc(u32 rtc_base);
40extern void __init at91_sysirq_mask_rtt(u32 rtt_base); 33extern void __init at91_sysirq_mask_rtt(u32 rtt_base);
41 34
@@ -49,16 +42,6 @@ extern void at91rm9200_timer_init(void);
49extern void at91sam926x_ioremap_pit(u32 addr); 42extern void at91sam926x_ioremap_pit(u32 addr);
50extern void at91sam926x_pit_init(int irq); 43extern void at91sam926x_pit_init(int irq);
51 44
52 /* Clocks */
53#ifdef CONFIG_OLD_CLK_AT91
54extern int __init at91_clock_init(unsigned long main_clock);
55extern int __init at91_dt_clock_init(void);
56#else
57static int inline at91_clock_init(unsigned long main_clock) { return 0; }
58static int inline at91_dt_clock_init(void) { return 0; }
59#endif
60struct device;
61
62 /* Power Management */ 45 /* Power Management */
63extern void at91_irq_suspend(void); 46extern void at91_irq_suspend(void);
64extern void at91_irq_resume(void); 47extern void at91_irq_resume(void);
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
deleted file mode 100644
index cdb3ec9efd2b..000000000000
--- a/arch/arm/mach-at91/irq.c
+++ /dev/null
@@ -1,296 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/irq.c
3 *
4 * Copyright (C) 2004 SAN People
5 * Copyright (C) 2004 ATMEL
6 * Copyright (C) Rick Bronson
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/mm.h>
26#include <linux/bitmap.h>
27#include <linux/types.h>
28#include <linux/irq.h>
29#include <linux/of.h>
30#include <linux/of_address.h>
31#include <linux/of_irq.h>
32#include <linux/irqdomain.h>
33#include <linux/err.h>
34#include <linux/slab.h>
35
36#include <mach/hardware.h>
37#include <asm/irq.h>
38#include <asm/setup.h>
39
40#include <asm/exception.h>
41#include <asm/mach/arch.h>
42#include <asm/mach/irq.h>
43#include <asm/mach/map.h>
44
45#include "at91_aic.h"
46
47void __iomem *at91_aic_base;
48static struct irq_domain *at91_aic_domain;
49static struct device_node *at91_aic_np;
50static unsigned int n_irqs = NR_AIC_IRQS;
51
52#ifdef CONFIG_PM
53
54static unsigned long *wakeups;
55static unsigned long *backups;
56
57#define set_backup(bit) set_bit(bit, backups)
58#define clear_backup(bit) clear_bit(bit, backups)
59
60static int at91_aic_pm_init(void)
61{
62 backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
63 if (!backups)
64 return -ENOMEM;
65
66 wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
67 if (!wakeups) {
68 kfree(backups);
69 return -ENOMEM;
70 }
71
72 return 0;
73}
74
75static int at91_aic_set_wake(struct irq_data *d, unsigned value)
76{
77 if (unlikely(d->hwirq >= n_irqs))
78 return -EINVAL;
79
80 if (value)
81 set_bit(d->hwirq, wakeups);
82 else
83 clear_bit(d->hwirq, wakeups);
84
85 return 0;
86}
87
88void at91_irq_suspend(void)
89{
90 at91_aic_write(AT91_AIC_IDCR, *backups);
91 at91_aic_write(AT91_AIC_IECR, *wakeups);
92}
93
94void at91_irq_resume(void)
95{
96 at91_aic_write(AT91_AIC_IDCR, *wakeups);
97 at91_aic_write(AT91_AIC_IECR, *backups);
98}
99
100#else
101static inline int at91_aic_pm_init(void)
102{
103 return 0;
104}
105
106#define set_backup(bit)
107#define clear_backup(bit)
108#define at91_aic_set_wake NULL
109
110#endif /* CONFIG_PM */
111
112asmlinkage void __exception_irq_entry
113at91_aic_handle_irq(struct pt_regs *regs)
114{
115 u32 irqnr;
116 u32 irqstat;
117
118 irqnr = at91_aic_read(AT91_AIC_IVR);
119 irqstat = at91_aic_read(AT91_AIC_ISR);
120
121 /*
122 * ISR value is 0 when there is no current interrupt or when there is
123 * a spurious interrupt
124 */
125 if (!irqstat)
126 at91_aic_write(AT91_AIC_EOICR, 0);
127 else
128 handle_IRQ(irqnr, regs);
129}
130
131static void at91_aic_mask_irq(struct irq_data *d)
132{
133 /* Disable interrupt on AIC */
134 at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
135 /* Update ISR cache */
136 clear_backup(d->hwirq);
137}
138
139static void at91_aic_unmask_irq(struct irq_data *d)
140{
141 /* Enable interrupt on AIC */
142 at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
143 /* Update ISR cache */
144 set_backup(d->hwirq);
145}
146
147static void at91_aic_eoi(struct irq_data *d)
148{
149 /*
150 * Mark end-of-interrupt on AIC, the controller doesn't care about
151 * the value written. Moreover it's a write-only register.
152 */
153 at91_aic_write(AT91_AIC_EOICR, 0);
154}
155
156static unsigned long *at91_extern_irq;
157
158u32 at91_get_extern_irq(void)
159{
160 if (!at91_extern_irq)
161 return 0;
162 return *at91_extern_irq;
163}
164
165#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
166
167static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
168{
169 int srctype;
170
171 switch (type) {
172 case IRQ_TYPE_LEVEL_HIGH:
173 srctype = AT91_AIC_SRCTYPE_HIGH;
174 break;
175 case IRQ_TYPE_EDGE_RISING:
176 srctype = AT91_AIC_SRCTYPE_RISING;
177 break;
178 case IRQ_TYPE_LEVEL_LOW:
179 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
180 srctype = AT91_AIC_SRCTYPE_LOW;
181 else
182 srctype = -EINVAL;
183 break;
184 case IRQ_TYPE_EDGE_FALLING:
185 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
186 srctype = AT91_AIC_SRCTYPE_FALLING;
187 else
188 srctype = -EINVAL;
189 break;
190 default:
191 srctype = -EINVAL;
192 }
193
194 return srctype;
195}
196
197static int at91_aic_set_type(struct irq_data *d, unsigned type)
198{
199 unsigned int smr;
200 int srctype;
201
202 srctype = at91_aic_compute_srctype(d, type);
203 if (srctype < 0)
204 return srctype;
205
206 smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
207 at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
208
209 return 0;
210}
211
212static struct irq_chip at91_aic_chip = {
213 .name = "AIC",
214 .irq_mask = at91_aic_mask_irq,
215 .irq_unmask = at91_aic_unmask_irq,
216 .irq_set_type = at91_aic_set_type,
217 .irq_set_wake = at91_aic_set_wake,
218 .irq_eoi = at91_aic_eoi,
219};
220
221static void __init at91_aic_hw_init(unsigned int spu_vector)
222{
223 int i;
224
225 /*
226 * Perform 8 End Of Interrupt Command to make sure AIC
227 * will not Lock out nIRQ
228 */
229 for (i = 0; i < 8; i++)
230 at91_aic_write(AT91_AIC_EOICR, 0);
231
232 /*
233 * Spurious Interrupt ID in Spurious Vector Register.
234 * When there is no current interrupt, the IRQ Vector Register
235 * reads the value stored in AIC_SPU
236 */
237 at91_aic_write(AT91_AIC_SPU, spu_vector);
238
239 /* No debugging in AIC: Debug (Protect) Control Register */
240 at91_aic_write(AT91_AIC_DCR, 0);
241
242 /* Disable and clear all interrupts initially */
243 at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
244 at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
245}
246
247/*
248 * Initialize the AIC interrupt controller.
249 */
250void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
251{
252 unsigned int i;
253 int irq_base;
254
255 at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
256 * sizeof(*at91_extern_irq), GFP_KERNEL);
257
258 if (at91_aic_pm_init() || at91_extern_irq == NULL)
259 panic("Unable to allocate bit maps\n");
260
261 *at91_extern_irq = ext_irq_mask;
262
263 at91_aic_base = ioremap(AT91_AIC, 512);
264 if (!at91_aic_base)
265 panic("Unable to ioremap AIC registers\n");
266
267 /* Add irq domain for AIC */
268 irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
269 if (irq_base < 0) {
270 WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
271 irq_base = 0;
272 }
273 at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
274 irq_base, 0,
275 &irq_domain_simple_ops, NULL);
276
277 if (!at91_aic_domain)
278 panic("Unable to add AIC irq domain\n");
279
280 irq_set_default_host(at91_aic_domain);
281
282 /*
283 * The IVR is used by macro get_irqnr_and_base to read and verify.
284 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
285 */
286 for (i = 0; i < n_irqs; i++) {
287 /* Put hardware irq number in Source Vector Register: */
288 at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
289 /* Active Low interrupt, with the specified priority */
290 at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
291 irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
292 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
293 }
294
295 at91_aic_hw_init(n_irqs);
296}
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 4073ab7f38f3..a42360f69127 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -29,7 +29,6 @@
29#include <mach/cpu.h> 29#include <mach/cpu.h>
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31 31
32#include "at91_aic.h"
33#include "generic.h" 32#include "generic.h"
34#include "pm.h" 33#include "pm.h"
35#include "gpio.h" 34#include "gpio.h"
@@ -136,19 +135,6 @@ static int at91_pm_enter(suspend_state_t state)
136 else 135 else
137 at91_gpio_suspend(); 136 at91_gpio_suspend();
138 137
139 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base) {
140 at91_irq_suspend();
141
142 pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
143 /* remember all the always-wake irqs */
144 (at91_pmc_read(AT91_PMC_PCSR)
145 | (1 << AT91_ID_FIQ)
146 | (1 << AT91_ID_SYS)
147 | (at91_get_extern_irq()))
148 & at91_aic_read(AT91_AIC_IMR),
149 state);
150 }
151
152 switch (state) { 138 switch (state) {
153 /* 139 /*
154 * Suspend-to-RAM is like STANDBY plus slow clock mode, so 140 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
@@ -212,17 +198,9 @@ static int at91_pm_enter(suspend_state_t state)
212 goto error; 198 goto error;
213 } 199 }
214 200
215 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
216 pr_debug("AT91: PM - wakeup %08x\n",
217 at91_aic_read(AT91_AIC_IPR) &
218 at91_aic_read(AT91_AIC_IMR));
219
220error: 201error:
221 target_state = PM_SUSPEND_ON; 202 target_state = PM_SUSPEND_ON;
222 203
223 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
224 at91_irq_resume();
225
226 if (of_have_populated_dt()) 204 if (of_have_populated_dt())
227 at91_pinctrl_gpio_resume(); 205 at91_pinctrl_gpio_resume();
228 else 206 else
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index a78fbb7b13c9..6c3013e3309b 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -49,10 +49,6 @@ void __init at91_init_irq_default(void)
49 49
50void __init at91_init_interrupts(unsigned int *priority) 50void __init at91_init_interrupts(unsigned int *priority)
51{ 51{
52 /* Initialize the AIC interrupt controller */
53 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
54 at91_aic_init(priority, at91_boot_soc.extern_irq);
55
56 /* Enable GPIO interrupts */ 52 /* Enable GPIO interrupts */
57 at91_gpio_irq_setup(); 53 at91_gpio_irq_setup();
58} 54}
@@ -460,9 +456,6 @@ void __init at91rm9200_dt_initialize(void)
460{ 456{
461 at91_dt_ramc(); 457 at91_dt_ramc();
462 458
463 /* Init clock subsystem */
464 at91_dt_clock_init();
465
466 /* Register the processor-specific clocks */ 459 /* Register the processor-specific clocks */
467 if (at91_boot_soc.register_clocks) 460 if (at91_boot_soc.register_clocks)
468 at91_boot_soc.register_clocks(); 461 at91_boot_soc.register_clocks();
@@ -474,9 +467,6 @@ void __init at91_dt_initialize(void)
474{ 467{
475 at91_dt_ramc(); 468 at91_dt_ramc();
476 469
477 /* Init clock subsystem */
478 at91_dt_clock_init();
479
480 /* Register the processor-specific clocks */ 470 /* Register the processor-specific clocks */
481 if (at91_boot_soc.register_clocks) 471 if (at91_boot_soc.register_clocks)
482 at91_boot_soc.register_clocks(); 472 at91_boot_soc.register_clocks();
@@ -490,9 +480,6 @@ void __init at91_initialize(unsigned long main_clock)
490{ 480{
491 at91_boot_soc.ioremap_registers(); 481 at91_boot_soc.ioremap_registers();
492 482
493 /* Init clock subsystem */
494 at91_clock_init(main_clock);
495
496 /* Register the processor-specific clocks */ 483 /* Register the processor-specific clocks */
497 at91_boot_soc.register_clocks(); 484 at91_boot_soc.register_clocks();
498 485
diff --git a/drivers/net/ethernet/cadence/Kconfig b/drivers/net/ethernet/cadence/Kconfig
index 9e089d24466e..3564fe9d3f69 100644
--- a/drivers/net/ethernet/cadence/Kconfig
+++ b/drivers/net/ethernet/cadence/Kconfig
@@ -22,7 +22,7 @@ if NET_CADENCE
22 22
23config ARM_AT91_ETHER 23config ARM_AT91_ETHER
24 tristate "AT91RM9200 Ethernet support" 24 tristate "AT91RM9200 Ethernet support"
25 depends on HAS_DMA && (ARCH_AT91RM9200 || COMPILE_TEST) 25 depends on HAS_DMA && (ARCH_AT91 || COMPILE_TEST)
26 select MACB 26 select MACB
27 ---help--- 27 ---help---
28 If you wish to compile a kernel for the AT91RM9200 and enable 28 If you wish to compile a kernel for the AT91RM9200 and enable
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 15a232e1c2a0..da5a1c789f36 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1110,7 +1110,7 @@ config RTC_DRV_AT91RM9200
1110 1110
1111config RTC_DRV_AT91SAM9 1111config RTC_DRV_AT91SAM9
1112 tristate "AT91SAM9x/AT91CAP9 RTT as RTC" 1112 tristate "AT91SAM9x/AT91CAP9 RTT as RTC"
1113 depends on ARCH_AT91 && !ARCH_AT91RM9200 1113 depends on ARCH_AT91
1114 help 1114 help
1115 RTC driver for the Atmel AT91SAM9x and AT91CAP9 internal RTT 1115 RTC driver for the Atmel AT91SAM9x and AT91CAP9 internal RTT
1116 (Real Time Timer). These timers are powered by the backup power 1116 (Real Time Timer). These timers are powered by the backup power
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index d0107d424ee4..08f41add1461 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -154,14 +154,14 @@ config ARM_SP805_WATCHDOG
154 154
155config AT91RM9200_WATCHDOG 155config AT91RM9200_WATCHDOG
156 tristate "AT91RM9200 watchdog" 156 tristate "AT91RM9200 watchdog"
157 depends on ARCH_AT91RM9200 157 depends on SOC_AT91RM9200
158 help 158 help
159 Watchdog timer embedded into AT91RM9200 chips. This will reboot your 159 Watchdog timer embedded into AT91RM9200 chips. This will reboot your
160 system when the timeout is reached. 160 system when the timeout is reached.
161 161
162config AT91SAM9X_WATCHDOG 162config AT91SAM9X_WATCHDOG
163 tristate "AT91SAM9X / AT91CAP9 watchdog" 163 tristate "AT91SAM9X / AT91CAP9 watchdog"
164 depends on ARCH_AT91 && !ARCH_AT91RM9200 164 depends on ARCH_AT91
165 select WATCHDOG_CORE 165 select WATCHDOG_CORE
166 help 166 help
167 Watchdog timer embedded into AT91SAM9X and AT91CAP9 chips. This will 167 Watchdog timer embedded into AT91SAM9X and AT91CAP9 chips. This will
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 07:40:08 -0400