diff options
author | Ben Dooks <ben-linux@fluff.org> | 2009-05-17 17:08:32 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2009-05-18 11:26:01 -0400 |
commit | 9c7099ca7519268f6ec79782bc06faa27a714d95 (patch) | |
tree | c286b53343abb59d5b23dfac323790406ff3db23 | |
parent | 86c03c526e2b282846c09509a48ab8be68fe7168 (diff) |
[ARM] S3C24XX: GPIO: Clean out unused definitions in <mach/regs-gpio.h>
The <mach/regs-gpio.h> really does not need the input and output
pin configurations as these are standard and have a generic
representation (plus the s3c24xx gpio specific code is going to
be phased out soon).
The following sed was applied to remove the lines:
sed -i~ -e '/S3C2410_GP[A-Z][0-9]*_\INP/d' \
-e '/S3C2410_GP[A-Z][0-9]*_\OUTP/d' \
-e '/S3C2410_GPA[0-9]*_OUT/d'
to remove these.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
-rw-r--r-- | arch/arm/mach-s3c2410/include/mach/regs-gpio.h | 211 |
1 files changed, 0 insertions, 211 deletions
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index 35a03df473fc..90cefebd2937 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h | |||
@@ -70,103 +70,80 @@ | |||
70 | #define S3C2400_GPADAT S3C2410_GPIOREG(0x04) | 70 | #define S3C2400_GPADAT S3C2410_GPIOREG(0x04) |
71 | 71 | ||
72 | #define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) | 72 | #define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) |
73 | #define S3C2410_GPA0_OUT (0<<0) | ||
74 | #define S3C2410_GPA0_ADDR0 (1<<0) | 73 | #define S3C2410_GPA0_ADDR0 (1<<0) |
75 | 74 | ||
76 | #define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1) | 75 | #define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1) |
77 | #define S3C2410_GPA1_OUT (0<<1) | ||
78 | #define S3C2410_GPA1_ADDR16 (1<<1) | 76 | #define S3C2410_GPA1_ADDR16 (1<<1) |
79 | 77 | ||
80 | #define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2) | 78 | #define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2) |
81 | #define S3C2410_GPA2_OUT (0<<2) | ||
82 | #define S3C2410_GPA2_ADDR17 (1<<2) | 79 | #define S3C2410_GPA2_ADDR17 (1<<2) |
83 | 80 | ||
84 | #define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3) | 81 | #define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3) |
85 | #define S3C2410_GPA3_OUT (0<<3) | ||
86 | #define S3C2410_GPA3_ADDR18 (1<<3) | 82 | #define S3C2410_GPA3_ADDR18 (1<<3) |
87 | 83 | ||
88 | #define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4) | 84 | #define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4) |
89 | #define S3C2410_GPA4_OUT (0<<4) | ||
90 | #define S3C2410_GPA4_ADDR19 (1<<4) | 85 | #define S3C2410_GPA4_ADDR19 (1<<4) |
91 | 86 | ||
92 | #define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5) | 87 | #define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5) |
93 | #define S3C2410_GPA5_OUT (0<<5) | ||
94 | #define S3C2410_GPA5_ADDR20 (1<<5) | 88 | #define S3C2410_GPA5_ADDR20 (1<<5) |
95 | 89 | ||
96 | #define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6) | 90 | #define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6) |
97 | #define S3C2410_GPA6_OUT (0<<6) | ||
98 | #define S3C2410_GPA6_ADDR21 (1<<6) | 91 | #define S3C2410_GPA6_ADDR21 (1<<6) |
99 | 92 | ||
100 | #define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7) | 93 | #define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7) |
101 | #define S3C2410_GPA7_OUT (0<<7) | ||
102 | #define S3C2410_GPA7_ADDR22 (1<<7) | 94 | #define S3C2410_GPA7_ADDR22 (1<<7) |
103 | 95 | ||
104 | #define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8) | 96 | #define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8) |
105 | #define S3C2410_GPA8_OUT (0<<8) | ||
106 | #define S3C2410_GPA8_ADDR23 (1<<8) | 97 | #define S3C2410_GPA8_ADDR23 (1<<8) |
107 | 98 | ||
108 | #define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9) | 99 | #define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9) |
109 | #define S3C2410_GPA9_OUT (0<<9) | ||
110 | #define S3C2410_GPA9_ADDR24 (1<<9) | 100 | #define S3C2410_GPA9_ADDR24 (1<<9) |
111 | 101 | ||
112 | #define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) | 102 | #define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) |
113 | #define S3C2410_GPA10_OUT (0<<10) | ||
114 | #define S3C2410_GPA10_ADDR25 (1<<10) | 103 | #define S3C2410_GPA10_ADDR25 (1<<10) |
115 | #define S3C2400_GPA10_SCKE (1<<10) | 104 | #define S3C2400_GPA10_SCKE (1<<10) |
116 | 105 | ||
117 | #define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) | 106 | #define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) |
118 | #define S3C2410_GPA11_OUT (0<<11) | ||
119 | #define S3C2410_GPA11_ADDR26 (1<<11) | 107 | #define S3C2410_GPA11_ADDR26 (1<<11) |
120 | #define S3C2400_GPA11_nCAS0 (1<<11) | 108 | #define S3C2400_GPA11_nCAS0 (1<<11) |
121 | 109 | ||
122 | #define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) | 110 | #define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) |
123 | #define S3C2410_GPA12_OUT (0<<12) | ||
124 | #define S3C2410_GPA12_nGCS1 (1<<12) | 111 | #define S3C2410_GPA12_nGCS1 (1<<12) |
125 | #define S3C2400_GPA12_nCAS1 (1<<12) | 112 | #define S3C2400_GPA12_nCAS1 (1<<12) |
126 | 113 | ||
127 | #define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) | 114 | #define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) |
128 | #define S3C2410_GPA13_OUT (0<<13) | ||
129 | #define S3C2410_GPA13_nGCS2 (1<<13) | 115 | #define S3C2410_GPA13_nGCS2 (1<<13) |
130 | #define S3C2400_GPA13_nGCS1 (1<<13) | 116 | #define S3C2400_GPA13_nGCS1 (1<<13) |
131 | 117 | ||
132 | #define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) | 118 | #define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) |
133 | #define S3C2410_GPA14_OUT (0<<14) | ||
134 | #define S3C2410_GPA14_nGCS3 (1<<14) | 119 | #define S3C2410_GPA14_nGCS3 (1<<14) |
135 | #define S3C2400_GPA14_nGCS2 (1<<14) | 120 | #define S3C2400_GPA14_nGCS2 (1<<14) |
136 | 121 | ||
137 | #define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) | 122 | #define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) |
138 | #define S3C2410_GPA15_OUT (0<<15) | ||
139 | #define S3C2410_GPA15_nGCS4 (1<<15) | 123 | #define S3C2410_GPA15_nGCS4 (1<<15) |
140 | #define S3C2400_GPA15_nGCS3 (1<<15) | 124 | #define S3C2400_GPA15_nGCS3 (1<<15) |
141 | 125 | ||
142 | #define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) | 126 | #define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) |
143 | #define S3C2410_GPA16_OUT (0<<16) | ||
144 | #define S3C2410_GPA16_nGCS5 (1<<16) | 127 | #define S3C2410_GPA16_nGCS5 (1<<16) |
145 | #define S3C2400_GPA16_nGCS4 (1<<16) | 128 | #define S3C2400_GPA16_nGCS4 (1<<16) |
146 | 129 | ||
147 | #define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) | 130 | #define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) |
148 | #define S3C2410_GPA17_OUT (0<<17) | ||
149 | #define S3C2410_GPA17_CLE (1<<17) | 131 | #define S3C2410_GPA17_CLE (1<<17) |
150 | #define S3C2400_GPA17_nGCS5 (1<<17) | 132 | #define S3C2400_GPA17_nGCS5 (1<<17) |
151 | 133 | ||
152 | #define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) | 134 | #define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) |
153 | #define S3C2410_GPA18_OUT (0<<18) | ||
154 | #define S3C2410_GPA18_ALE (1<<18) | 135 | #define S3C2410_GPA18_ALE (1<<18) |
155 | 136 | ||
156 | #define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19) | 137 | #define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19) |
157 | #define S3C2410_GPA19_OUT (0<<19) | ||
158 | #define S3C2410_GPA19_nFWE (1<<19) | 138 | #define S3C2410_GPA19_nFWE (1<<19) |
159 | 139 | ||
160 | #define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20) | 140 | #define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20) |
161 | #define S3C2410_GPA20_OUT (0<<20) | ||
162 | #define S3C2410_GPA20_nFRE (1<<20) | 141 | #define S3C2410_GPA20_nFRE (1<<20) |
163 | 142 | ||
164 | #define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21) | 143 | #define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21) |
165 | #define S3C2410_GPA21_OUT (0<<21) | ||
166 | #define S3C2410_GPA21_nRSTOUT (1<<21) | 144 | #define S3C2410_GPA21_nRSTOUT (1<<21) |
167 | 145 | ||
168 | #define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22) | 146 | #define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22) |
169 | #define S3C2410_GPA22_OUT (0<<22) | ||
170 | #define S3C2410_GPA22_nFCE (1<<22) | 147 | #define S3C2410_GPA22_nFCE (1<<22) |
171 | 148 | ||
172 | /* 0x08 and 0x0c are reserved on S3C2410 */ | 149 | /* 0x08 and 0x0c are reserved on S3C2410 */ |
@@ -195,34 +172,24 @@ | |||
195 | /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ | 172 | /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ |
196 | 173 | ||
197 | #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) | 174 | #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) |
198 | #define S3C2410_GPB0_INP (0x00 << 0) | ||
199 | #define S3C2410_GPB0_OUTP (0x01 << 0) | ||
200 | #define S3C2410_GPB0_TOUT0 (0x02 << 0) | 175 | #define S3C2410_GPB0_TOUT0 (0x02 << 0) |
201 | #define S3C2400_GPB0_DATA16 (0x02 << 0) | 176 | #define S3C2400_GPB0_DATA16 (0x02 << 0) |
202 | 177 | ||
203 | #define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) | 178 | #define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) |
204 | #define S3C2410_GPB1_INP (0x00 << 2) | ||
205 | #define S3C2410_GPB1_OUTP (0x01 << 2) | ||
206 | #define S3C2410_GPB1_TOUT1 (0x02 << 2) | 179 | #define S3C2410_GPB1_TOUT1 (0x02 << 2) |
207 | #define S3C2400_GPB1_DATA17 (0x02 << 2) | 180 | #define S3C2400_GPB1_DATA17 (0x02 << 2) |
208 | 181 | ||
209 | #define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) | 182 | #define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) |
210 | #define S3C2410_GPB2_INP (0x00 << 4) | ||
211 | #define S3C2410_GPB2_OUTP (0x01 << 4) | ||
212 | #define S3C2410_GPB2_TOUT2 (0x02 << 4) | 183 | #define S3C2410_GPB2_TOUT2 (0x02 << 4) |
213 | #define S3C2400_GPB2_DATA18 (0x02 << 4) | 184 | #define S3C2400_GPB2_DATA18 (0x02 << 4) |
214 | #define S3C2400_GPB2_TCLK1 (0x03 << 4) | 185 | #define S3C2400_GPB2_TCLK1 (0x03 << 4) |
215 | 186 | ||
216 | #define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) | 187 | #define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) |
217 | #define S3C2410_GPB3_INP (0x00 << 6) | ||
218 | #define S3C2410_GPB3_OUTP (0x01 << 6) | ||
219 | #define S3C2410_GPB3_TOUT3 (0x02 << 6) | 188 | #define S3C2410_GPB3_TOUT3 (0x02 << 6) |
220 | #define S3C2400_GPB3_DATA19 (0x02 << 6) | 189 | #define S3C2400_GPB3_DATA19 (0x02 << 6) |
221 | #define S3C2400_GPB3_TXD1 (0x03 << 6) | 190 | #define S3C2400_GPB3_TXD1 (0x03 << 6) |
222 | 191 | ||
223 | #define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) | 192 | #define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) |
224 | #define S3C2410_GPB4_INP (0x00 << 8) | ||
225 | #define S3C2410_GPB4_OUTP (0x01 << 8) | ||
226 | #define S3C2410_GPB4_TCLK0 (0x02 << 8) | 193 | #define S3C2410_GPB4_TCLK0 (0x02 << 8) |
227 | #define S3C2400_GPB4_DATA20 (0x02 << 8) | 194 | #define S3C2400_GPB4_DATA20 (0x02 << 8) |
228 | #define S3C2410_GPB4_MASK (0x03 << 8) | 195 | #define S3C2410_GPB4_MASK (0x03 << 8) |
@@ -230,45 +197,33 @@ | |||
230 | #define S3C2400_GPB4_MASK (0x03 << 8) | 197 | #define S3C2400_GPB4_MASK (0x03 << 8) |
231 | 198 | ||
232 | #define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) | 199 | #define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) |
233 | #define S3C2410_GPB5_INP (0x00 << 10) | ||
234 | #define S3C2410_GPB5_OUTP (0x01 << 10) | ||
235 | #define S3C2410_GPB5_nXBACK (0x02 << 10) | 200 | #define S3C2410_GPB5_nXBACK (0x02 << 10) |
236 | #define S3C2443_GPB5_XBACK (0x03 << 10) | 201 | #define S3C2443_GPB5_XBACK (0x03 << 10) |
237 | #define S3C2400_GPB5_DATA21 (0x02 << 10) | 202 | #define S3C2400_GPB5_DATA21 (0x02 << 10) |
238 | #define S3C2400_GPB5_nCTS1 (0x03 << 10) | 203 | #define S3C2400_GPB5_nCTS1 (0x03 << 10) |
239 | 204 | ||
240 | #define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) | 205 | #define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) |
241 | #define S3C2410_GPB6_INP (0x00 << 12) | ||
242 | #define S3C2410_GPB6_OUTP (0x01 << 12) | ||
243 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) | 206 | #define S3C2410_GPB6_nXBREQ (0x02 << 12) |
244 | #define S3C2443_GPB6_XBREQ (0x03 << 12) | 207 | #define S3C2443_GPB6_XBREQ (0x03 << 12) |
245 | #define S3C2400_GPB6_DATA22 (0x02 << 12) | 208 | #define S3C2400_GPB6_DATA22 (0x02 << 12) |
246 | #define S3C2400_GPB6_nRTS1 (0x03 << 12) | 209 | #define S3C2400_GPB6_nRTS1 (0x03 << 12) |
247 | 210 | ||
248 | #define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) | 211 | #define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) |
249 | #define S3C2410_GPB7_INP (0x00 << 14) | ||
250 | #define S3C2410_GPB7_OUTP (0x01 << 14) | ||
251 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) | 212 | #define S3C2410_GPB7_nXDACK1 (0x02 << 14) |
252 | #define S3C2443_GPB7_XDACK1 (0x03 << 14) | 213 | #define S3C2443_GPB7_XDACK1 (0x03 << 14) |
253 | #define S3C2400_GPB7_DATA23 (0x02 << 14) | 214 | #define S3C2400_GPB7_DATA23 (0x02 << 14) |
254 | 215 | ||
255 | #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) | 216 | #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) |
256 | #define S3C2410_GPB8_INP (0x00 << 16) | ||
257 | #define S3C2410_GPB8_OUTP (0x01 << 16) | ||
258 | #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) | 217 | #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) |
259 | #define S3C2400_GPB8_DATA24 (0x02 << 16) | 218 | #define S3C2400_GPB8_DATA24 (0x02 << 16) |
260 | 219 | ||
261 | #define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) | 220 | #define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) |
262 | #define S3C2410_GPB9_INP (0x00 << 18) | ||
263 | #define S3C2410_GPB9_OUTP (0x01 << 18) | ||
264 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) | 221 | #define S3C2410_GPB9_nXDACK0 (0x02 << 18) |
265 | #define S3C2443_GPB9_XDACK0 (0x03 << 18) | 222 | #define S3C2443_GPB9_XDACK0 (0x03 << 18) |
266 | #define S3C2400_GPB9_DATA25 (0x02 << 18) | 223 | #define S3C2400_GPB9_DATA25 (0x02 << 18) |
267 | #define S3C2400_GPB9_I2SSDI (0x03 << 18) | 224 | #define S3C2400_GPB9_I2SSDI (0x03 << 18) |
268 | 225 | ||
269 | #define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) | 226 | #define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) |
270 | #define S3C2410_GPB10_INP (0x00 << 20) | ||
271 | #define S3C2410_GPB10_OUTP (0x01 << 20) | ||
272 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) | 227 | #define S3C2410_GPB10_nXDRE0 (0x02 << 20) |
273 | #define S3C2443_GPB10_XDREQ0 (0x03 << 20) | 228 | #define S3C2443_GPB10_XDREQ0 (0x03 << 20) |
274 | #define S3C2400_GPB10_DATA26 (0x02 << 20) | 229 | #define S3C2400_GPB10_DATA26 (0x02 << 20) |
@@ -316,98 +271,66 @@ | |||
316 | #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) | 271 | #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) |
317 | 272 | ||
318 | #define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) | 273 | #define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) |
319 | #define S3C2410_GPC0_INP (0x00 << 0) | ||
320 | #define S3C2410_GPC0_OUTP (0x01 << 0) | ||
321 | #define S3C2410_GPC0_LEND (0x02 << 0) | 274 | #define S3C2410_GPC0_LEND (0x02 << 0) |
322 | #define S3C2400_GPC0_VD0 (0x02 << 0) | 275 | #define S3C2400_GPC0_VD0 (0x02 << 0) |
323 | 276 | ||
324 | #define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) | 277 | #define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) |
325 | #define S3C2410_GPC1_INP (0x00 << 2) | ||
326 | #define S3C2410_GPC1_OUTP (0x01 << 2) | ||
327 | #define S3C2410_GPC1_VCLK (0x02 << 2) | 278 | #define S3C2410_GPC1_VCLK (0x02 << 2) |
328 | #define S3C2400_GPC1_VD1 (0x02 << 2) | 279 | #define S3C2400_GPC1_VD1 (0x02 << 2) |
329 | 280 | ||
330 | #define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) | 281 | #define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) |
331 | #define S3C2410_GPC2_INP (0x00 << 4) | ||
332 | #define S3C2410_GPC2_OUTP (0x01 << 4) | ||
333 | #define S3C2410_GPC2_VLINE (0x02 << 4) | 282 | #define S3C2410_GPC2_VLINE (0x02 << 4) |
334 | #define S3C2400_GPC2_VD2 (0x02 << 4) | 283 | #define S3C2400_GPC2_VD2 (0x02 << 4) |
335 | 284 | ||
336 | #define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) | 285 | #define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) |
337 | #define S3C2410_GPC3_INP (0x00 << 6) | ||
338 | #define S3C2410_GPC3_OUTP (0x01 << 6) | ||
339 | #define S3C2410_GPC3_VFRAME (0x02 << 6) | 286 | #define S3C2410_GPC3_VFRAME (0x02 << 6) |
340 | #define S3C2400_GPC3_VD3 (0x02 << 6) | 287 | #define S3C2400_GPC3_VD3 (0x02 << 6) |
341 | 288 | ||
342 | #define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) | 289 | #define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) |
343 | #define S3C2410_GPC4_INP (0x00 << 8) | ||
344 | #define S3C2410_GPC4_OUTP (0x01 << 8) | ||
345 | #define S3C2410_GPC4_VM (0x02 << 8) | 290 | #define S3C2410_GPC4_VM (0x02 << 8) |
346 | #define S3C2400_GPC4_VD4 (0x02 << 8) | 291 | #define S3C2400_GPC4_VD4 (0x02 << 8) |
347 | 292 | ||
348 | #define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) | 293 | #define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) |
349 | #define S3C2410_GPC5_INP (0x00 << 10) | ||
350 | #define S3C2410_GPC5_OUTP (0x01 << 10) | ||
351 | #define S3C2410_GPC5_LCDVF0 (0x02 << 10) | 294 | #define S3C2410_GPC5_LCDVF0 (0x02 << 10) |
352 | #define S3C2400_GPC5_VD5 (0x02 << 10) | 295 | #define S3C2400_GPC5_VD5 (0x02 << 10) |
353 | 296 | ||
354 | #define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) | 297 | #define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) |
355 | #define S3C2410_GPC6_INP (0x00 << 12) | ||
356 | #define S3C2410_GPC6_OUTP (0x01 << 12) | ||
357 | #define S3C2410_GPC6_LCDVF1 (0x02 << 12) | 298 | #define S3C2410_GPC6_LCDVF1 (0x02 << 12) |
358 | #define S3C2400_GPC6_VD6 (0x02 << 12) | 299 | #define S3C2400_GPC6_VD6 (0x02 << 12) |
359 | 300 | ||
360 | #define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) | 301 | #define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) |
361 | #define S3C2410_GPC7_INP (0x00 << 14) | ||
362 | #define S3C2410_GPC7_OUTP (0x01 << 14) | ||
363 | #define S3C2410_GPC7_LCDVF2 (0x02 << 14) | 302 | #define S3C2410_GPC7_LCDVF2 (0x02 << 14) |
364 | #define S3C2400_GPC7_VD7 (0x02 << 14) | 303 | #define S3C2400_GPC7_VD7 (0x02 << 14) |
365 | 304 | ||
366 | #define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) | 305 | #define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) |
367 | #define S3C2410_GPC8_INP (0x00 << 16) | ||
368 | #define S3C2410_GPC8_OUTP (0x01 << 16) | ||
369 | #define S3C2410_GPC8_VD0 (0x02 << 16) | 306 | #define S3C2410_GPC8_VD0 (0x02 << 16) |
370 | #define S3C2400_GPC8_VD8 (0x02 << 16) | 307 | #define S3C2400_GPC8_VD8 (0x02 << 16) |
371 | 308 | ||
372 | #define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) | 309 | #define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) |
373 | #define S3C2410_GPC9_INP (0x00 << 18) | ||
374 | #define S3C2410_GPC9_OUTP (0x01 << 18) | ||
375 | #define S3C2410_GPC9_VD1 (0x02 << 18) | 310 | #define S3C2410_GPC9_VD1 (0x02 << 18) |
376 | #define S3C2400_GPC9_VD9 (0x02 << 18) | 311 | #define S3C2400_GPC9_VD9 (0x02 << 18) |
377 | 312 | ||
378 | #define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) | 313 | #define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) |
379 | #define S3C2410_GPC10_INP (0x00 << 20) | ||
380 | #define S3C2410_GPC10_OUTP (0x01 << 20) | ||
381 | #define S3C2410_GPC10_VD2 (0x02 << 20) | 314 | #define S3C2410_GPC10_VD2 (0x02 << 20) |
382 | #define S3C2400_GPC10_VD10 (0x02 << 20) | 315 | #define S3C2400_GPC10_VD10 (0x02 << 20) |
383 | 316 | ||
384 | #define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) | 317 | #define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) |
385 | #define S3C2410_GPC11_INP (0x00 << 22) | ||
386 | #define S3C2410_GPC11_OUTP (0x01 << 22) | ||
387 | #define S3C2410_GPC11_VD3 (0x02 << 22) | 318 | #define S3C2410_GPC11_VD3 (0x02 << 22) |
388 | #define S3C2400_GPC11_VD11 (0x02 << 22) | 319 | #define S3C2400_GPC11_VD11 (0x02 << 22) |
389 | 320 | ||
390 | #define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) | 321 | #define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) |
391 | #define S3C2410_GPC12_INP (0x00 << 24) | ||
392 | #define S3C2410_GPC12_OUTP (0x01 << 24) | ||
393 | #define S3C2410_GPC12_VD4 (0x02 << 24) | 322 | #define S3C2410_GPC12_VD4 (0x02 << 24) |
394 | #define S3C2400_GPC12_VD12 (0x02 << 24) | 323 | #define S3C2400_GPC12_VD12 (0x02 << 24) |
395 | 324 | ||
396 | #define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) | 325 | #define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) |
397 | #define S3C2410_GPC13_INP (0x00 << 26) | ||
398 | #define S3C2410_GPC13_OUTP (0x01 << 26) | ||
399 | #define S3C2410_GPC13_VD5 (0x02 << 26) | 326 | #define S3C2410_GPC13_VD5 (0x02 << 26) |
400 | #define S3C2400_GPC13_VD13 (0x02 << 26) | 327 | #define S3C2400_GPC13_VD13 (0x02 << 26) |
401 | 328 | ||
402 | #define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) | 329 | #define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) |
403 | #define S3C2410_GPC14_INP (0x00 << 28) | ||
404 | #define S3C2410_GPC14_OUTP (0x01 << 28) | ||
405 | #define S3C2410_GPC14_VD6 (0x02 << 28) | 330 | #define S3C2410_GPC14_VD6 (0x02 << 28) |
406 | #define S3C2400_GPC14_VD14 (0x02 << 28) | 331 | #define S3C2400_GPC14_VD14 (0x02 << 28) |
407 | 332 | ||
408 | #define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) | 333 | #define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) |
409 | #define S3C2410_GPC15_INP (0x00 << 30) | ||
410 | #define S3C2410_GPC15_OUTP (0x01 << 30) | ||
411 | #define S3C2410_GPC15_VD7 (0x02 << 30) | 334 | #define S3C2410_GPC15_VD7 (0x02 << 30) |
412 | #define S3C2400_GPC15_VD15 (0x02 << 30) | 335 | #define S3C2400_GPC15_VD15 (0x02 << 30) |
413 | 336 | ||
@@ -433,98 +356,66 @@ | |||
433 | #define S3C2400_GPDUP S3C2410_GPIOREG(0x28) | 356 | #define S3C2400_GPDUP S3C2410_GPIOREG(0x28) |
434 | 357 | ||
435 | #define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) | 358 | #define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) |
436 | #define S3C2410_GPD0_INP (0x00 << 0) | ||
437 | #define S3C2410_GPD0_OUTP (0x01 << 0) | ||
438 | #define S3C2410_GPD0_VD8 (0x02 << 0) | 359 | #define S3C2410_GPD0_VD8 (0x02 << 0) |
439 | #define S3C2400_GPD0_VFRAME (0x02 << 0) | 360 | #define S3C2400_GPD0_VFRAME (0x02 << 0) |
440 | #define S3C2442_GPD0_nSPICS1 (0x03 << 0) | 361 | #define S3C2442_GPD0_nSPICS1 (0x03 << 0) |
441 | 362 | ||
442 | #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) | 363 | #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) |
443 | #define S3C2410_GPD1_INP (0x00 << 2) | ||
444 | #define S3C2410_GPD1_OUTP (0x01 << 2) | ||
445 | #define S3C2410_GPD1_VD9 (0x02 << 2) | 364 | #define S3C2410_GPD1_VD9 (0x02 << 2) |
446 | #define S3C2400_GPD1_VM (0x02 << 2) | 365 | #define S3C2400_GPD1_VM (0x02 << 2) |
447 | #define S3C2442_GPD1_SPICLK1 (0x03 << 2) | 366 | #define S3C2442_GPD1_SPICLK1 (0x03 << 2) |
448 | 367 | ||
449 | #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) | 368 | #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) |
450 | #define S3C2410_GPD2_INP (0x00 << 4) | ||
451 | #define S3C2410_GPD2_OUTP (0x01 << 4) | ||
452 | #define S3C2410_GPD2_VD10 (0x02 << 4) | 369 | #define S3C2410_GPD2_VD10 (0x02 << 4) |
453 | #define S3C2400_GPD2_VLINE (0x02 << 4) | 370 | #define S3C2400_GPD2_VLINE (0x02 << 4) |
454 | 371 | ||
455 | #define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) | 372 | #define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) |
456 | #define S3C2410_GPD3_INP (0x00 << 6) | ||
457 | #define S3C2410_GPD3_OUTP (0x01 << 6) | ||
458 | #define S3C2410_GPD3_VD11 (0x02 << 6) | 373 | #define S3C2410_GPD3_VD11 (0x02 << 6) |
459 | #define S3C2400_GPD3_VCLK (0x02 << 6) | 374 | #define S3C2400_GPD3_VCLK (0x02 << 6) |
460 | 375 | ||
461 | #define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) | 376 | #define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) |
462 | #define S3C2410_GPD4_INP (0x00 << 8) | ||
463 | #define S3C2410_GPD4_OUTP (0x01 << 8) | ||
464 | #define S3C2410_GPD4_VD12 (0x02 << 8) | 377 | #define S3C2410_GPD4_VD12 (0x02 << 8) |
465 | #define S3C2400_GPD4_LEND (0x02 << 8) | 378 | #define S3C2400_GPD4_LEND (0x02 << 8) |
466 | 379 | ||
467 | #define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) | 380 | #define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) |
468 | #define S3C2410_GPD5_INP (0x00 << 10) | ||
469 | #define S3C2410_GPD5_OUTP (0x01 << 10) | ||
470 | #define S3C2410_GPD5_VD13 (0x02 << 10) | 381 | #define S3C2410_GPD5_VD13 (0x02 << 10) |
471 | #define S3C2400_GPD5_TOUT0 (0x02 << 10) | 382 | #define S3C2400_GPD5_TOUT0 (0x02 << 10) |
472 | 383 | ||
473 | #define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) | 384 | #define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) |
474 | #define S3C2410_GPD6_INP (0x00 << 12) | ||
475 | #define S3C2410_GPD6_OUTP (0x01 << 12) | ||
476 | #define S3C2410_GPD6_VD14 (0x02 << 12) | 385 | #define S3C2410_GPD6_VD14 (0x02 << 12) |
477 | #define S3C2400_GPD6_TOUT1 (0x02 << 12) | 386 | #define S3C2400_GPD6_TOUT1 (0x02 << 12) |
478 | 387 | ||
479 | #define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) | 388 | #define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) |
480 | #define S3C2410_GPD7_INP (0x00 << 14) | ||
481 | #define S3C2410_GPD7_OUTP (0x01 << 14) | ||
482 | #define S3C2410_GPD7_VD15 (0x02 << 14) | 389 | #define S3C2410_GPD7_VD15 (0x02 << 14) |
483 | #define S3C2400_GPD7_TOUT2 (0x02 << 14) | 390 | #define S3C2400_GPD7_TOUT2 (0x02 << 14) |
484 | 391 | ||
485 | #define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) | 392 | #define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) |
486 | #define S3C2410_GPD8_INP (0x00 << 16) | ||
487 | #define S3C2410_GPD8_OUTP (0x01 << 16) | ||
488 | #define S3C2410_GPD8_VD16 (0x02 << 16) | 393 | #define S3C2410_GPD8_VD16 (0x02 << 16) |
489 | #define S3C2400_GPD8_TOUT3 (0x02 << 16) | 394 | #define S3C2400_GPD8_TOUT3 (0x02 << 16) |
490 | 395 | ||
491 | #define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) | 396 | #define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) |
492 | #define S3C2410_GPD9_INP (0x00 << 18) | ||
493 | #define S3C2410_GPD9_OUTP (0x01 << 18) | ||
494 | #define S3C2410_GPD9_VD17 (0x02 << 18) | 397 | #define S3C2410_GPD9_VD17 (0x02 << 18) |
495 | #define S3C2400_GPD9_TCLK0 (0x02 << 18) | 398 | #define S3C2400_GPD9_TCLK0 (0x02 << 18) |
496 | #define S3C2410_GPD9_MASK (0x03 << 18) | 399 | #define S3C2410_GPD9_MASK (0x03 << 18) |
497 | 400 | ||
498 | #define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) | 401 | #define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) |
499 | #define S3C2410_GPD10_INP (0x00 << 20) | ||
500 | #define S3C2410_GPD10_OUTP (0x01 << 20) | ||
501 | #define S3C2410_GPD10_VD18 (0x02 << 20) | 402 | #define S3C2410_GPD10_VD18 (0x02 << 20) |
502 | #define S3C2400_GPD10_nWAIT (0x02 << 20) | 403 | #define S3C2400_GPD10_nWAIT (0x02 << 20) |
503 | 404 | ||
504 | #define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) | 405 | #define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) |
505 | #define S3C2410_GPD11_INP (0x00 << 22) | ||
506 | #define S3C2410_GPD11_OUTP (0x01 << 22) | ||
507 | #define S3C2410_GPD11_VD19 (0x02 << 22) | 406 | #define S3C2410_GPD11_VD19 (0x02 << 22) |
508 | 407 | ||
509 | #define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12) | 408 | #define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12) |
510 | #define S3C2410_GPD12_INP (0x00 << 24) | ||
511 | #define S3C2410_GPD12_OUTP (0x01 << 24) | ||
512 | #define S3C2410_GPD12_VD20 (0x02 << 24) | 409 | #define S3C2410_GPD12_VD20 (0x02 << 24) |
513 | 410 | ||
514 | #define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13) | 411 | #define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13) |
515 | #define S3C2410_GPD13_INP (0x00 << 26) | ||
516 | #define S3C2410_GPD13_OUTP (0x01 << 26) | ||
517 | #define S3C2410_GPD13_VD21 (0x02 << 26) | 412 | #define S3C2410_GPD13_VD21 (0x02 << 26) |
518 | 413 | ||
519 | #define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14) | 414 | #define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14) |
520 | #define S3C2410_GPD14_INP (0x00 << 28) | ||
521 | #define S3C2410_GPD14_OUTP (0x01 << 28) | ||
522 | #define S3C2410_GPD14_VD22 (0x02 << 28) | 415 | #define S3C2410_GPD14_VD22 (0x02 << 28) |
523 | #define S3C2410_GPD14_nSS1 (0x03 << 28) | 416 | #define S3C2410_GPD14_nSS1 (0x03 << 28) |
524 | 417 | ||
525 | #define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) | 418 | #define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) |
526 | #define S3C2410_GPD15_INP (0x00 << 30) | ||
527 | #define S3C2410_GPD15_OUTP (0x01 << 30) | ||
528 | #define S3C2410_GPD15_VD23 (0x02 << 30) | 419 | #define S3C2410_GPD15_VD23 (0x02 << 30) |
529 | #define S3C2410_GPD15_nSS0 (0x03 << 30) | 420 | #define S3C2410_GPD15_nSS0 (0x03 << 30) |
530 | 421 | ||
@@ -551,16 +442,12 @@ | |||
551 | #define S3C2400_GPEUP S3C2410_GPIOREG(0x34) | 442 | #define S3C2400_GPEUP S3C2410_GPIOREG(0x34) |
552 | 443 | ||
553 | #define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) | 444 | #define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) |
554 | #define S3C2410_GPE0_INP (0x00 << 0) | ||
555 | #define S3C2410_GPE0_OUTP (0x01 << 0) | ||
556 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) | 445 | #define S3C2410_GPE0_I2SLRCK (0x02 << 0) |
557 | #define S3C2443_GPE0_AC_nRESET (0x03 << 0) | 446 | #define S3C2443_GPE0_AC_nRESET (0x03 << 0) |
558 | #define S3C2400_GPE0_EINT0 (0x02 << 0) | 447 | #define S3C2400_GPE0_EINT0 (0x02 << 0) |
559 | #define S3C2410_GPE0_MASK (0x03 << 0) | 448 | #define S3C2410_GPE0_MASK (0x03 << 0) |
560 | 449 | ||
561 | #define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) | 450 | #define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) |
562 | #define S3C2410_GPE1_INP (0x00 << 2) | ||
563 | #define S3C2410_GPE1_OUTP (0x01 << 2) | ||
564 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) | 451 | #define S3C2410_GPE1_I2SSCLK (0x02 << 2) |
565 | #define S3C2443_GPE1_AC_SYNC (0x03 << 2) | 452 | #define S3C2443_GPE1_AC_SYNC (0x03 << 2) |
566 | #define S3C2400_GPE1_EINT1 (0x02 << 2) | 453 | #define S3C2400_GPE1_EINT1 (0x02 << 2) |
@@ -568,16 +455,12 @@ | |||
568 | #define S3C2410_GPE1_MASK (0x03 << 2) | 455 | #define S3C2410_GPE1_MASK (0x03 << 2) |
569 | 456 | ||
570 | #define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) | 457 | #define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) |
571 | #define S3C2410_GPE2_INP (0x00 << 4) | ||
572 | #define S3C2410_GPE2_OUTP (0x01 << 4) | ||
573 | #define S3C2410_GPE2_CDCLK (0x02 << 4) | 458 | #define S3C2410_GPE2_CDCLK (0x02 << 4) |
574 | #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) | 459 | #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) |
575 | #define S3C2400_GPE2_EINT2 (0x02 << 4) | 460 | #define S3C2400_GPE2_EINT2 (0x02 << 4) |
576 | #define S3C2400_GPE2_I2SSDI (0x03 << 4) | 461 | #define S3C2400_GPE2_I2SSDI (0x03 << 4) |
577 | 462 | ||
578 | #define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) | 463 | #define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) |
579 | #define S3C2410_GPE3_INP (0x00 << 6) | ||
580 | #define S3C2410_GPE3_OUTP (0x01 << 6) | ||
581 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) | 464 | #define S3C2410_GPE3_I2SSDI (0x02 << 6) |
582 | #define S3C2443_GPE3_AC_SDI (0x03 << 6) | 465 | #define S3C2443_GPE3_AC_SDI (0x03 << 6) |
583 | #define S3C2400_GPE3_EINT3 (0x02 << 6) | 466 | #define S3C2400_GPE3_EINT3 (0x02 << 6) |
@@ -586,8 +469,6 @@ | |||
586 | #define S3C2410_GPE3_MASK (0x03 << 6) | 469 | #define S3C2410_GPE3_MASK (0x03 << 6) |
587 | 470 | ||
588 | #define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4) | 471 | #define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4) |
589 | #define S3C2410_GPE4_INP (0x00 << 8) | ||
590 | #define S3C2410_GPE4_OUTP (0x01 << 8) | ||
591 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) | 472 | #define S3C2410_GPE4_I2SSDO (0x02 << 8) |
592 | #define S3C2443_GPE4_AC_SDO (0x03 << 8) | 473 | #define S3C2443_GPE4_AC_SDO (0x03 << 8) |
593 | #define S3C2400_GPE4_EINT4 (0x02 << 8) | 474 | #define S3C2400_GPE4_EINT4 (0x02 << 8) |
@@ -596,40 +477,30 @@ | |||
596 | #define S3C2410_GPE4_MASK (0x03 << 8) | 477 | #define S3C2410_GPE4_MASK (0x03 << 8) |
597 | 478 | ||
598 | #define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5) | 479 | #define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5) |
599 | #define S3C2410_GPE5_INP (0x00 << 10) | ||
600 | #define S3C2410_GPE5_OUTP (0x01 << 10) | ||
601 | #define S3C2410_GPE5_SDCLK (0x02 << 10) | 480 | #define S3C2410_GPE5_SDCLK (0x02 << 10) |
602 | #define S3C2443_GPE5_SD1_CLK (0x02 << 10) | 481 | #define S3C2443_GPE5_SD1_CLK (0x02 << 10) |
603 | #define S3C2400_GPE5_EINT5 (0x02 << 10) | 482 | #define S3C2400_GPE5_EINT5 (0x02 << 10) |
604 | #define S3C2400_GPE5_TCLK1 (0x03 << 10) | 483 | #define S3C2400_GPE5_TCLK1 (0x03 << 10) |
605 | 484 | ||
606 | #define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) | 485 | #define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) |
607 | #define S3C2410_GPE6_INP (0x00 << 12) | ||
608 | #define S3C2410_GPE6_OUTP (0x01 << 12) | ||
609 | #define S3C2410_GPE6_SDCMD (0x02 << 12) | 486 | #define S3C2410_GPE6_SDCMD (0x02 << 12) |
610 | #define S3C2443_GPE6_SD1_CMD (0x02 << 12) | 487 | #define S3C2443_GPE6_SD1_CMD (0x02 << 12) |
611 | #define S3C2443_GPE6_AC_BITCLK (0x03 << 12) | 488 | #define S3C2443_GPE6_AC_BITCLK (0x03 << 12) |
612 | #define S3C2400_GPE6_EINT6 (0x02 << 12) | 489 | #define S3C2400_GPE6_EINT6 (0x02 << 12) |
613 | 490 | ||
614 | #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) | 491 | #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) |
615 | #define S3C2410_GPE7_INP (0x00 << 14) | ||
616 | #define S3C2410_GPE7_OUTP (0x01 << 14) | ||
617 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) | 492 | #define S3C2410_GPE7_SDDAT0 (0x02 << 14) |
618 | #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) | 493 | #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) |
619 | #define S3C2443_GPE7_AC_SDI (0x03 << 14) | 494 | #define S3C2443_GPE7_AC_SDI (0x03 << 14) |
620 | #define S3C2400_GPE7_EINT7 (0x02 << 14) | 495 | #define S3C2400_GPE7_EINT7 (0x02 << 14) |
621 | 496 | ||
622 | #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) | 497 | #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) |
623 | #define S3C2410_GPE8_INP (0x00 << 16) | ||
624 | #define S3C2410_GPE8_OUTP (0x01 << 16) | ||
625 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) | 498 | #define S3C2410_GPE8_SDDAT1 (0x02 << 16) |
626 | #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) | 499 | #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) |
627 | #define S3C2443_GPE8_AC_SDO (0x03 << 16) | 500 | #define S3C2443_GPE8_AC_SDO (0x03 << 16) |
628 | #define S3C2400_GPE8_nXDACK0 (0x02 << 16) | 501 | #define S3C2400_GPE8_nXDACK0 (0x02 << 16) |
629 | 502 | ||
630 | #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) | 503 | #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) |
631 | #define S3C2410_GPE9_INP (0x00 << 18) | ||
632 | #define S3C2410_GPE9_OUTP (0x01 << 18) | ||
633 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) | 504 | #define S3C2410_GPE9_SDDAT2 (0x02 << 18) |
634 | #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) | 505 | #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) |
635 | #define S3C2443_GPE9_AC_SYNC (0x03 << 18) | 506 | #define S3C2443_GPE9_AC_SYNC (0x03 << 18) |
@@ -637,39 +508,27 @@ | |||
637 | #define S3C2400_GPE9_nXBACK (0x03 << 18) | 508 | #define S3C2400_GPE9_nXBACK (0x03 << 18) |
638 | 509 | ||
639 | #define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) | 510 | #define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) |
640 | #define S3C2410_GPE10_INP (0x00 << 20) | ||
641 | #define S3C2410_GPE10_OUTP (0x01 << 20) | ||
642 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) | 511 | #define S3C2410_GPE10_SDDAT3 (0x02 << 20) |
643 | #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) | 512 | #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) |
644 | #define S3C2443_GPE10_AC_nRESET (0x03 << 20) | 513 | #define S3C2443_GPE10_AC_nRESET (0x03 << 20) |
645 | #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) | 514 | #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) |
646 | 515 | ||
647 | #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) | 516 | #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) |
648 | #define S3C2410_GPE11_INP (0x00 << 22) | ||
649 | #define S3C2410_GPE11_OUTP (0x01 << 22) | ||
650 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) | 517 | #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) |
651 | #define S3C2400_GPE11_nXDREQ1 (0x02 << 22) | 518 | #define S3C2400_GPE11_nXDREQ1 (0x02 << 22) |
652 | #define S3C2400_GPE11_nXBREQ (0x03 << 22) | 519 | #define S3C2400_GPE11_nXBREQ (0x03 << 22) |
653 | 520 | ||
654 | #define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) | 521 | #define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) |
655 | #define S3C2410_GPE12_INP (0x00 << 24) | ||
656 | #define S3C2410_GPE12_OUTP (0x01 << 24) | ||
657 | #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) | 522 | #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) |
658 | 523 | ||
659 | #define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13) | 524 | #define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13) |
660 | #define S3C2410_GPE13_INP (0x00 << 26) | ||
661 | #define S3C2410_GPE13_OUTP (0x01 << 26) | ||
662 | #define S3C2410_GPE13_SPICLK0 (0x02 << 26) | 525 | #define S3C2410_GPE13_SPICLK0 (0x02 << 26) |
663 | 526 | ||
664 | #define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14) | 527 | #define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14) |
665 | #define S3C2410_GPE14_INP (0x00 << 28) | ||
666 | #define S3C2410_GPE14_OUTP (0x01 << 28) | ||
667 | #define S3C2410_GPE14_IICSCL (0x02 << 28) | 528 | #define S3C2410_GPE14_IICSCL (0x02 << 28) |
668 | #define S3C2410_GPE14_MASK (0x03 << 28) | 529 | #define S3C2410_GPE14_MASK (0x03 << 28) |
669 | 530 | ||
670 | #define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15) | 531 | #define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15) |
671 | #define S3C2410_GPE15_INP (0x00 << 30) | ||
672 | #define S3C2410_GPE15_OUTP (0x01 << 30) | ||
673 | #define S3C2410_GPE15_IICSDA (0x02 << 30) | 532 | #define S3C2410_GPE15_IICSDA (0x02 << 30) |
674 | #define S3C2410_GPE15_MASK (0x03 << 30) | 533 | #define S3C2410_GPE15_MASK (0x03 << 30) |
675 | 534 | ||
@@ -706,54 +565,38 @@ | |||
706 | #define S3C2400_GPFUP S3C2410_GPIOREG(0x40) | 565 | #define S3C2400_GPFUP S3C2410_GPIOREG(0x40) |
707 | 566 | ||
708 | #define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) | 567 | #define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) |
709 | #define S3C2410_GPF0_INP (0x00 << 0) | ||
710 | #define S3C2410_GPF0_OUTP (0x01 << 0) | ||
711 | #define S3C2410_GPF0_EINT0 (0x02 << 0) | 568 | #define S3C2410_GPF0_EINT0 (0x02 << 0) |
712 | #define S3C2400_GPF0_RXD0 (0x02 << 0) | 569 | #define S3C2400_GPF0_RXD0 (0x02 << 0) |
713 | 570 | ||
714 | #define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) | 571 | #define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) |
715 | #define S3C2410_GPF1_INP (0x00 << 2) | ||
716 | #define S3C2410_GPF1_OUTP (0x01 << 2) | ||
717 | #define S3C2410_GPF1_EINT1 (0x02 << 2) | 572 | #define S3C2410_GPF1_EINT1 (0x02 << 2) |
718 | #define S3C2400_GPF1_RXD1 (0x02 << 2) | 573 | #define S3C2400_GPF1_RXD1 (0x02 << 2) |
719 | #define S3C2400_GPF1_IICSDA (0x03 << 2) | 574 | #define S3C2400_GPF1_IICSDA (0x03 << 2) |
720 | 575 | ||
721 | #define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) | 576 | #define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) |
722 | #define S3C2410_GPF2_INP (0x00 << 4) | ||
723 | #define S3C2410_GPF2_OUTP (0x01 << 4) | ||
724 | #define S3C2410_GPF2_EINT2 (0x02 << 4) | 577 | #define S3C2410_GPF2_EINT2 (0x02 << 4) |
725 | #define S3C2400_GPF2_TXD0 (0x02 << 4) | 578 | #define S3C2400_GPF2_TXD0 (0x02 << 4) |
726 | 579 | ||
727 | #define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) | 580 | #define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) |
728 | #define S3C2410_GPF3_INP (0x00 << 6) | ||
729 | #define S3C2410_GPF3_OUTP (0x01 << 6) | ||
730 | #define S3C2410_GPF3_EINT3 (0x02 << 6) | 581 | #define S3C2410_GPF3_EINT3 (0x02 << 6) |
731 | #define S3C2400_GPF3_TXD1 (0x02 << 6) | 582 | #define S3C2400_GPF3_TXD1 (0x02 << 6) |
732 | #define S3C2400_GPF3_IICSCL (0x03 << 6) | 583 | #define S3C2400_GPF3_IICSCL (0x03 << 6) |
733 | 584 | ||
734 | #define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) | 585 | #define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) |
735 | #define S3C2410_GPF4_INP (0x00 << 8) | ||
736 | #define S3C2410_GPF4_OUTP (0x01 << 8) | ||
737 | #define S3C2410_GPF4_EINT4 (0x02 << 8) | 586 | #define S3C2410_GPF4_EINT4 (0x02 << 8) |
738 | #define S3C2400_GPF4_nRTS0 (0x02 << 8) | 587 | #define S3C2400_GPF4_nRTS0 (0x02 << 8) |
739 | #define S3C2400_GPF4_nXBACK (0x03 << 8) | 588 | #define S3C2400_GPF4_nXBACK (0x03 << 8) |
740 | 589 | ||
741 | #define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) | 590 | #define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) |
742 | #define S3C2410_GPF5_INP (0x00 << 10) | ||
743 | #define S3C2410_GPF5_OUTP (0x01 << 10) | ||
744 | #define S3C2410_GPF5_EINT5 (0x02 << 10) | 591 | #define S3C2410_GPF5_EINT5 (0x02 << 10) |
745 | #define S3C2400_GPF5_nCTS0 (0x02 << 10) | 592 | #define S3C2400_GPF5_nCTS0 (0x02 << 10) |
746 | #define S3C2400_GPF5_nXBREQ (0x03 << 10) | 593 | #define S3C2400_GPF5_nXBREQ (0x03 << 10) |
747 | 594 | ||
748 | #define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) | 595 | #define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) |
749 | #define S3C2410_GPF6_INP (0x00 << 12) | ||
750 | #define S3C2410_GPF6_OUTP (0x01 << 12) | ||
751 | #define S3C2410_GPF6_EINT6 (0x02 << 12) | 596 | #define S3C2410_GPF6_EINT6 (0x02 << 12) |
752 | #define S3C2400_GPF6_CLKOUT (0x02 << 12) | 597 | #define S3C2400_GPF6_CLKOUT (0x02 << 12) |
753 | 598 | ||
754 | #define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) | 599 | #define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) |
755 | #define S3C2410_GPF7_INP (0x00 << 14) | ||
756 | #define S3C2410_GPF7_OUTP (0x01 << 14) | ||
757 | #define S3C2410_GPF7_EINT7 (0x02 << 14) | 600 | #define S3C2410_GPF7_EINT7 (0x02 << 14) |
758 | 601 | ||
759 | #define S3C2410_GPF_PUPDIS(x) (1<<(x)) | 602 | #define S3C2410_GPF_PUPDIS(x) (1<<(x)) |
@@ -779,35 +622,25 @@ | |||
779 | #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) | 622 | #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) |
780 | 623 | ||
781 | #define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) | 624 | #define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) |
782 | #define S3C2410_GPG0_INP (0x00 << 0) | ||
783 | #define S3C2410_GPG0_OUTP (0x01 << 0) | ||
784 | #define S3C2410_GPG0_EINT8 (0x02 << 0) | 625 | #define S3C2410_GPG0_EINT8 (0x02 << 0) |
785 | #define S3C2400_GPG0_I2SLRCK (0x02 << 0) | 626 | #define S3C2400_GPG0_I2SLRCK (0x02 << 0) |
786 | 627 | ||
787 | #define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) | 628 | #define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) |
788 | #define S3C2410_GPG1_INP (0x00 << 2) | ||
789 | #define S3C2410_GPG1_OUTP (0x01 << 2) | ||
790 | #define S3C2410_GPG1_EINT9 (0x02 << 2) | 629 | #define S3C2410_GPG1_EINT9 (0x02 << 2) |
791 | #define S3C2400_GPG1_I2SSCLK (0x02 << 2) | 630 | #define S3C2400_GPG1_I2SSCLK (0x02 << 2) |
792 | 631 | ||
793 | #define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) | 632 | #define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) |
794 | #define S3C2410_GPG2_INP (0x00 << 4) | ||
795 | #define S3C2410_GPG2_OUTP (0x01 << 4) | ||
796 | #define S3C2410_GPG2_EINT10 (0x02 << 4) | 633 | #define S3C2410_GPG2_EINT10 (0x02 << 4) |
797 | #define S3C2410_GPG2_nSS0 (0x03 << 4) | 634 | #define S3C2410_GPG2_nSS0 (0x03 << 4) |
798 | #define S3C2400_GPG2_CDCLK (0x02 << 4) | 635 | #define S3C2400_GPG2_CDCLK (0x02 << 4) |
799 | 636 | ||
800 | #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) | 637 | #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) |
801 | #define S3C2410_GPG3_INP (0x00 << 6) | ||
802 | #define S3C2410_GPG3_OUTP (0x01 << 6) | ||
803 | #define S3C2410_GPG3_EINT11 (0x02 << 6) | 638 | #define S3C2410_GPG3_EINT11 (0x02 << 6) |
804 | #define S3C2410_GPG3_nSS1 (0x03 << 6) | 639 | #define S3C2410_GPG3_nSS1 (0x03 << 6) |
805 | #define S3C2400_GPG3_I2SSDO (0x02 << 6) | 640 | #define S3C2400_GPG3_I2SSDO (0x02 << 6) |
806 | #define S3C2400_GPG3_I2SSDI (0x03 << 6) | 641 | #define S3C2400_GPG3_I2SSDI (0x03 << 6) |
807 | 642 | ||
808 | #define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) | 643 | #define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) |
809 | #define S3C2410_GPG4_INP (0x00 << 8) | ||
810 | #define S3C2410_GPG4_OUTP (0x01 << 8) | ||
811 | #define S3C2410_GPG4_EINT12 (0x02 << 8) | 644 | #define S3C2410_GPG4_EINT12 (0x02 << 8) |
812 | #define S3C2400_GPG4_MMCCLK (0x02 << 8) | 645 | #define S3C2400_GPG4_MMCCLK (0x02 << 8) |
813 | #define S3C2400_GPG4_I2SSDI (0x03 << 8) | 646 | #define S3C2400_GPG4_I2SSDI (0x03 << 8) |
@@ -815,80 +648,58 @@ | |||
815 | #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) | 648 | #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) |
816 | 649 | ||
817 | #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) | 650 | #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) |
818 | #define S3C2410_GPG5_INP (0x00 << 10) | ||
819 | #define S3C2410_GPG5_OUTP (0x01 << 10) | ||
820 | #define S3C2410_GPG5_EINT13 (0x02 << 10) | 651 | #define S3C2410_GPG5_EINT13 (0x02 << 10) |
821 | #define S3C2400_GPG5_MMCCMD (0x02 << 10) | 652 | #define S3C2400_GPG5_MMCCMD (0x02 << 10) |
822 | #define S3C2400_GPG5_IICSDA (0x03 << 10) | 653 | #define S3C2400_GPG5_IICSDA (0x03 << 10) |
823 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ | 654 | #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ |
824 | 655 | ||
825 | #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) | 656 | #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) |
826 | #define S3C2410_GPG6_INP (0x00 << 12) | ||
827 | #define S3C2410_GPG6_OUTP (0x01 << 12) | ||
828 | #define S3C2410_GPG6_EINT14 (0x02 << 12) | 657 | #define S3C2410_GPG6_EINT14 (0x02 << 12) |
829 | #define S3C2400_GPG6_MMCDAT (0x02 << 12) | 658 | #define S3C2400_GPG6_MMCDAT (0x02 << 12) |
830 | #define S3C2400_GPG6_IICSCL (0x03 << 12) | 659 | #define S3C2400_GPG6_IICSCL (0x03 << 12) |
831 | #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) | 660 | #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) |
832 | 661 | ||
833 | #define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) | 662 | #define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) |
834 | #define S3C2410_GPG7_INP (0x00 << 14) | ||
835 | #define S3C2410_GPG7_OUTP (0x01 << 14) | ||
836 | #define S3C2410_GPG7_EINT15 (0x02 << 14) | 663 | #define S3C2410_GPG7_EINT15 (0x02 << 14) |
837 | #define S3C2410_GPG7_SPICLK1 (0x03 << 14) | 664 | #define S3C2410_GPG7_SPICLK1 (0x03 << 14) |
838 | #define S3C2400_GPG7_SPIMISO (0x02 << 14) | 665 | #define S3C2400_GPG7_SPIMISO (0x02 << 14) |
839 | #define S3C2400_GPG7_IICSDA (0x03 << 14) | 666 | #define S3C2400_GPG7_IICSDA (0x03 << 14) |
840 | 667 | ||
841 | #define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) | 668 | #define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) |
842 | #define S3C2410_GPG8_INP (0x00 << 16) | ||
843 | #define S3C2410_GPG8_OUTP (0x01 << 16) | ||
844 | #define S3C2410_GPG8_EINT16 (0x02 << 16) | 669 | #define S3C2410_GPG8_EINT16 (0x02 << 16) |
845 | #define S3C2400_GPG8_SPIMOSI (0x02 << 16) | 670 | #define S3C2400_GPG8_SPIMOSI (0x02 << 16) |
846 | #define S3C2400_GPG8_IICSCL (0x03 << 16) | 671 | #define S3C2400_GPG8_IICSCL (0x03 << 16) |
847 | 672 | ||
848 | #define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) | 673 | #define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) |
849 | #define S3C2410_GPG9_INP (0x00 << 18) | ||
850 | #define S3C2410_GPG9_OUTP (0x01 << 18) | ||
851 | #define S3C2410_GPG9_EINT17 (0x02 << 18) | 674 | #define S3C2410_GPG9_EINT17 (0x02 << 18) |
852 | #define S3C2400_GPG9_SPICLK (0x02 << 18) | 675 | #define S3C2400_GPG9_SPICLK (0x02 << 18) |
853 | #define S3C2400_GPG9_MMCCLK (0x03 << 18) | 676 | #define S3C2400_GPG9_MMCCLK (0x03 << 18) |
854 | 677 | ||
855 | #define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) | 678 | #define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) |
856 | #define S3C2410_GPG10_INP (0x00 << 20) | ||
857 | #define S3C2410_GPG10_OUTP (0x01 << 20) | ||
858 | #define S3C2410_GPG10_EINT18 (0x02 << 20) | 679 | #define S3C2410_GPG10_EINT18 (0x02 << 20) |
859 | 680 | ||
860 | #define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11) | 681 | #define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11) |
861 | #define S3C2410_GPG11_INP (0x00 << 22) | ||
862 | #define S3C2410_GPG11_OUTP (0x01 << 22) | ||
863 | #define S3C2410_GPG11_EINT19 (0x02 << 22) | 682 | #define S3C2410_GPG11_EINT19 (0x02 << 22) |
864 | #define S3C2410_GPG11_TCLK1 (0x03 << 22) | 683 | #define S3C2410_GPG11_TCLK1 (0x03 << 22) |
865 | #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) | 684 | #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) |
866 | 685 | ||
867 | #define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) | 686 | #define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) |
868 | #define S3C2410_GPG12_INP (0x00 << 24) | ||
869 | #define S3C2410_GPG12_OUTP (0x01 << 24) | ||
870 | #define S3C2410_GPG12_EINT20 (0x02 << 24) | 687 | #define S3C2410_GPG12_EINT20 (0x02 << 24) |
871 | #define S3C2410_GPG12_XMON (0x03 << 24) | 688 | #define S3C2410_GPG12_XMON (0x03 << 24) |
872 | #define S3C2442_GPG12_nSPICS0 (0x03 << 24) | 689 | #define S3C2442_GPG12_nSPICS0 (0x03 << 24) |
873 | #define S3C2443_GPG12_nINPACK (0x03 << 24) | 690 | #define S3C2443_GPG12_nINPACK (0x03 << 24) |
874 | 691 | ||
875 | #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) | 692 | #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) |
876 | #define S3C2410_GPG13_INP (0x00 << 26) | ||
877 | #define S3C2410_GPG13_OUTP (0x01 << 26) | ||
878 | #define S3C2410_GPG13_EINT21 (0x02 << 26) | 693 | #define S3C2410_GPG13_EINT21 (0x02 << 26) |
879 | #define S3C2410_GPG13_nXPON (0x03 << 26) | 694 | #define S3C2410_GPG13_nXPON (0x03 << 26) |
880 | #define S3C2443_GPG13_CF_nREG (0x03 << 26) | 695 | #define S3C2443_GPG13_CF_nREG (0x03 << 26) |
881 | 696 | ||
882 | #define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) | 697 | #define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) |
883 | #define S3C2410_GPG14_INP (0x00 << 28) | ||
884 | #define S3C2410_GPG14_OUTP (0x01 << 28) | ||
885 | #define S3C2410_GPG14_EINT22 (0x02 << 28) | 698 | #define S3C2410_GPG14_EINT22 (0x02 << 28) |
886 | #define S3C2410_GPG14_YMON (0x03 << 28) | 699 | #define S3C2410_GPG14_YMON (0x03 << 28) |
887 | #define S3C2443_GPG14_CF_RESET (0x03 << 28) | 700 | #define S3C2443_GPG14_CF_RESET (0x03 << 28) |
888 | 701 | ||
889 | #define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) | 702 | #define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) |
890 | #define S3C2410_GPG15_INP (0x00 << 30) | ||
891 | #define S3C2410_GPG15_OUTP (0x01 << 30) | ||
892 | #define S3C2410_GPG15_EINT23 (0x02 << 30) | 703 | #define S3C2410_GPG15_EINT23 (0x02 << 30) |
893 | #define S3C2410_GPG15_nYPON (0x03 << 30) | 704 | #define S3C2410_GPG15_nYPON (0x03 << 30) |
894 | #define S3C2443_GPG15_CF_PWR (0x03 << 30) | 705 | #define S3C2443_GPG15_CF_PWR (0x03 << 30) |
@@ -908,61 +719,39 @@ | |||
908 | #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) | 719 | #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) |
909 | 720 | ||
910 | #define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0) | 721 | #define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0) |
911 | #define S3C2410_GPH0_INP (0x00 << 0) | ||
912 | #define S3C2410_GPH0_OUTP (0x01 << 0) | ||
913 | #define S3C2410_GPH0_nCTS0 (0x02 << 0) | 722 | #define S3C2410_GPH0_nCTS0 (0x02 << 0) |
914 | 723 | ||
915 | #define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1) | 724 | #define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1) |
916 | #define S3C2410_GPH1_INP (0x00 << 2) | ||
917 | #define S3C2410_GPH1_OUTP (0x01 << 2) | ||
918 | #define S3C2410_GPH1_nRTS0 (0x02 << 2) | 725 | #define S3C2410_GPH1_nRTS0 (0x02 << 2) |
919 | 726 | ||
920 | #define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2) | 727 | #define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2) |
921 | #define S3C2410_GPH2_INP (0x00 << 4) | ||
922 | #define S3C2410_GPH2_OUTP (0x01 << 4) | ||
923 | #define S3C2410_GPH2_TXD0 (0x02 << 4) | 728 | #define S3C2410_GPH2_TXD0 (0x02 << 4) |
924 | 729 | ||
925 | #define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3) | 730 | #define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3) |
926 | #define S3C2410_GPH3_INP (0x00 << 6) | ||
927 | #define S3C2410_GPH3_OUTP (0x01 << 6) | ||
928 | #define S3C2410_GPH3_RXD0 (0x02 << 6) | 731 | #define S3C2410_GPH3_RXD0 (0x02 << 6) |
929 | 732 | ||
930 | #define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4) | 733 | #define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4) |
931 | #define S3C2410_GPH4_INP (0x00 << 8) | ||
932 | #define S3C2410_GPH4_OUTP (0x01 << 8) | ||
933 | #define S3C2410_GPH4_TXD1 (0x02 << 8) | 734 | #define S3C2410_GPH4_TXD1 (0x02 << 8) |
934 | 735 | ||
935 | #define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5) | 736 | #define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5) |
936 | #define S3C2410_GPH5_INP (0x00 << 10) | ||
937 | #define S3C2410_GPH5_OUTP (0x01 << 10) | ||
938 | #define S3C2410_GPH5_RXD1 (0x02 << 10) | 737 | #define S3C2410_GPH5_RXD1 (0x02 << 10) |
939 | 738 | ||
940 | #define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6) | 739 | #define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6) |
941 | #define S3C2410_GPH6_INP (0x00 << 12) | ||
942 | #define S3C2410_GPH6_OUTP (0x01 << 12) | ||
943 | #define S3C2410_GPH6_TXD2 (0x02 << 12) | 740 | #define S3C2410_GPH6_TXD2 (0x02 << 12) |
944 | #define S3C2410_GPH6_nRTS1 (0x03 << 12) | 741 | #define S3C2410_GPH6_nRTS1 (0x03 << 12) |
945 | 742 | ||
946 | #define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7) | 743 | #define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7) |
947 | #define S3C2410_GPH7_INP (0x00 << 14) | ||
948 | #define S3C2410_GPH7_OUTP (0x01 << 14) | ||
949 | #define S3C2410_GPH7_RXD2 (0x02 << 14) | 744 | #define S3C2410_GPH7_RXD2 (0x02 << 14) |
950 | #define S3C2410_GPH7_nCTS1 (0x03 << 14) | 745 | #define S3C2410_GPH7_nCTS1 (0x03 << 14) |
951 | 746 | ||
952 | #define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8) | 747 | #define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8) |
953 | #define S3C2410_GPH8_INP (0x00 << 16) | ||
954 | #define S3C2410_GPH8_OUTP (0x01 << 16) | ||
955 | #define S3C2410_GPH8_UCLK (0x02 << 16) | 748 | #define S3C2410_GPH8_UCLK (0x02 << 16) |
956 | 749 | ||
957 | #define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9) | 750 | #define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9) |
958 | #define S3C2410_GPH9_INP (0x00 << 18) | ||
959 | #define S3C2410_GPH9_OUTP (0x01 << 18) | ||
960 | #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) | 751 | #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) |
961 | #define S3C2442_GPH9_nSPICS0 (0x03 << 18) | 752 | #define S3C2442_GPH9_nSPICS0 (0x03 << 18) |
962 | 753 | ||
963 | #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) | 754 | #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) |
964 | #define S3C2410_GPH10_INP (0x00 << 20) | ||
965 | #define S3C2410_GPH10_OUTP (0x01 << 20) | ||
966 | #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) | 755 | #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) |
967 | 756 | ||
968 | /* The S3C2412 and S3C2413 move the GPJ register set to after | 757 | /* The S3C2412 and S3C2413 move the GPJ register set to after |