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authorSenthilvadivu Guruswamy <svadivu@ti.com>2011-02-22 02:50:36 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-02-23 02:19:06 -0500
commit996746ca127d722c279325552cdcc48b20079a61 (patch)
tree2eae38127314d9d62abf3d328e63c170c4c9254e
parent04aa67dec63b61c1a8b9b6d001262250f1a92130 (diff)
OMAP2420: hwmod data: add DSS DISPC RFBI VENC
Hwmod needs database of all IPs in a system. This patch generates the hwmod database for OMAP2420 Display Sub System,. Since DSS is also considered as an IP as DISPC, RFBI, name it as dss_core. Acked-by: Benoit Cousson <b-cousson@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c310
-rw-r--r--arch/arm/plat-omap/include/plat/l3_2xxx.h20
-rw-r--r--arch/arm/plat-omap/include/plat/l4_2xxx.h24
3 files changed, 354 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 7fffd340c76f..f323c6bb22de 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -19,6 +19,8 @@
19#include <plat/i2c.h> 19#include <plat/i2c.h>
20#include <plat/gpio.h> 20#include <plat/gpio.h>
21#include <plat/mcspi.h> 21#include <plat/mcspi.h>
22#include <plat/l3_2xxx.h>
23#include <plat/l4_2xxx.h>
22 24
23#include "omap_hwmod_common_data.h" 25#include "omap_hwmod_common_data.h"
24 26
@@ -39,6 +41,10 @@ static struct omap_hwmod omap2420_mpu_hwmod;
39static struct omap_hwmod omap2420_iva_hwmod; 41static struct omap_hwmod omap2420_iva_hwmod;
40static struct omap_hwmod omap2420_l3_main_hwmod; 42static struct omap_hwmod omap2420_l3_main_hwmod;
41static struct omap_hwmod omap2420_l4_core_hwmod; 43static struct omap_hwmod omap2420_l4_core_hwmod;
44static struct omap_hwmod omap2420_dss_core_hwmod;
45static struct omap_hwmod omap2420_dss_dispc_hwmod;
46static struct omap_hwmod omap2420_dss_rfbi_hwmod;
47static struct omap_hwmod omap2420_dss_venc_hwmod;
42static struct omap_hwmod omap2420_wd_timer2_hwmod; 48static struct omap_hwmod omap2420_wd_timer2_hwmod;
43static struct omap_hwmod omap2420_gpio1_hwmod; 49static struct omap_hwmod omap2420_gpio1_hwmod;
44static struct omap_hwmod omap2420_gpio2_hwmod; 50static struct omap_hwmod omap2420_gpio2_hwmod;
@@ -67,6 +73,19 @@ static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
67 &omap2420_mpu__l3_main, 73 &omap2420_mpu__l3_main,
68}; 74};
69 75
76/* DSS -> l3 */
77static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
78 .master = &omap2420_dss_core_hwmod,
79 .slave = &omap2420_l3_main_hwmod,
80 .fw = {
81 .omap2 = {
82 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
83 .flags = OMAP_FIREWALL_L3,
84 }
85 },
86 .user = OCP_USER_MPU | OCP_USER_SDMA,
87};
88
70/* Master interfaces on the L3 interconnect */ 89/* Master interfaces on the L3 interconnect */
71static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { 90static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
72 &omap2420_l3_main__l4_core, 91 &omap2420_l3_main__l4_core,
@@ -509,6 +528,291 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 528 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
510}; 529};
511 530
531/*
532 * 'dss' class
533 * display sub-system
534 */
535
536static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
537 .rev_offs = 0x0000,
538 .sysc_offs = 0x0010,
539 .syss_offs = 0x0014,
540 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
541 .sysc_fields = &omap_hwmod_sysc_type1,
542};
543
544static struct omap_hwmod_class omap2420_dss_hwmod_class = {
545 .name = "dss",
546 .sysc = &omap2420_dss_sysc,
547};
548
549/* dss */
550static struct omap_hwmod_irq_info omap2420_dss_irqs[] = {
551 { .irq = 25 },
552};
553
554static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
555 { .name = "dispc", .dma_req = 5 },
556};
557
558/* dss */
559/* dss master ports */
560static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
561 &omap2420_dss__l3,
562};
563
564static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
565 {
566 .pa_start = 0x48050000,
567 .pa_end = 0x480503FF,
568 .flags = ADDR_TYPE_RT
569 },
570};
571
572/* l4_core -> dss */
573static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
574 .master = &omap2420_l4_core_hwmod,
575 .slave = &omap2420_dss_core_hwmod,
576 .clk = "dss_ick",
577 .addr = omap2420_dss_addrs,
578 .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs),
579 .fw = {
580 .omap2 = {
581 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
582 .flags = OMAP_FIREWALL_L4,
583 }
584 },
585 .user = OCP_USER_MPU | OCP_USER_SDMA,
586};
587
588/* dss slave ports */
589static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
590 &omap2420_l4_core__dss,
591};
592
593static struct omap_hwmod_opt_clk dss_opt_clks[] = {
594 { .role = "tv_clk", .clk = "dss_54m_fck" },
595 { .role = "sys_clk", .clk = "dss2_fck" },
596};
597
598static struct omap_hwmod omap2420_dss_core_hwmod = {
599 .name = "dss_core",
600 .class = &omap2420_dss_hwmod_class,
601 .main_clk = "dss1_fck", /* instead of dss_fck */
602 .mpu_irqs = omap2420_dss_irqs,
603 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dss_irqs),
604 .sdma_reqs = omap2420_dss_sdma_chs,
605 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs),
606 .prcm = {
607 .omap2 = {
608 .prcm_reg_id = 1,
609 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
610 .module_offs = CORE_MOD,
611 .idlest_reg_id = 1,
612 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
613 },
614 },
615 .opt_clks = dss_opt_clks,
616 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
617 .slaves = omap2420_dss_slaves,
618 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
619 .masters = omap2420_dss_masters,
620 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
621 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
622 .flags = HWMOD_NO_IDLEST,
623};
624
625/*
626 * 'dispc' class
627 * display controller
628 */
629
630static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
631 .rev_offs = 0x0000,
632 .sysc_offs = 0x0010,
633 .syss_offs = 0x0014,
634 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
635 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
636 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
637 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
638 .sysc_fields = &omap_hwmod_sysc_type1,
639};
640
641static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
642 .name = "dispc",
643 .sysc = &omap2420_dispc_sysc,
644};
645
646static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
647 {
648 .pa_start = 0x48050400,
649 .pa_end = 0x480507FF,
650 .flags = ADDR_TYPE_RT
651 },
652};
653
654/* l4_core -> dss_dispc */
655static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
656 .master = &omap2420_l4_core_hwmod,
657 .slave = &omap2420_dss_dispc_hwmod,
658 .clk = "dss_ick",
659 .addr = omap2420_dss_dispc_addrs,
660 .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs),
661 .fw = {
662 .omap2 = {
663 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
664 .flags = OMAP_FIREWALL_L4,
665 }
666 },
667 .user = OCP_USER_MPU | OCP_USER_SDMA,
668};
669
670/* dss_dispc slave ports */
671static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
672 &omap2420_l4_core__dss_dispc,
673};
674
675static struct omap_hwmod omap2420_dss_dispc_hwmod = {
676 .name = "dss_dispc",
677 .class = &omap2420_dispc_hwmod_class,
678 .main_clk = "dss1_fck",
679 .prcm = {
680 .omap2 = {
681 .prcm_reg_id = 1,
682 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
683 .module_offs = CORE_MOD,
684 .idlest_reg_id = 1,
685 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
686 },
687 },
688 .slaves = omap2420_dss_dispc_slaves,
689 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
690 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
691 .flags = HWMOD_NO_IDLEST,
692};
693
694/*
695 * 'rfbi' class
696 * remote frame buffer interface
697 */
698
699static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
700 .rev_offs = 0x0000,
701 .sysc_offs = 0x0010,
702 .syss_offs = 0x0014,
703 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
704 SYSC_HAS_AUTOIDLE),
705 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
706 .sysc_fields = &omap_hwmod_sysc_type1,
707};
708
709static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
710 .name = "rfbi",
711 .sysc = &omap2420_rfbi_sysc,
712};
713
714static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
715 {
716 .pa_start = 0x48050800,
717 .pa_end = 0x48050BFF,
718 .flags = ADDR_TYPE_RT
719 },
720};
721
722/* l4_core -> dss_rfbi */
723static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
724 .master = &omap2420_l4_core_hwmod,
725 .slave = &omap2420_dss_rfbi_hwmod,
726 .clk = "dss_ick",
727 .addr = omap2420_dss_rfbi_addrs,
728 .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
729 .fw = {
730 .omap2 = {
731 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
732 .flags = OMAP_FIREWALL_L4,
733 }
734 },
735 .user = OCP_USER_MPU | OCP_USER_SDMA,
736};
737
738/* dss_rfbi slave ports */
739static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
740 &omap2420_l4_core__dss_rfbi,
741};
742
743static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
744 .name = "dss_rfbi",
745 .class = &omap2420_rfbi_hwmod_class,
746 .main_clk = "dss1_fck",
747 .prcm = {
748 .omap2 = {
749 .prcm_reg_id = 1,
750 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
751 .module_offs = CORE_MOD,
752 },
753 },
754 .slaves = omap2420_dss_rfbi_slaves,
755 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
756 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
757 .flags = HWMOD_NO_IDLEST,
758};
759
760/*
761 * 'venc' class
762 * video encoder
763 */
764
765static struct omap_hwmod_class omap2420_venc_hwmod_class = {
766 .name = "venc",
767};
768
769/* dss_venc */
770static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
771 {
772 .pa_start = 0x48050C00,
773 .pa_end = 0x48050FFF,
774 .flags = ADDR_TYPE_RT
775 },
776};
777
778/* l4_core -> dss_venc */
779static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
780 .master = &omap2420_l4_core_hwmod,
781 .slave = &omap2420_dss_venc_hwmod,
782 .clk = "dss_54m_fck",
783 .addr = omap2420_dss_venc_addrs,
784 .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs),
785 .fw = {
786 .omap2 = {
787 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
788 .flags = OMAP_FIREWALL_L4,
789 }
790 },
791 .user = OCP_USER_MPU | OCP_USER_SDMA,
792};
793
794/* dss_venc slave ports */
795static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
796 &omap2420_l4_core__dss_venc,
797};
798
799static struct omap_hwmod omap2420_dss_venc_hwmod = {
800 .name = "dss_venc",
801 .class = &omap2420_venc_hwmod_class,
802 .main_clk = "dss1_fck",
803 .prcm = {
804 .omap2 = {
805 .prcm_reg_id = 1,
806 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
807 .module_offs = CORE_MOD,
808 },
809 },
810 .slaves = omap2420_dss_venc_slaves,
811 .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves),
812 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
813 .flags = HWMOD_NO_IDLEST,
814};
815
512/* I2C common */ 816/* I2C common */
513static struct omap_hwmod_class_sysconfig i2c_sysc = { 817static struct omap_hwmod_class_sysconfig i2c_sysc = {
514 .rev_offs = 0x00, 818 .rev_offs = 0x00,
@@ -1026,6 +1330,12 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1026 &omap2420_uart1_hwmod, 1330 &omap2420_uart1_hwmod,
1027 &omap2420_uart2_hwmod, 1331 &omap2420_uart2_hwmod,
1028 &omap2420_uart3_hwmod, 1332 &omap2420_uart3_hwmod,
1333 /* dss class */
1334 &omap2420_dss_core_hwmod,
1335 &omap2420_dss_dispc_hwmod,
1336 &omap2420_dss_rfbi_hwmod,
1337 &omap2420_dss_venc_hwmod,
1338 /* i2c class */
1029 &omap2420_i2c1_hwmod, 1339 &omap2420_i2c1_hwmod,
1030 &omap2420_i2c2_hwmod, 1340 &omap2420_i2c2_hwmod,
1031 1341
diff --git a/arch/arm/plat-omap/include/plat/l3_2xxx.h b/arch/arm/plat-omap/include/plat/l3_2xxx.h
new file mode 100644
index 000000000000..b8b5641379b0
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l3_2xxx.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Sumit Semwal
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
14#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H
15
16/* L3 CONNIDs */
17/* Display Sub system (DSS) */
18#define OMAP2_L3_CORE_FW_CONNID_DSS 8
19
20#endif
diff --git a/arch/arm/plat-omap/include/plat/l4_2xxx.h b/arch/arm/plat-omap/include/plat/l4_2xxx.h
new file mode 100644
index 000000000000..3f39cf8a35c6
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l4_2xxx.h
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Sumit Semwal
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
14#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H
15
16/* L4 CORE */
17/* Display Sub system (DSS) */
18#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28
19#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29
20#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30
21#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31
22#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32
23
24#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 23:56:48 -0500