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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2005-06-19 14:26:54 -0400
committerRussell King <rmk@dyn-67.arm.linux.org.uk>2005-06-19 14:26:54 -0400
commitea4423c3b6c1dbd116c91be876b3ad07067c77c8 (patch)
treed4132a9ffc173be69b2e7abf0b52a52eb61bffcc
parent36c5ed23b9f535d1c79986efb45f9c1f115e0997 (diff)
parentfe6ef2daa29df8fef1a95446faccd18ab163993e (diff)
Merge with ../linux-2.6-smp
-rw-r--r--arch/arm/kernel/head.S44
-rw-r--r--arch/arm/kernel/smp.c107
-rw-r--r--arch/arm/mach-integrator/Makefile1
-rw-r--r--arch/arm/mach-integrator/core.c20
-rw-r--r--arch/arm/mach-integrator/headsmp.S37
-rw-r--r--arch/arm/mach-integrator/leds.c4
-rw-r--r--arch/arm/mach-integrator/platsmp.c192
-rw-r--r--include/asm-arm/arch-integrator/smp.h19
-rw-r--r--include/asm-arm/smp.h14
9 files changed, 436 insertions, 2 deletions
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 4733877296d4..bd4823c74645 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -2,6 +2,8 @@
2 * linux/arch/arm/kernel/head.S 2 * linux/arch/arm/kernel/head.S
3 * 3 *
4 * Copyright (C) 1994-2002 Russell King 4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
6 * All Rights Reserved
5 * 7 *
6 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -165,6 +167,48 @@ __mmap_switched:
165 stmia r6, {r0, r4} @ Save control register values 167 stmia r6, {r0, r4} @ Save control register values
166 b start_kernel 168 b start_kernel
167 169
170#if defined(CONFIG_SMP)
171 .type secondary_startup, #function
172ENTRY(secondary_startup)
173 /*
174 * Common entry point for secondary CPUs.
175 *
176 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
177 * the processor type - there is no need to check the machine type
178 * as it has already been validated by the primary processor.
179 */
180 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
181 bl __lookup_processor_type
182 movs r10, r5 @ invalid processor?
183 moveq r0, #'p' @ yes, error 'p'
184 beq __error
185
186 /*
187 * Use the page tables supplied from __cpu_up.
188 */
189 adr r4, __secondary_data
190 ldmia r4, {r5, r6, r13} @ address to jump to after
191 sub r4, r4, r5 @ mmu has been enabled
192 ldr r4, [r6, r4] @ get secondary_data.pgdir
193 adr lr, __enable_mmu @ return address
194 add pc, r10, #12 @ initialise processor
195 @ (return control reg)
196
197 /*
198 * r6 = &secondary_data
199 */
200ENTRY(__secondary_switched)
201 ldr sp, [r6, #4] @ get secondary_data.stack
202 mov fp, #0
203 b secondary_start_kernel
204
205 .type __secondary_data, %object
206__secondary_data:
207 .long .
208 .long secondary_data
209 .long __secondary_switched
210#endif /* defined(CONFIG_SMP) */
211
168 212
169 213
170/* 214/*
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ecc8c3332408..45ed036336e0 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -24,6 +24,9 @@
24#include <asm/atomic.h> 24#include <asm/atomic.h>
25#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
26#include <asm/cpu.h> 26#include <asm/cpu.h>
27#include <asm/mmu_context.h>
28#include <asm/pgtable.h>
29#include <asm/pgalloc.h>
27#include <asm/processor.h> 30#include <asm/processor.h>
28#include <asm/tlbflush.h> 31#include <asm/tlbflush.h>
29#include <asm/ptrace.h> 32#include <asm/ptrace.h>
@@ -37,6 +40,13 @@ cpumask_t cpu_present_mask;
37cpumask_t cpu_online_map; 40cpumask_t cpu_online_map;
38 41
39/* 42/*
43 * as from 2.5, kernels no longer have an init_tasks structure
44 * so we need some other way of telling a new secondary core
45 * where to place its SVC stack
46 */
47struct secondary_data secondary_data;
48
49/*
40 * structures for inter-processor calls 50 * structures for inter-processor calls
41 * - A collection of single bit ipi messages. 51 * - A collection of single bit ipi messages.
42 */ 52 */
@@ -71,6 +81,8 @@ static DEFINE_SPINLOCK(smp_call_function_lock);
71int __init __cpu_up(unsigned int cpu) 81int __init __cpu_up(unsigned int cpu)
72{ 82{
73 struct task_struct *idle; 83 struct task_struct *idle;
84 pgd_t *pgd;
85 pmd_t *pmd;
74 int ret; 86 int ret;
75 87
76 /* 88 /*
@@ -84,9 +96,54 @@ int __init __cpu_up(unsigned int cpu)
84 } 96 }
85 97
86 /* 98 /*
99 * Allocate initial page tables to allow the new CPU to
100 * enable the MMU safely. This essentially means a set
101 * of our "standard" page tables, with the addition of
102 * a 1:1 mapping for the physical address of the kernel.
103 */
104 pgd = pgd_alloc(&init_mm);
105 pmd = pmd_offset(pgd, PHYS_OFFSET);
106 *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) |
107 PMD_TYPE_SECT | PMD_SECT_AP_WRITE);
108
109 /*
110 * We need to tell the secondary core where to find
111 * its stack and the page tables.
112 */
113 secondary_data.stack = (void *)idle->thread_info + THREAD_SIZE - 8;
114 secondary_data.pgdir = virt_to_phys(pgd);
115 wmb();
116
117 /*
87 * Now bring the CPU into our world. 118 * Now bring the CPU into our world.
88 */ 119 */
89 ret = boot_secondary(cpu, idle); 120 ret = boot_secondary(cpu, idle);
121 if (ret == 0) {
122 unsigned long timeout;
123
124 /*
125 * CPU was successfully started, wait for it
126 * to come online or time out.
127 */
128 timeout = jiffies + HZ;
129 while (time_before(jiffies, timeout)) {
130 if (cpu_online(cpu))
131 break;
132
133 udelay(10);
134 barrier();
135 }
136
137 if (!cpu_online(cpu))
138 ret = -EIO;
139 }
140
141 secondary_data.stack = 0;
142 secondary_data.pgdir = 0;
143
144 *pmd_offset(pgd, PHYS_OFFSET) = __pmd(0);
145 pgd_free(pgd);
146
90 if (ret) { 147 if (ret) {
91 printk(KERN_CRIT "cpu_up: processor %d failed to boot\n", cpu); 148 printk(KERN_CRIT "cpu_up: processor %d failed to boot\n", cpu);
92 /* 149 /*
@@ -98,6 +155,56 @@ int __init __cpu_up(unsigned int cpu)
98} 155}
99 156
100/* 157/*
158 * This is the secondary CPU boot entry. We're using this CPUs
159 * idle thread stack, but a set of temporary page tables.
160 */
161asmlinkage void __init secondary_start_kernel(void)
162{
163 struct mm_struct *mm = &init_mm;
164 unsigned int cpu = smp_processor_id();
165
166 printk("CPU%u: Booted secondary processor\n", cpu);
167
168 /*
169 * All kernel threads share the same mm context; grab a
170 * reference and switch to it.
171 */
172 atomic_inc(&mm->mm_users);
173 atomic_inc(&mm->mm_count);
174 current->active_mm = mm;
175 cpu_set(cpu, mm->cpu_vm_mask);
176 cpu_switch_mm(mm->pgd, mm);
177 enter_lazy_tlb(mm, current);
178
179 cpu_init();
180
181 /*
182 * Give the platform a chance to do its own initialisation.
183 */
184 platform_secondary_init(cpu);
185
186 /*
187 * Enable local interrupts.
188 */
189 local_irq_enable();
190 local_fiq_enable();
191
192 calibrate_delay();
193
194 smp_store_cpu_info(cpu);
195
196 /*
197 * OK, now it's safe to let the boot CPU continue
198 */
199 cpu_set(cpu, cpu_online_map);
200
201 /*
202 * OK, it's off to the idle thread for us
203 */
204 cpu_idle();
205}
206
207/*
101 * Called by both boot and secondaries to move global data into 208 * Called by both boot and secondaries to move global data into
102 * per-processor storage. 209 * per-processor storage.
103 */ 210 */
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index 158daaf9e3b0..ebb255bdce8a 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_LEDS) += leds.o
12obj-$(CONFIG_PCI) += pci_v3.o pci.o 12obj-$(CONFIG_PCI) += pci_v3.o pci.o
13obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o 13obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o
14obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o 14obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o
15obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index bd17b5154311..d302f0405fd2 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -14,6 +14,7 @@
14#include <linux/spinlock.h> 14#include <linux/spinlock.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/sched.h> 16#include <linux/sched.h>
17#include <linux/smp.h>
17 18
18#include <asm/hardware.h> 19#include <asm/hardware.h>
19#include <asm/irq.h> 20#include <asm/irq.h>
@@ -221,7 +222,24 @@ integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
221 */ 222 */
222 timer1->TimerClear = 1; 223 timer1->TimerClear = 1;
223 224
224 timer_tick(regs); 225 /*
226 * the clock tick routines are only processed on the
227 * primary CPU
228 */
229 if (hard_smp_processor_id() == 0) {
230 nmi_tick();
231 timer_tick(regs);
232#ifdef CONFIG_SMP
233 smp_send_timer();
234#endif
235 }
236
237#ifdef CONFIG_SMP
238 /*
239 * this is the ARM equivalent of the APIC timer interrupt
240 */
241 update_process_times(user_mode(regs));
242#endif /* CONFIG_SMP */
225 243
226 write_sequnlock(&xtime_lock); 244 write_sequnlock(&xtime_lock);
227 245
diff --git a/arch/arm/mach-integrator/headsmp.S b/arch/arm/mach-integrator/headsmp.S
new file mode 100644
index 000000000000..ceaa88e30d70
--- /dev/null
+++ b/arch/arm/mach-integrator/headsmp.S
@@ -0,0 +1,37 @@
1/*
2 * linux/arch/arm/mach-integrator/headsmp.S
3 *
4 * Copyright (c) 2003 ARM Limited
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/linkage.h>
12#include <linux/init.h>
13
14 __INIT
15
16/*
17 * Integrator specific entry point for secondary CPUs. This provides
18 * a "holding pen" into which all secondary cores are held until we're
19 * ready for them to initialise.
20 */
21ENTRY(integrator_secondary_startup)
22 adr r4, 1f
23 ldmia r4, {r5, r6}
24 sub r4, r4, r5
25 ldr r6, [r6, r4]
26pen: ldr r7, [r6]
27 cmp r7, r0
28 bne pen
29
30 /*
31 * we've been released from the holding pen: secondary_stack
32 * should now contain the SVC stack for this core
33 */
34 b secondary_startup
35
361: .long .
37 .long phys_pen_release
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index d2c0ab21150c..f1436e683b49 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -22,6 +22,8 @@
22 */ 22 */
23#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/smp.h>
26#include <linux/spinlock.h>
25 27
26#include <asm/hardware.h> 28#include <asm/hardware.h>
27#include <asm/io.h> 29#include <asm/io.h>
@@ -85,4 +87,4 @@ static int __init leds_init(void)
85 return 0; 87 return 0;
86} 88}
87 89
88__initcall(leds_init); 90core_initcall(leds_init);
diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c
new file mode 100644
index 000000000000..ead15dfcb53d
--- /dev/null
+++ b/arch/arm/mach-integrator/platsmp.c
@@ -0,0 +1,192 @@
1/*
2 * linux/arch/arm/mach-cintegrator/platsmp.c
3 *
4 * Copyright (C) 2002 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/errno.h>
15#include <linux/mm.h>
16
17#include <asm/atomic.h>
18#include <asm/delay.h>
19#include <asm/mmu_context.h>
20#include <asm/procinfo.h>
21#include <asm/ptrace.h>
22#include <asm/smp.h>
23
24extern void integrator_secondary_startup(void);
25
26/*
27 * control for which core is the next to come out of the secondary
28 * boot "holding pen"
29 */
30volatile int __initdata pen_release = -1;
31unsigned long __initdata phys_pen_release = 0;
32
33static DEFINE_SPINLOCK(boot_lock);
34
35void __init platform_secondary_init(unsigned int cpu)
36{
37 /*
38 * the primary core may have used a "cross call" soft interrupt
39 * to get this processor out of WFI in the BootMonitor - make
40 * sure that we are no longer being sent this soft interrupt
41 */
42 smp_cross_call_done(cpumask_of_cpu(cpu));
43
44 /*
45 * if any interrupts are already enabled for the primary
46 * core (e.g. timer irq), then they will not have been enabled
47 * for us: do so
48 */
49 secondary_scan_irqs();
50
51 /*
52 * let the primary processor know we're out of the
53 * pen, then head off into the C entry point
54 */
55 pen_release = -1;
56
57 /*
58 * Synchronise with the boot thread.
59 */
60 spin_lock(&boot_lock);
61 spin_unlock(&boot_lock);
62}
63
64int __init boot_secondary(unsigned int cpu, struct task_struct *idle)
65{
66 unsigned long timeout;
67
68 /*
69 * set synchronisation state between this boot processor
70 * and the secondary one
71 */
72 spin_lock(&boot_lock);
73
74 /*
75 * The secondary processor is waiting to be released from
76 * the holding pen - release it, then wait for it to flag
77 * that it has been released by resetting pen_release.
78 *
79 * Note that "pen_release" is the hardware CPU ID, whereas
80 * "cpu" is Linux's internal ID.
81 */
82 pen_release = cpu;
83
84 /*
85 * XXX
86 *
87 * This is a later addition to the booting protocol: the
88 * bootMonitor now puts secondary cores into WFI, so
89 * poke_milo() no longer gets the cores moving; we need
90 * to send a soft interrupt to wake the secondary core.
91 * Use smp_cross_call() for this, since there's little
92 * point duplicating the code here
93 */
94 smp_cross_call(cpumask_of_cpu(cpu));
95
96 timeout = jiffies + (1 * HZ);
97 while (time_before(jiffies, timeout)) {
98 if (pen_release == -1)
99 break;
100
101 udelay(10);
102 }
103
104 /*
105 * now the secondary core is starting up let it run its
106 * calibrations, then wait for it to finish
107 */
108 spin_unlock(&boot_lock);
109
110 return pen_release != -1 ? -ENOSYS : 0;
111}
112
113static void __init poke_milo(void)
114{
115 extern void secondary_startup(void);
116
117 /* nobody is to be released from the pen yet */
118 pen_release = -1;
119
120 phys_pen_release = virt_to_phys(&pen_release);
121
122 /*
123 * write the address of secondary startup into the system-wide
124 * flags register, then clear the bottom two bits, which is what
125 * BootMonitor is waiting for
126 */
127#if 1
128#define CINTEGRATOR_HDR_FLAGSS_OFFSET 0x30
129 __raw_writel(virt_to_phys(integrator_secondary_startup),
130 (IO_ADDRESS(INTEGRATOR_HDR_BASE) +
131 CINTEGRATOR_HDR_FLAGSS_OFFSET));
132#define CINTEGRATOR_HDR_FLAGSC_OFFSET 0x34
133 __raw_writel(3,
134 (IO_ADDRESS(INTEGRATOR_HDR_BASE) +
135 CINTEGRATOR_HDR_FLAGSC_OFFSET));
136#endif
137
138 mb();
139}
140
141void __init smp_prepare_cpus(unsigned int max_cpus)
142{
143 unsigned int ncores = get_core_count();
144 unsigned int cpu = smp_processor_id();
145 int i;
146
147 /* sanity check */
148 if (ncores == 0) {
149 printk(KERN_ERR
150 "Integrator/CP: strange CM count of 0? Default to 1\n");
151
152 ncores = 1;
153 }
154
155 if (ncores > NR_CPUS) {
156 printk(KERN_WARNING
157 "Integrator/CP: no. of cores (%d) greater than configured "
158 "maximum of %d - clipping\n",
159 ncores, NR_CPUS);
160 ncores = NR_CPUS;
161 }
162
163 /*
164 * start with some more config for the Boot CPU, now that
165 * the world is a bit more alive (which was not the case
166 * when smp_prepare_boot_cpu() was called)
167 */
168 smp_store_cpu_info(cpu);
169
170 /*
171 * are we trying to boot more cores than exist?
172 */
173 if (max_cpus > ncores)
174 max_cpus = ncores;
175
176 /*
177 * Initialise the present mask - this tells us which CPUs should
178 * be present.
179 */
180 for (i = 0; i < max_cpus; i++) {
181 cpu_set(i, cpu_present_mask);
182 }
183
184 /*
185 * Do we need any more CPUs? If so, then let them know where
186 * to start. Note that, on modern versions of MILO, the "poke"
187 * doesn't actually do anything until each individual core is
188 * sent a soft interrupt to get it out of WFI
189 */
190 if (max_cpus > 1)
191 poke_milo();
192}
diff --git a/include/asm-arm/arch-integrator/smp.h b/include/asm-arm/arch-integrator/smp.h
new file mode 100644
index 000000000000..0ec7093f7c37
--- /dev/null
+++ b/include/asm-arm/arch-integrator/smp.h
@@ -0,0 +1,19 @@
1#ifndef ASMARM_ARCH_SMP_H
2#define ASMARM_ARCH_SMP_H
3
4#include <linux/config.h>
5
6#include <asm/arch/hardware.h>
7#include <asm/io.h>
8
9#define hard_smp_processor_id() \
10 ({ \
11 unsigned int cpunum; \
12 __asm__("mrc p15, 0, %0, c0, c0, 5" \
13 : "=r" (cpunum)); \
14 cpunum &= 0x0F; \
15 })
16
17extern void secondary_scan_irqs(void);
18
19#endif
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index f21fd8f6bcdd..bd44f894690f 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -55,4 +55,18 @@ extern void smp_cross_call(cpumask_t callmap);
55 */ 55 */
56extern int boot_secondary(unsigned int cpu, struct task_struct *); 56extern int boot_secondary(unsigned int cpu, struct task_struct *);
57 57
58/*
59 * Perform platform specific initialisation of the specified CPU.
60 */
61extern void platform_secondary_init(unsigned int cpu);
62
63/*
64 * Initial data for bringing up a secondary CPU.
65 */
66struct secondary_data {
67 unsigned long pgdir;
68 void *stack;
69};
70extern struct secondary_data secondary_data;
71
58#endif /* ifndef __ASM_ARM_SMP_H */ 72#endif /* ifndef __ASM_ARM_SMP_H */