aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-12-07 14:00:31 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-12-07 14:00:31 -0500
commite17587b5b90da78f56c7a948e54dbac3dc791f31 (patch)
tree60228100507c7c6509188d9f3ee7bd43947c718d
parent29ac0052ea454871273a1fc7ef09a97f3c214ee6 (diff)
parent5998a3cf327c90d0a7116eca72c0d2df2be8ecfd (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/hskinnemoen/avr32-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/hskinnemoen/avr32-2.6: [AVR32] Fix wrong pt_regs in critical exception handler [AVR32] Fix copy_to_user_page() breakage [AVR32] Follow the rules when dealing with the OCD system [AVR32] Clean up OCD register usage [AVR32] Implement irqflags trace and lockdep support [AVR32] Implement stacktrace support [AVR32] Kconfig: Use def_bool instead of bool + default [AVR32] Fix invalid status register bit definitions in asm/ptrace.h [AVR32] Add TIF_RESTORE_SIGMASK to the work masks
Diffstat
-rw-r--r--arch/avr32/Kconfig65
-rw-r--r--arch/avr32/kernel/Makefile1
-rw-r--r--arch/avr32/kernel/asm-offsets.c2
-rw-r--r--arch/avr32/kernel/entry-avr32b.S285
-rw-r--r--arch/avr32/kernel/kprobes.c14
-rw-r--r--arch/avr32/kernel/process.c9
-rw-r--r--arch/avr32/kernel/ptrace.c273
-rw-r--r--arch/avr32/kernel/stacktrace.c53
-rw-r--r--arch/avr32/kernel/traps.c2
-rw-r--r--arch/avr32/kernel/vmlinux.lds.S2
-rw-r--r--arch/avr32/mm/cache.c20
-rw-r--r--include/asm-avr32/cacheflush.h19
-rw-r--r--include/asm-avr32/ocd.h592
-rw-r--r--include/asm-avr32/processor.h3
-rw-r--r--include/asm-avr32/ptrace.h6
-rw-r--r--include/asm-avr32/sysreg.h2
-rw-r--r--include/asm-avr32/system.h4
-rw-r--r--include/asm-avr32/thread_info.h25
18 files changed, 1006 insertions, 371 deletions
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index 4f402c924504..b77abce10c7a 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -6,8 +6,7 @@
6mainmenu "Linux Kernel Configuration" 6mainmenu "Linux Kernel Configuration"
7 7
8config AVR32 8config AVR32
9 bool 9 def_bool y
10 default y
11 # With EMBEDDED=n, we get lots of stuff automatically selected 10 # With EMBEDDED=n, we get lots of stuff automatically selected
12 # that we usually don't need on AVR32. 11 # that we usually don't need on AVR32.
13 select EMBEDDED 12 select EMBEDDED
@@ -20,51 +19,49 @@ config AVR32
20 http://avr32linux.org/. 19 http://avr32linux.org/.
21 20
22config GENERIC_GPIO 21config GENERIC_GPIO
23 bool 22 def_bool y
24 default y
25 23
26config GENERIC_HARDIRQS 24config GENERIC_HARDIRQS
27 bool 25 def_bool y
28 default y 26
27config STACKTRACE_SUPPORT
28 def_bool y
29
30config LOCKDEP_SUPPORT
31 def_bool y
32
33config TRACE_IRQFLAGS_SUPPORT
34 def_bool y
29 35
30config HARDIRQS_SW_RESEND 36config HARDIRQS_SW_RESEND
31 bool 37 def_bool y
32 default y
33 38
34config GENERIC_IRQ_PROBE 39config GENERIC_IRQ_PROBE
35 bool 40 def_bool y
36 default y
37 41
38config RWSEM_GENERIC_SPINLOCK 42config RWSEM_GENERIC_SPINLOCK
39 bool 43 def_bool y
40 default y
41 44
42config GENERIC_TIME 45config GENERIC_TIME
43 bool 46 def_bool y
44 default y
45 47
46config RWSEM_XCHGADD_ALGORITHM 48config RWSEM_XCHGADD_ALGORITHM
47 bool 49 def_bool n
48 50
49config ARCH_HAS_ILOG2_U32 51config ARCH_HAS_ILOG2_U32
50 bool 52 def_bool n
51 default n
52 53
53config ARCH_HAS_ILOG2_U64 54config ARCH_HAS_ILOG2_U64
54 bool 55 def_bool n
55 default n
56 56
57config GENERIC_HWEIGHT 57config GENERIC_HWEIGHT
58 bool 58 def_bool y
59 default y
60 59
61config GENERIC_CALIBRATE_DELAY 60config GENERIC_CALIBRATE_DELAY
62 bool 61 def_bool y
63 default y
64 62
65config GENERIC_BUG 63config GENERIC_BUG
66 bool 64 def_bool y
67 default y
68 depends on BUG 65 depends on BUG
69 66
70source "init/Kconfig" 67source "init/Kconfig"
@@ -139,28 +136,22 @@ config PHYS_OFFSET
139source "kernel/Kconfig.preempt" 136source "kernel/Kconfig.preempt"
140 137
141config HAVE_ARCH_BOOTMEM_NODE 138config HAVE_ARCH_BOOTMEM_NODE
142 bool 139 def_bool n
143 default n
144 140
145config ARCH_HAVE_MEMORY_PRESENT 141config ARCH_HAVE_MEMORY_PRESENT
146 bool 142 def_bool n
147 default n
148 143
149config NEED_NODE_MEMMAP_SIZE 144config NEED_NODE_MEMMAP_SIZE
150 bool 145 def_bool n
151 default n
152 146
153config ARCH_FLATMEM_ENABLE 147config ARCH_FLATMEM_ENABLE
154 bool 148 def_bool y
155 default y
156 149
157config ARCH_DISCONTIGMEM_ENABLE 150config ARCH_DISCONTIGMEM_ENABLE
158 bool 151 def_bool n
159 default n
160 152
161config ARCH_SPARSEMEM_ENABLE 153config ARCH_SPARSEMEM_ENABLE
162 bool 154 def_bool n
163 default n
164 155
165source "mm/Kconfig" 156source "mm/Kconfig"
166 157
diff --git a/arch/avr32/kernel/Makefile b/arch/avr32/kernel/Makefile
index 989fcd1fef7e..2d6d48f35f69 100644
--- a/arch/avr32/kernel/Makefile
+++ b/arch/avr32/kernel/Makefile
@@ -11,3 +11,4 @@ obj-y += signal.o sys_avr32.o process.o time.o
11obj-y += init_task.o switch_to.o cpu.o 11obj-y += init_task.o switch_to.o cpu.o
12obj-$(CONFIG_MODULES) += module.o avr32_ksyms.o 12obj-$(CONFIG_MODULES) += module.o avr32_ksyms.o
13obj-$(CONFIG_KPROBES) += kprobes.o 13obj-$(CONFIG_KPROBES) += kprobes.o
14obj-$(CONFIG_STACKTRACE) += stacktrace.o
diff --git a/arch/avr32/kernel/asm-offsets.c b/arch/avr32/kernel/asm-offsets.c
index 97d865865667..078cd33f467b 100644
--- a/arch/avr32/kernel/asm-offsets.c
+++ b/arch/avr32/kernel/asm-offsets.c
@@ -21,5 +21,7 @@ void foo(void)
21 OFFSET(TI_flags, thread_info, flags); 21 OFFSET(TI_flags, thread_info, flags);
22 OFFSET(TI_cpu, thread_info, cpu); 22 OFFSET(TI_cpu, thread_info, cpu);
23 OFFSET(TI_preempt_count, thread_info, preempt_count); 23 OFFSET(TI_preempt_count, thread_info, preempt_count);
24 OFFSET(TI_rar_saved, thread_info, rar_saved);
25 OFFSET(TI_rsr_saved, thread_info, rsr_saved);
24 OFFSET(TI_restart_block, thread_info, restart_block); 26 OFFSET(TI_restart_block, thread_info, restart_block);
25} 27}
diff --git a/arch/avr32/kernel/entry-avr32b.S b/arch/avr32/kernel/entry-avr32b.S
index ccadfd9b438d..8cf16d7a7040 100644
--- a/arch/avr32/kernel/entry-avr32b.S
+++ b/arch/avr32/kernel/entry-avr32b.S
@@ -264,16 +264,7 @@ syscall_exit_work:
264 264
2653: bld r1, TIF_BREAKPOINT 2653: bld r1, TIF_BREAKPOINT
266 brcc syscall_exit_cont 266 brcc syscall_exit_cont
267 mfsr r3, SYSREG_TLBEHI 267 rjmp enter_monitor_mode
268 lddsp r2, sp[REG_PC]
269 andl r3, 0xff, COH
270 lsl r3, 1
271 sbr r3, 30
272 sbr r3, 0
273 mtdr DBGREG_BWA2A, r2
274 mtdr DBGREG_BWC2A, r3
275 rjmp syscall_exit_cont
276
277 268
278 /* The slow path of the TLB miss handler */ 269 /* The slow path of the TLB miss handler */
279page_table_not_present: 270page_table_not_present:
@@ -288,11 +279,16 @@ page_not_present:
288 rjmp ret_from_exception 279 rjmp ret_from_exception
289 280
290 /* This function expects to find offending PC in SYSREG_RAR_EX */ 281 /* This function expects to find offending PC in SYSREG_RAR_EX */
282 .type save_full_context_ex, @function
283 .align 2
291save_full_context_ex: 284save_full_context_ex:
285 mfsr r11, SYSREG_RAR_EX
286 sub r9, pc, . - debug_trampoline
292 mfsr r8, SYSREG_RSR_EX 287 mfsr r8, SYSREG_RSR_EX
288 cp.w r9, r11
289 breq 3f
293 mov r12, r8 290 mov r12, r8
294 andh r8, (MODE_MASK >> 16), COH 291 andh r8, (MODE_MASK >> 16), COH
295 mfsr r11, SYSREG_RAR_EX
296 brne 2f 292 brne 2f
297 293
2981: pushm r11, r12 /* PC and SR */ 2941: pushm r11, r12 /* PC and SR */
@@ -303,10 +299,25 @@ save_full_context_ex:
303 stdsp sp[4], r10 /* replace saved SP */ 299 stdsp sp[4], r10 /* replace saved SP */
304 rjmp 1b 300 rjmp 1b
305 301
302 /*
303 * The debug handler set up a trampoline to make us
304 * automatically enter monitor mode upon return, but since
305 * we're saving the full context, we must assume that the
306 * exception handler might want to alter the return address
307 * and/or status register. So we need to restore the original
308 * context and enter monitor mode manually after the exception
309 * has been handled.
310 */
3113: get_thread_info r8
312 ld.w r11, r8[TI_rar_saved]
313 ld.w r12, r8[TI_rsr_saved]
314 rjmp 1b
315 .size save_full_context_ex, . - save_full_context_ex
316
306 /* Low-level exception handlers */ 317 /* Low-level exception handlers */
307handle_critical: 318handle_critical:
308 pushm r12 319 sub sp, 4
309 pushm r0-r12 320 stmts --sp, r0-lr
310 rcall save_full_context_ex 321 rcall save_full_context_ex
311 mfsr r12, SYSREG_ECR 322 mfsr r12, SYSREG_ECR
312 mov r11, sp 323 mov r11, sp
@@ -439,6 +450,7 @@ do_fpe_ll:
439ret_from_exception: 450ret_from_exception:
440 mask_interrupts 451 mask_interrupts
441 lddsp r4, sp[REG_SR] 452 lddsp r4, sp[REG_SR]
453
442 andh r4, (MODE_MASK >> 16), COH 454 andh r4, (MODE_MASK >> 16), COH
443 brne fault_resume_kernel 455 brne fault_resume_kernel
444 456
@@ -515,119 +527,124 @@ fault_exit_work:
515 527
5162: bld r1, TIF_BREAKPOINT 5282: bld r1, TIF_BREAKPOINT
517 brcc fault_resume_user 529 brcc fault_resume_user
518 mfsr r3, SYSREG_TLBEHI 530 rjmp enter_monitor_mode
519 lddsp r2, sp[REG_PC] 531
520 andl r3, 0xff, COH 532 .section .kprobes.text, "ax", @progbits
521 lsl r3, 1 533 .type handle_debug, @function
522 sbr r3, 30 534handle_debug:
523 sbr r3, 0 535 sub sp, 4 /* r12_orig */
524 mtdr DBGREG_BWA2A, r2 536 stmts --sp, r0-lr
525 mtdr DBGREG_BWC2A, r3 537 mfsr r8, SYSREG_RAR_DBG
526 rjmp fault_resume_user 538 mfsr r9, SYSREG_RSR_DBG
527 539 unmask_exceptions
528 /* If we get a debug trap from privileged context we end up here */ 540 pushm r8-r9
529handle_debug_priv: 541 bfextu r9, r9, SYSREG_MODE_OFFSET, SYSREG_MODE_SIZE
530 /* Fix up LR and SP in regs. r11 contains the mode we came from */ 542 brne debug_fixup_regs
543
544.Ldebug_fixup_cont:
545#ifdef CONFIG_TRACE_IRQFLAGS
546 rcall trace_hardirqs_off
547#endif
548 mov r12, sp
549 rcall do_debug
550 mov sp, r12
551
552 lddsp r2, sp[REG_SR]
553 bfextu r3, r2, SYSREG_MODE_OFFSET, SYSREG_MODE_SIZE
554 brne debug_resume_kernel
555
556 get_thread_info r0
557 ld.w r1, r0[TI_flags]
558 mov r2, _TIF_DBGWORK_MASK
559 tst r1, r2
560 brne debug_exit_work
561
562 bld r1, TIF_SINGLE_STEP
563 brcc 1f
564 mfdr r4, OCD_DC
565 sbr r4, OCD_DC_SS_BIT
566 mtdr OCD_DC, r4
567
5681: popm r10,r11
569 mask_exceptions
570 mtsr SYSREG_RSR_DBG, r11
571 mtsr SYSREG_RAR_DBG, r10
572#ifdef CONFIG_TRACE_IRQFLAGS
573 rcall trace_hardirqs_on
5741:
575#endif
576 ldmts sp++, r0-lr
577 sub sp, -4
578 retd
579 .size handle_debug, . - handle_debug
580
581 /* Mode of the trapped context is in r9 */
582 .type debug_fixup_regs, @function
583debug_fixup_regs:
531 mfsr r8, SYSREG_SR 584 mfsr r8, SYSREG_SR
532 mov r9, r8 585 mov r10, r8
533 andh r8, hi(~MODE_MASK) 586 bfins r8, r9, SYSREG_MODE_OFFSET, SYSREG_MODE_SIZE
534 or r8, r11
535 mtsr SYSREG_SR, r8 587 mtsr SYSREG_SR, r8
536 sub pc, -2 588 sub pc, -2
537 stdsp sp[REG_LR], lr 589 stdsp sp[REG_LR], lr
538 mtsr SYSREG_SR, r9 590 mtsr SYSREG_SR, r10
539 sub pc, -2 591 sub pc, -2
540 sub r10, sp, -FRAME_SIZE_FULL 592 sub r8, sp, -FRAME_SIZE_FULL
541 stdsp sp[REG_SP], r10 593 stdsp sp[REG_SP], r8
542 mov r12, sp 594 rjmp .Ldebug_fixup_cont
543 rcall do_debug_priv 595 .size debug_fixup_regs, . - debug_fixup_regs
544 596
545 /* Now, put everything back */ 597 .type debug_resume_kernel, @function
546 ssrf SR_EM_BIT 598debug_resume_kernel:
599 mask_exceptions
547 popm r10, r11 600 popm r10, r11
548 mtsr SYSREG_RAR_DBG, r10 601 mtsr SYSREG_RAR_DBG, r10
549 mtsr SYSREG_RSR_DBG, r11 602 mtsr SYSREG_RSR_DBG, r11
550 mfsr r8, SYSREG_SR 603#ifdef CONFIG_TRACE_IRQFLAGS
551 mov r9, r8 604 bld r11, SYSREG_GM_OFFSET
552 andh r8, hi(~MODE_MASK) 605 brcc 1f
553 andh r11, hi(MODE_MASK) 606 rcall trace_hardirqs_on
554 or r8, r11 6071:
555 mtsr SYSREG_SR, r8 608#endif
609 mfsr r2, SYSREG_SR
610 mov r1, r2
611 bfins r2, r3, SYSREG_MODE_OFFSET, SYSREG_MODE_SIZE
612 mtsr SYSREG_SR, r2
556 sub pc, -2 613 sub pc, -2
557 popm lr 614 popm lr
558 mtsr SYSREG_SR, r9 615 mtsr SYSREG_SR, r1
559 sub pc, -2 616 sub pc, -2
560 sub sp, -4 /* skip SP */ 617 sub sp, -4 /* skip SP */
561 popm r0-r12 618 popm r0-r12
562 sub sp, -4 619 sub sp, -4
563 retd 620 retd
621 .size debug_resume_kernel, . - debug_resume_kernel
564 622
623 .type debug_exit_work, @function
624debug_exit_work:
565 /* 625 /*
566 * At this point, everything is masked, that is, interrupts, 626 * We must return from Monitor Mode using a retd, and we must
567 * exceptions and debugging traps. We might get called from 627 * not schedule since that involves the D bit in SR getting
568 * interrupt or exception context in some rare cases, but this 628 * cleared by something other than the debug hardware. This
569 * will be taken care of by do_debug(), so we're not going to 629 * may cause undefined behaviour according to the Architecture
570 * do a 100% correct context save here. 630 * manual.
631 *
632 * So we fix up the return address and status and return to a
633 * stub below in Exception mode. From there, we can follow the
634 * normal exception return path.
635 *
636 * The real return address and status registers are stored on
637 * the stack in the way the exception return path understands,
638 * so no need to fix anything up there.
571 */ 639 */
572handle_debug: 640 sub r8, pc, . - fault_exit_work
573 sub sp, 4 /* r12_orig */ 641 mtsr SYSREG_RAR_DBG, r8
574 stmts --sp, r0-lr 642 mov r9, 0
575 mfsr r10, SYSREG_RAR_DBG 643 orh r9, hi(SR_EM | SR_GM | MODE_EXCEPTION)
576 mfsr r11, SYSREG_RSR_DBG 644 mtsr SYSREG_RSR_DBG, r9
577 unmask_exceptions 645 sub pc, -2
578 pushm r10,r11
579 andh r11, (MODE_MASK >> 16), COH
580 brne handle_debug_priv
581
582 mov r12, sp
583 rcall do_debug
584
585 lddsp r10, sp[REG_SR]
586 andh r10, (MODE_MASK >> 16), COH
587 breq debug_resume_user
588
589debug_restore_all:
590 popm r10,r11
591 mask_exceptions
592 mtsr SYSREG_RSR_DBG, r11
593 mtsr SYSREG_RAR_DBG, r10
594 ldmts sp++, r0-lr
595 sub sp, -4
596 retd 646 retd
597 647 .size debug_exit_work, . - debug_exit_work
598debug_resume_user:
599 get_thread_info r0
600 mask_interrupts
601
602 ld.w r1, r0[TI_flags]
603 andl r1, _TIF_DBGWORK_MASK, COH
604 breq debug_restore_all
605
6061: bld r1, TIF_NEED_RESCHED
607 brcc 2f
608 unmask_interrupts
609 rcall schedule
610 mask_interrupts
611 ld.w r1, r0[TI_flags]
612 rjmp 1b
613
6142: mov r2, _TIF_SIGPENDING | _TIF_RESTORE_SIGMASK
615 tst r1, r2
616 breq 3f
617 unmask_interrupts
618 mov r12, sp
619 mov r11, r0
620 rcall do_notify_resume
621 mask_interrupts
622 ld.w r1, r0[TI_flags]
623 rjmp 1b
624
6253: bld r1, TIF_SINGLE_STEP
626 brcc debug_restore_all
627 mfdr r2, DBGREG_DC
628 sbr r2, DC_SS_BIT
629 mtdr DBGREG_DC, r2
630 rjmp debug_restore_all
631 648
632 .set rsr_int0, SYSREG_RSR_INT0 649 .set rsr_int0, SYSREG_RSR_INT0
633 .set rsr_int1, SYSREG_RSR_INT1 650 .set rsr_int1, SYSREG_RSR_INT1
@@ -675,7 +692,11 @@ irq_level\level:
675 andl r1, _TIF_WORK_MASK, COH 692 andl r1, _TIF_WORK_MASK, COH
676 brne irq_exit_work 693 brne irq_exit_work
677 694
6781: popm r8-r9 6951:
696#ifdef CONFIG_TRACE_IRQFLAGS
697 rcall trace_hardirqs_on
698#endif
699 popm r8-r9
679 mtsr rar_int\level, r8 700 mtsr rar_int\level, r8
680 mtsr rsr_int\level, r9 701 mtsr rsr_int\level, r9
681 ldmts sp++,r0-lr 702 ldmts sp++,r0-lr
@@ -748,3 +769,53 @@ cpu_idle_enable_int_and_exit:
748 IRQ_LEVEL 1 769 IRQ_LEVEL 1
749 IRQ_LEVEL 2 770 IRQ_LEVEL 2
750 IRQ_LEVEL 3 771 IRQ_LEVEL 3
772
773 .section .kprobes.text, "ax", @progbits
774 .type enter_monitor_mode, @function
775enter_monitor_mode:
776 /*
777 * We need to enter monitor mode to do a single step. The
778 * monitor code will alter the return address so that we
779 * return directly to the user instead of returning here.
780 */
781 breakpoint
782 rjmp breakpoint_failed
783
784 .size enter_monitor_mode, . - enter_monitor_mode
785
786 .type debug_trampoline, @function
787 .global debug_trampoline
788debug_trampoline:
789 /*
790 * Save the registers on the stack so that the monitor code
791 * can find them easily.
792 */
793 sub sp, 4 /* r12_orig */
794 stmts --sp, r0-lr
795 get_thread_info r0
796 ld.w r8, r0[TI_rar_saved]
797 ld.w r9, r0[TI_rsr_saved]
798 pushm r8-r9
799
800 /*
801 * The monitor code will alter the return address so we don't
802 * return here.
803 */
804 breakpoint
805 rjmp breakpoint_failed
806 .size debug_trampoline, . - debug_trampoline
807
808 .type breakpoint_failed, @function
809breakpoint_failed:
810 /*
811 * Something went wrong. Perhaps the debug hardware isn't
812 * enabled?
813 */
814 lda.w r12, msg_breakpoint_failed
815 mov r11, sp
816 mov r10, 9 /* SIGKILL */
817 call die
8181: rjmp 1b
819
820msg_breakpoint_failed:
821 .asciz "Failed to enter Debug Mode"
diff --git a/arch/avr32/kernel/kprobes.c b/arch/avr32/kernel/kprobes.c
index 20b1c9d8f945..799ba89b07a8 100644
--- a/arch/avr32/kernel/kprobes.c
+++ b/arch/avr32/kernel/kprobes.c
@@ -70,9 +70,9 @@ static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
70 70
71 BUG_ON(!(sysreg_read(SR) & SYSREG_BIT(SR_D))); 71 BUG_ON(!(sysreg_read(SR) & SYSREG_BIT(SR_D)));
72 72
73 dc = __mfdr(DBGREG_DC); 73 dc = ocd_read(DC);
74 dc |= DC_SS; 74 dc |= 1 << OCD_DC_SS_BIT;
75 __mtdr(DBGREG_DC, dc); 75 ocd_write(DC, dc);
76 76
77 /* 77 /*
78 * We must run the instruction from its original location 78 * We must run the instruction from its original location
@@ -91,9 +91,9 @@ static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs)
91 91
92 pr_debug("resuming execution at PC=%08lx\n", regs->pc); 92 pr_debug("resuming execution at PC=%08lx\n", regs->pc);
93 93
94 dc = __mfdr(DBGREG_DC); 94 dc = ocd_read(DC);
95 dc &= ~DC_SS; 95 dc &= ~(1 << OCD_DC_SS_BIT);
96 __mtdr(DBGREG_DC, dc); 96 ocd_write(DC, dc);
97 97
98 *p->addr = BREAKPOINT_INSTRUCTION; 98 *p->addr = BREAKPOINT_INSTRUCTION;
99 flush_icache_range((unsigned long)p->addr, 99 flush_icache_range((unsigned long)p->addr,
@@ -261,7 +261,7 @@ int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
261int __init arch_init_kprobes(void) 261int __init arch_init_kprobes(void)
262{ 262{
263 printk("KPROBES: Enabling monitor mode (MM|DBE)...\n"); 263 printk("KPROBES: Enabling monitor mode (MM|DBE)...\n");
264 __mtdr(DBGREG_DC, DC_MM | DC_DBE); 264 ocd_write(DC, (1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT));
265 265
266 /* TODO: Register kretprobe trampoline */ 266 /* TODO: Register kretprobe trampoline */
267 return 0; 267 return 0;
diff --git a/arch/avr32/kernel/process.c b/arch/avr32/kernel/process.c
index 13f988402613..9d6dac8af7a2 100644
--- a/arch/avr32/kernel/process.c
+++ b/arch/avr32/kernel/process.c
@@ -55,8 +55,8 @@ void machine_power_off(void)
55 55
56void machine_restart(char *cmd) 56void machine_restart(char *cmd)
57{ 57{
58 __mtdr(DBGREG_DC, DC_DBE); 58 ocd_write(DC, (1 << OCD_DC_DBE_BIT));
59 __mtdr(DBGREG_DC, DC_RES); 59 ocd_write(DC, (1 << OCD_DC_RES_BIT));
60 while (1) ; 60 while (1) ;
61} 61}
62 62
@@ -287,10 +287,11 @@ void show_regs_log_lvl(struct pt_regs *regs, const char *log_lvl)
287 regs->sr & SR_N ? 'N' : 'n', 287 regs->sr & SR_N ? 'N' : 'n',
288 regs->sr & SR_Z ? 'Z' : 'z', 288 regs->sr & SR_Z ? 'Z' : 'z',
289 regs->sr & SR_C ? 'C' : 'c'); 289 regs->sr & SR_C ? 'C' : 'c');
290 printk("%sMode bits: %c%c%c%c%c%c%c%c%c\n", log_lvl, 290 printk("%sMode bits: %c%c%c%c%c%c%c%c%c%c\n", log_lvl,
291 regs->sr & SR_H ? 'H' : 'h', 291 regs->sr & SR_H ? 'H' : 'h',
292 regs->sr & SR_R ? 'R' : 'r',
293 regs->sr & SR_J ? 'J' : 'j', 292 regs->sr & SR_J ? 'J' : 'j',
293 regs->sr & SR_DM ? 'M' : 'm',
294 regs->sr & SR_D ? 'D' : 'd',
294 regs->sr & SR_EM ? 'E' : 'e', 295 regs->sr & SR_EM ? 'E' : 'e',
295 regs->sr & SR_I3M ? '3' : '.', 296 regs->sr & SR_I3M ? '3' : '.',
296 regs->sr & SR_I2M ? '2' : '.', 297 regs->sr & SR_I2M ? '2' : '.',
diff --git a/arch/avr32/kernel/ptrace.c b/arch/avr32/kernel/ptrace.c
index 9e16b8a447f2..002369e44093 100644
--- a/arch/avr32/kernel/ptrace.c
+++ b/arch/avr32/kernel/ptrace.c
@@ -30,20 +30,22 @@ static struct pt_regs *get_user_regs(struct task_struct *tsk)
30 30
31static void ptrace_single_step(struct task_struct *tsk) 31static void ptrace_single_step(struct task_struct *tsk)
32{ 32{
33 pr_debug("ptrace_single_step: pid=%u, SR=0x%08lx\n", 33 pr_debug("ptrace_single_step: pid=%u, PC=0x%08lx, SR=0x%08lx\n",
34 tsk->pid, tsk->thread.cpu_context.sr); 34 tsk->pid, task_pt_regs(tsk)->pc, task_pt_regs(tsk)->sr);
35 if (!(tsk->thread.cpu_context.sr & SR_D)) {
36 /*
37 * Set a breakpoint at the current pc to force the
38 * process into debug mode. The syscall/exception
39 * exit code will set a breakpoint at the return
40 * address when this flag is set.
41 */
42 pr_debug("ptrace_single_step: Setting TIF_BREAKPOINT\n");
43 set_tsk_thread_flag(tsk, TIF_BREAKPOINT);
44 }
45 35
46 /* The monitor code will do the actual step for us */ 36 /*
37 * We can't schedule in Debug mode, so when TIF_BREAKPOINT is
38 * set, the system call or exception handler will do a
39 * breakpoint to enter monitor mode before returning to
40 * userspace.
41 *
42 * The monitor code will then notice that TIF_SINGLE_STEP is
43 * set and return to userspace with single stepping enabled.
44 * The CPU will then enter monitor mode again after exactly
45 * one instruction has been executed, and the monitor code
46 * will then send a SIGTRAP to the process.
47 */
48 set_tsk_thread_flag(tsk, TIF_BREAKPOINT);
47 set_tsk_thread_flag(tsk, TIF_SINGLE_STEP); 49 set_tsk_thread_flag(tsk, TIF_SINGLE_STEP);
48} 50}
49 51
@@ -55,23 +57,7 @@ static void ptrace_single_step(struct task_struct *tsk)
55void ptrace_disable(struct task_struct *child) 57void ptrace_disable(struct task_struct *child)
56{ 58{
57 clear_tsk_thread_flag(child, TIF_SINGLE_STEP); 59 clear_tsk_thread_flag(child, TIF_SINGLE_STEP);
58} 60 clear_tsk_thread_flag(child, TIF_BREAKPOINT);
59
60/*
61 * Handle hitting a breakpoint
62 */
63static void ptrace_break(struct task_struct *tsk, struct pt_regs *regs)
64{
65 siginfo_t info;
66
67 info.si_signo = SIGTRAP;
68 info.si_errno = 0;
69 info.si_code = TRAP_BRKPT;
70 info.si_addr = (void __user *)instruction_pointer(regs);
71
72 pr_debug("ptrace_break: Sending SIGTRAP to PID %u (pc = 0x%p)\n",
73 tsk->pid, info.si_addr);
74 force_sig_info(SIGTRAP, &info, tsk);
75} 61}
76 62
77/* 63/*
@@ -84,9 +70,6 @@ static int ptrace_read_user(struct task_struct *tsk, unsigned long offset,
84 unsigned long *regs; 70 unsigned long *regs;
85 unsigned long value; 71 unsigned long value;
86 72
87 pr_debug("ptrace_read_user(%p, %#lx, %p)\n",
88 tsk, offset, data);
89
90 if (offset & 3 || offset >= sizeof(struct user)) { 73 if (offset & 3 || offset >= sizeof(struct user)) {
91 printk("ptrace_read_user: invalid offset 0x%08lx\n", offset); 74 printk("ptrace_read_user: invalid offset 0x%08lx\n", offset);
92 return -EIO; 75 return -EIO;
@@ -98,6 +81,9 @@ static int ptrace_read_user(struct task_struct *tsk, unsigned long offset,
98 if (offset < sizeof(struct pt_regs)) 81 if (offset < sizeof(struct pt_regs))
99 value = regs[offset / sizeof(regs[0])]; 82 value = regs[offset / sizeof(regs[0])];
100 83
84 pr_debug("ptrace_read_user(%s[%u], %#lx, %p) -> %#lx\n",
85 tsk->comm, tsk->pid, offset, data, value);
86
101 return put_user(value, data); 87 return put_user(value, data);
102} 88}
103 89
@@ -111,8 +97,11 @@ static int ptrace_write_user(struct task_struct *tsk, unsigned long offset,
111{ 97{
112 unsigned long *regs; 98 unsigned long *regs;
113 99
100 pr_debug("ptrace_write_user(%s[%u], %#lx, %#lx)\n",
101 tsk->comm, tsk->pid, offset, value);
102
114 if (offset & 3 || offset >= sizeof(struct user)) { 103 if (offset & 3 || offset >= sizeof(struct user)) {
115 printk("ptrace_write_user: invalid offset 0x%08lx\n", offset); 104 pr_debug(" invalid offset 0x%08lx\n", offset);
116 return -EIO; 105 return -EIO;
117 } 106 }
118 107
@@ -155,11 +144,9 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
155{ 144{
156 int ret; 145 int ret;
157 146
158 pr_debug("arch_ptrace(%ld, %d, %#lx, %#lx)\n",
159 request, child->pid, addr, data);
160
161 pr_debug("ptrace: Enabling monitor mode...\n"); 147 pr_debug("ptrace: Enabling monitor mode...\n");
162 __mtdr(DBGREG_DC, __mfdr(DBGREG_DC) | DC_MM | DC_DBE); 148 ocd_write(DC, ocd_read(DC) | (1 << OCD_DC_MM_BIT)
149 | (1 << OCD_DC_DBE_BIT));
163 150
164 switch (request) { 151 switch (request) {
165 /* Read the word at location addr in the child process */ 152 /* Read the word at location addr in the child process */
@@ -240,19 +227,16 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
240 break; 227 break;
241 } 228 }
242 229
243 pr_debug("sys_ptrace returning %d (DC = 0x%08lx)\n", ret, __mfdr(DBGREG_DC));
244 return ret; 230 return ret;
245} 231}
246 232
247asmlinkage void syscall_trace(void) 233asmlinkage void syscall_trace(void)
248{ 234{
249 pr_debug("syscall_trace called\n");
250 if (!test_thread_flag(TIF_SYSCALL_TRACE)) 235 if (!test_thread_flag(TIF_SYSCALL_TRACE))
251 return; 236 return;
252 if (!(current->ptrace & PT_PTRACED)) 237 if (!(current->ptrace & PT_PTRACED))
253 return; 238 return;
254 239
255 pr_debug("syscall_trace: notifying parent\n");
256 /* The 0x80 provides a way for the tracing parent to 240 /* The 0x80 provides a way for the tracing parent to
257 * distinguish between a syscall stop and SIGTRAP delivery */ 241 * distinguish between a syscall stop and SIGTRAP delivery */
258 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) 242 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
@@ -271,86 +255,143 @@ asmlinkage void syscall_trace(void)
271 } 255 }
272} 256}
273 257
274asmlinkage void do_debug_priv(struct pt_regs *regs)
275{
276 unsigned long dc, ds;
277 unsigned long die_val;
278
279 ds = __mfdr(DBGREG_DS);
280
281 pr_debug("do_debug_priv: pc = %08lx, ds = %08lx\n", regs->pc, ds);
282
283 if (ds & DS_SSS)
284 die_val = DIE_SSTEP;
285 else
286 die_val = DIE_BREAKPOINT;
287
288 if (notify_die(die_val, "ptrace", regs, 0, 0, SIGTRAP) == NOTIFY_STOP)
289 return;
290
291 if (likely(ds & DS_SSS)) {
292 extern void itlb_miss(void);
293 extern void tlb_miss_common(void);
294 struct thread_info *ti;
295
296 dc = __mfdr(DBGREG_DC);
297 dc &= ~DC_SS;
298 __mtdr(DBGREG_DC, dc);
299
300 ti = current_thread_info();
301 set_ti_thread_flag(ti, TIF_BREAKPOINT);
302
303 /* The TLB miss handlers don't check thread flags */
304 if ((regs->pc >= (unsigned long)&itlb_miss)
305 && (regs->pc <= (unsigned long)&tlb_miss_common)) {
306 __mtdr(DBGREG_BWA2A, sysreg_read(RAR_EX));
307 __mtdr(DBGREG_BWC2A, 0x40000001 | (get_asid() << 1));
308 }
309
310 /*
311 * If we're running in supervisor mode, the breakpoint
312 * will take us where we want directly, no need to
313 * single step.
314 */
315 if ((regs->sr & MODE_MASK) != MODE_SUPERVISOR)
316 set_ti_thread_flag(ti, TIF_SINGLE_STEP);
317 } else {
318 panic("Unable to handle debug trap at pc = %08lx\n",
319 regs->pc);
320 }
321}
322
323/* 258/*
324 * Handle breakpoints, single steps and other debuggy things. To keep 259 * debug_trampoline() is an assembly stub which will store all user
325 * things simple initially, we run with interrupts and exceptions 260 * registers on the stack and execute a breakpoint instruction.
326 * disabled all the time. 261 *
262 * If we single-step into an exception handler which runs with
263 * interrupts disabled the whole time so it doesn't have to check for
264 * pending work, its return address will be modified so that it ends
265 * up returning to debug_trampoline.
266 *
267 * If the exception handler decides to store the user context and
268 * enable interrupts after all, it will restore the original return
269 * address and status register value. Before it returns, it will
270 * notice that TIF_BREAKPOINT is set and execute a breakpoint
271 * instruction.
327 */ 272 */
328asmlinkage void do_debug(struct pt_regs *regs) 273extern void debug_trampoline(void);
329{
330 unsigned long dc, ds;
331 274
332 ds = __mfdr(DBGREG_DS); 275asmlinkage struct pt_regs *do_debug(struct pt_regs *regs)
333 pr_debug("do_debug: pc = %08lx, ds = %08lx\n", regs->pc, ds); 276{
277 struct thread_info *ti;
278 unsigned long trampoline_addr;
279 u32 status;
280 u32 ctrl;
281 int code;
282
283 status = ocd_read(DS);
284 ti = current_thread_info();
285 code = TRAP_BRKPT;
286
287 pr_debug("do_debug: status=0x%08x PC=0x%08lx SR=0x%08lx tif=0x%08lx\n",
288 status, regs->pc, regs->sr, ti->flags);
289
290 if (!user_mode(regs)) {
291 unsigned long die_val = DIE_BREAKPOINT;
292
293 if (status & (1 << OCD_DS_SSS_BIT))
294 die_val = DIE_SSTEP;
295
296 if (notify_die(die_val, "ptrace", regs, 0, 0, SIGTRAP)
297 == NOTIFY_STOP)
298 return regs;
299
300 if ((status & (1 << OCD_DS_SWB_BIT))
301 && test_and_clear_ti_thread_flag(
302 ti, TIF_BREAKPOINT)) {
303 /*
304 * Explicit breakpoint from trampoline or
305 * exception/syscall/interrupt handler.
306 *
307 * The real saved regs are on the stack right
308 * after the ones we saved on entry.
309 */
310 regs++;
311 pr_debug(" -> TIF_BREAKPOINT done, adjusted regs:"
312 "PC=0x%08lx SR=0x%08lx\n",
313 regs->pc, regs->sr);
314 BUG_ON(!user_mode(regs));
315
316 if (test_thread_flag(TIF_SINGLE_STEP)) {
317 pr_debug("Going to do single step...\n");
318 return regs;
319 }
320
321 /*
322 * No TIF_SINGLE_STEP means we're done
323 * stepping over a syscall. Do the trap now.
324 */
325 code = TRAP_TRACE;
326 } else if ((status & (1 << OCD_DS_SSS_BIT))
327 && test_ti_thread_flag(ti, TIF_SINGLE_STEP)) {
328
329 pr_debug("Stepped into something, "
330 "setting TIF_BREAKPOINT...\n");
331 set_ti_thread_flag(ti, TIF_BREAKPOINT);
332
333 /*
334 * We stepped into an exception, interrupt or
335 * syscall handler. Some exception handlers
336 * don't check for pending work, so we need to
337 * set up a trampoline just in case.
338 *
339 * The exception entry code will undo the
340 * trampoline stuff if it does a full context
341 * save (which also means that it'll check for
342 * pending work later.)
343 */
344 if ((regs->sr & MODE_MASK) == MODE_EXCEPTION) {
345 trampoline_addr
346 = (unsigned long)&debug_trampoline;
347
348 pr_debug("Setting up trampoline...\n");
349 ti->rar_saved = sysreg_read(RAR_EX);
350 ti->rsr_saved = sysreg_read(RSR_EX);
351 sysreg_write(RAR_EX, trampoline_addr);
352 sysreg_write(RSR_EX, (MODE_EXCEPTION
353 | SR_EM | SR_GM));
354 BUG_ON(ti->rsr_saved & MODE_MASK);
355 }
356
357 /*
358 * If we stepped into a system call, we
359 * shouldn't do a single step after we return
360 * since the return address is right after the
361 * "scall" instruction we were told to step
362 * over.
363 */
364 if ((regs->sr & MODE_MASK) == MODE_SUPERVISOR) {
365 pr_debug("Supervisor; no single step\n");
366 clear_ti_thread_flag(ti, TIF_SINGLE_STEP);
367 }
368
369 ctrl = ocd_read(DC);
370 ctrl &= ~(1 << OCD_DC_SS_BIT);
371 ocd_write(DC, ctrl);
372
373 return regs;
374 } else {
375 printk(KERN_ERR "Unexpected OCD_DS value: 0x%08x\n",
376 status);
377 printk(KERN_ERR "Thread flags: 0x%08lx\n", ti->flags);
378 die("Unhandled debug trap in kernel mode",
379 regs, SIGTRAP);
380 }
381 } else if (status & (1 << OCD_DS_SSS_BIT)) {
382 /* Single step in user mode */
383 code = TRAP_TRACE;
334 384
335 if (test_thread_flag(TIF_BREAKPOINT)) { 385 ctrl = ocd_read(DC);
336 pr_debug("TIF_BREAKPOINT set\n"); 386 ctrl &= ~(1 << OCD_DC_SS_BIT);
337 /* We're taking care of it */ 387 ocd_write(DC, ctrl);
338 clear_thread_flag(TIF_BREAKPOINT);
339 __mtdr(DBGREG_BWC2A, 0);
340 } 388 }
341 389
342 if (test_thread_flag(TIF_SINGLE_STEP)) { 390 pr_debug("Sending SIGTRAP: code=%d PC=0x%08lx SR=0x%08lx\n",
343 pr_debug("TIF_SINGLE_STEP set, ds = 0x%08lx\n", ds); 391 code, regs->pc, regs->sr);
344 if (ds & DS_SSS) {
345 dc = __mfdr(DBGREG_DC);
346 dc &= ~DC_SS;
347 __mtdr(DBGREG_DC, dc);
348 392
349 clear_thread_flag(TIF_SINGLE_STEP); 393 clear_thread_flag(TIF_SINGLE_STEP);
350 ptrace_break(current, regs); 394 _exception(SIGTRAP, regs, code, instruction_pointer(regs));
351 } 395
352 } else { 396 return regs;
353 /* regular breakpoint */
354 ptrace_break(current, regs);
355 }
356} 397}
diff --git a/arch/avr32/kernel/stacktrace.c b/arch/avr32/kernel/stacktrace.c
new file mode 100644
index 000000000000..9a68190bbffd
--- /dev/null
+++ b/arch/avr32/kernel/stacktrace.c
@@ -0,0 +1,53 @@
1/*
2 * Stack trace management functions
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/sched.h>
11#include <linux/stacktrace.h>
12#include <linux/thread_info.h>
13
14register unsigned long current_frame_pointer asm("r7");
15
16struct stackframe {
17 unsigned long lr;
18 unsigned long fp;
19};
20
21/*
22 * Save stack-backtrace addresses into a stack_trace buffer.
23 */
24void save_stack_trace(struct stack_trace *trace)
25{
26 unsigned long low, high;
27 unsigned long fp;
28 struct stackframe *frame;
29 int skip = trace->skip;
30
31 low = (unsigned long)task_stack_page(current);
32 high = low + THREAD_SIZE;
33 fp = current_frame_pointer;
34
35 while (fp >= low && fp <= (high - 8)) {
36 frame = (struct stackframe *)fp;
37
38 if (skip) {
39 skip--;
40 } else {
41 trace->entries[trace->nr_entries++] = frame->lr;
42 if (trace->nr_entries >= trace->max_entries)
43 break;
44 }
45
46 /*
47 * The next frame must be at a higher address than the
48 * current frame.
49 */
50 low = fp + 8;
51 fp = frame->fp;
52 }
53}
diff --git a/arch/avr32/kernel/traps.c b/arch/avr32/kernel/traps.c
index 8a7caf8e7b45..870c075e6314 100644
--- a/arch/avr32/kernel/traps.c
+++ b/arch/avr32/kernel/traps.c
@@ -39,7 +39,7 @@ void NORET_TYPE die(const char *str, struct pt_regs *regs, long err)
39 printk("FRAME_POINTER "); 39 printk("FRAME_POINTER ");
40#endif 40#endif
41 if (current_cpu_data.features & AVR32_FEATURE_OCD) { 41 if (current_cpu_data.features & AVR32_FEATURE_OCD) {
42 unsigned long did = __mfdr(DBGREG_DID); 42 unsigned long did = ocd_read(DID);
43 printk("chip: 0x%03lx:0x%04lx rev %lu\n", 43 printk("chip: 0x%03lx:0x%04lx rev %lu\n",
44 (did >> 1) & 0x7ff, 44 (did >> 1) & 0x7ff,
45 (did >> 12) & 0x7fff, 45 (did >> 12) & 0x7fff,
diff --git a/arch/avr32/kernel/vmlinux.lds.S b/arch/avr32/kernel/vmlinux.lds.S
index ce9ac9659883..11f08e35a2eb 100644
--- a/arch/avr32/kernel/vmlinux.lds.S
+++ b/arch/avr32/kernel/vmlinux.lds.S
@@ -77,10 +77,10 @@ SECTIONS
77 . = 0x100; 77 . = 0x100;
78 *(.scall.text) 78 *(.scall.text)
79 *(.irq.text) 79 *(.irq.text)
80 KPROBES_TEXT
80 TEXT_TEXT 81 TEXT_TEXT
81 SCHED_TEXT 82 SCHED_TEXT
82 LOCK_TEXT 83 LOCK_TEXT
83 KPROBES_TEXT
84 *(.fixup) 84 *(.fixup)
85 *(.gnu.warning) 85 *(.gnu.warning)
86 _etext = .; 86 _etext = .;
diff --git a/arch/avr32/mm/cache.c b/arch/avr32/mm/cache.c
index c1233c615e67..15a4e5e142c1 100644
--- a/arch/avr32/mm/cache.c
+++ b/arch/avr32/mm/cache.c
@@ -122,16 +122,6 @@ void flush_icache_page(struct vm_area_struct *vma, struct page *page)
122 } 122 }
123} 123}
124 124
125/*
126 * This one is used by copy_to_user_page()
127 */
128void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
129 unsigned long addr, int len)
130{
131 if (vma->vm_flags & VM_EXEC)
132 flush_icache_range(addr, addr + len);
133}
134
135asmlinkage int sys_cacheflush(int operation, void __user *addr, size_t len) 125asmlinkage int sys_cacheflush(int operation, void __user *addr, size_t len)
136{ 126{
137 int ret; 127 int ret;
@@ -159,3 +149,13 @@ asmlinkage int sys_cacheflush(int operation, void __user *addr, size_t len)
159out: 149out:
160 return ret; 150 return ret;
161} 151}
152
153void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
154 unsigned long vaddr, void *dst, const void *src,
155 unsigned long len)
156{
157 memcpy(dst, src, len);
158 if (vma->vm_flags & VM_EXEC)
159 flush_icache_range((unsigned long)dst,
160 (unsigned long)dst + len);
161}
diff --git a/include/asm-avr32/cacheflush.h b/include/asm-avr32/cacheflush.h
index dfaaa88cd412..670674749b20 100644
--- a/include/asm-avr32/cacheflush.h
+++ b/include/asm-avr32/cacheflush.h
@@ -116,15 +116,16 @@ extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
116 * flush with all configurations. 116 * flush with all configurations.
117 */ 117 */
118extern void flush_icache_range(unsigned long start, unsigned long end); 118extern void flush_icache_range(unsigned long start, unsigned long end);
119extern void flush_icache_user_range(struct vm_area_struct *vma,
120 struct page *page,
121 unsigned long addr, int len);
122 119
123#define copy_to_user_page(vma, page, vaddr, dst, src, len) do { \ 120extern void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
124 memcpy(dst, src, len); \ 121 unsigned long vaddr, void *dst, const void *src,
125 flush_icache_user_range(vma, page, vaddr, len); \ 122 unsigned long len);
126} while(0) 123
127#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 124static inline void copy_from_user_page(struct vm_area_struct *vma,
128 memcpy(dst, src, len) 125 struct page *page, unsigned long vaddr, void *dst,
126 const void *src, unsigned long len)
127{
128 memcpy(dst, src, len);
129}
129 130
130#endif /* __ASM_AVR32_CACHEFLUSH_H */ 131#endif /* __ASM_AVR32_CACHEFLUSH_H */
diff --git a/include/asm-avr32/ocd.h b/include/asm-avr32/ocd.h
index 46f73180a127..996405e0393f 100644
--- a/include/asm-avr32/ocd.h
+++ b/include/asm-avr32/ocd.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * AVR32 OCD Registers 2 * AVR32 OCD Interface and register definitions
3 * 3 *
4 * Copyright (C) 2004-2006 Atmel Corporation 4 * Copyright (C) 2004-2007 Atmel Corporation
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -10,69 +10,529 @@
10#ifndef __ASM_AVR32_OCD_H 10#ifndef __ASM_AVR32_OCD_H
11#define __ASM_AVR32_OCD_H 11#define __ASM_AVR32_OCD_H
12 12
13/* Debug Registers */ 13/* OCD Register offsets. Abbreviations used below:
14#define DBGREG_DID 0 14 *
15#define DBGREG_DC 8 15 * BP Breakpoint
16#define DBGREG_DS 16 16 * Comm Communication
17#define DBGREG_RWCS 28 17 * DT Data Trace
18#define DBGREG_RWA 36 18 * PC Program Counter
19#define DBGREG_RWD 40 19 * PID Process ID
20#define DBGREG_WT 44 20 * R/W Read/Write
21#define DBGREG_DTC 52 21 * WP Watchpoint
22#define DBGREG_DTSA0 56 22 */
23#define DBGREG_DTSA1 60 23#define OCD_DID 0x0000 /* Device ID */
24#define DBGREG_DTEA0 72 24#define OCD_DC 0x0008 /* Development Control */
25#define DBGREG_DTEA1 76 25#define OCD_DS 0x0010 /* Development Status */
26#define DBGREG_BWC0A 88 26#define OCD_RWCS 0x001c /* R/W Access Control */
27#define DBGREG_BWC0B 92 27#define OCD_RWA 0x0024 /* R/W Access Address */
28#define DBGREG_BWC1A 96 28#define OCD_RWD 0x0028 /* R/W Access Data */
29#define DBGREG_BWC1B 100 29#define OCD_WT 0x002c /* Watchpoint Trigger */
30#define DBGREG_BWC2A 104 30#define OCD_DTC 0x0034 /* Data Trace Control */
31#define DBGREG_BWC2B 108 31#define OCD_DTSA0 0x0038 /* DT Start Addr Channel 0 */
32#define DBGREG_BWC3A 112 32#define OCD_DTSA1 0x003c /* DT Start Addr Channel 1 */
33#define DBGREG_BWC3B 116 33#define OCD_DTEA0 0x0048 /* DT End Addr Channel 0 */
34#define DBGREG_BWA0A 120 34#define OCD_DTEA1 0x004c /* DT End Addr Channel 1 */
35#define DBGREG_BWA0B 124 35#define OCD_BWC0A 0x0058 /* PC BP/WP Control 0A */
36#define DBGREG_BWA1A 128 36#define OCD_BWC0B 0x005c /* PC BP/WP Control 0B */
37#define DBGREG_BWA1B 132 37#define OCD_BWC1A 0x0060 /* PC BP/WP Control 1A */
38#define DBGREG_BWA2A 136 38#define OCD_BWC1B 0x0064 /* PC BP/WP Control 1B */
39#define DBGREG_BWA2B 140 39#define OCD_BWC2A 0x0068 /* PC BP/WP Control 2A */
40#define DBGREG_BWA3A 144 40#define OCD_BWC2B 0x006c /* PC BP/WP Control 2B */
41#define DBGREG_BWA3B 148 41#define OCD_BWC3A 0x0070 /* Data BP/WP Control 3A */
42#define DBGREG_BWD3A 153 42#define OCD_BWC3B 0x0074 /* Data BP/WP Control 3B */
43#define DBGREG_BWD3B 156 43#define OCD_BWA0A 0x0078 /* PC BP/WP Address 0A */
44 44#define OCD_BWA0B 0x007c /* PC BP/WP Address 0B */
45#define DBGREG_PID 284 45#define OCD_BWA1A 0x0080 /* PC BP/WP Address 1A */
46 46#define OCD_BWA1B 0x0084 /* PC BP/WP Address 1B */
47#define SABAH_OCD 0x01 47#define OCD_BWA2A 0x0088 /* PC BP/WP Address 2A */
48#define SABAH_ICACHE 0x02 48#define OCD_BWA2B 0x008c /* PC BP/WP Address 2B */
49#define SABAH_MEM_CACHED 0x04 49#define OCD_BWA3A 0x0090 /* Data BP/WP Address 3A */
50#define SABAH_MEM_UNCACHED 0x05 50#define OCD_BWA3B 0x0094 /* Data BP/WP Address 3B */
51 51#define OCD_NXCFG 0x0100 /* Nexus Configuration */
52/* Fields in the Development Control register */ 52#define OCD_DINST 0x0104 /* Debug Instruction */
53#define DC_SS_BIT 8 53#define OCD_DPC 0x0108 /* Debug Program Counter */
54 54#define OCD_CPUCM 0x010c /* CPU Control Mask */
55#define DC_SS (1 << DC_SS_BIT) 55#define OCD_DCCPU 0x0110 /* Debug Comm CPU */
56#define DC_DBE (1 << 13) 56#define OCD_DCEMU 0x0114 /* Debug Comm Emulator */
57#define DC_RID (1 << 27) 57#define OCD_DCSR 0x0118 /* Debug Comm Status */
58#define DC_ORP (1 << 28) 58#define OCD_PID 0x011c /* Ownership Trace PID */
59#define DC_MM (1 << 29) 59#define OCD_EPC0 0x0120 /* Event Pair Control 0 */
60#define DC_RES (1 << 30) 60#define OCD_EPC1 0x0124 /* Event Pair Control 1 */
61 61#define OCD_EPC2 0x0128 /* Event Pair Control 2 */
62/* Fields in the Development Status register */ 62#define OCD_EPC3 0x012c /* Event Pair Control 3 */
63#define DS_SSS (1 << 0) 63#define OCD_AXC 0x0130 /* AUX port Control */
64#define DS_SWB (1 << 1) 64
65#define DS_HWB (1 << 2) 65/* Bits in DID */
66#define DS_BP_SHIFT 8 66#define OCD_DID_MID_START 1
67#define DS_BP_MASK (0xff << DS_BP_SHIFT) 67#define OCD_DID_MID_SIZE 11
68 68#define OCD_DID_PN_START 12
69#define __mfdr(addr) \ 69#define OCD_DID_PN_SIZE 16
70({ \ 70#define OCD_DID_RN_START 28
71 register unsigned long value; \ 71#define OCD_DID_RN_SIZE 4
72 asm volatile("mfdr %0, %1" : "=r"(value) : "i"(addr)); \ 72
73 value; \ 73/* Bits in DC */
74}) 74#define OCD_DC_TM_START 0
75#define __mtdr(addr, value) \ 75#define OCD_DC_TM_SIZE 2
76 asm volatile("mtdr %0, %1" : : "i"(addr), "r"(value)) 76#define OCD_DC_EIC_START 3
77#define OCD_DC_EIC_SIZE 2
78#define OCD_DC_OVC_START 5
79#define OCD_DC_OVC_SIZE 3
80#define OCD_DC_SS_BIT 8
81#define OCD_DC_DBR_BIT 12
82#define OCD_DC_DBE_BIT 13
83#define OCD_DC_EOS_START 20
84#define OCD_DC_EOS_SIZE 2
85#define OCD_DC_SQA_BIT 22
86#define OCD_DC_IRP_BIT 23
87#define OCD_DC_IFM_BIT 24
88#define OCD_DC_TOZ_BIT 25
89#define OCD_DC_TSR_BIT 26
90#define OCD_DC_RID_BIT 27
91#define OCD_DC_ORP_BIT 28
92#define OCD_DC_MM_BIT 29
93#define OCD_DC_RES_BIT 30
94#define OCD_DC_ABORT_BIT 31
95
96/* Bits in DS */
97#define OCD_DS_SSS_BIT 0
98#define OCD_DS_SWB_BIT 1
99#define OCD_DS_HWB_BIT 2
100#define OCD_DS_HWE_BIT 3
101#define OCD_DS_STP_BIT 4
102#define OCD_DS_DBS_BIT 5
103#define OCD_DS_BP_START 8
104#define OCD_DS_BP_SIZE 8
105#define OCD_DS_INC_BIT 24
106#define OCD_DS_BOZ_BIT 25
107#define OCD_DS_DBA_BIT 26
108#define OCD_DS_EXB_BIT 27
109#define OCD_DS_NTBF_BIT 28
110
111/* Bits in RWCS */
112#define OCD_RWCS_DV_BIT 0
113#define OCD_RWCS_ERR_BIT 1
114#define OCD_RWCS_CNT_START 2
115#define OCD_RWCS_CNT_SIZE 14
116#define OCD_RWCS_CRC_BIT 19
117#define OCD_RWCS_NTBC_START 20
118#define OCD_RWCS_NTBC_SIZE 2
119#define OCD_RWCS_NTE_BIT 22
120#define OCD_RWCS_NTAP_BIT 23
121#define OCD_RWCS_WRAPPED_BIT 24
122#define OCD_RWCS_CCTRL_START 25
123#define OCD_RWCS_CCTRL_SIZE 2
124#define OCD_RWCS_SZ_START 27
125#define OCD_RWCS_SZ_SIZE 3
126#define OCD_RWCS_RW_BIT 30
127#define OCD_RWCS_AC_BIT 31
128
129/* Bits in RWA */
130#define OCD_RWA_RWA_START 0
131#define OCD_RWA_RWA_SIZE 32
132
133/* Bits in RWD */
134#define OCD_RWD_RWD_START 0
135#define OCD_RWD_RWD_SIZE 32
136
137/* Bits in WT */
138#define OCD_WT_DTE_START 20
139#define OCD_WT_DTE_SIZE 3
140#define OCD_WT_DTS_START 23
141#define OCD_WT_DTS_SIZE 3
142#define OCD_WT_PTE_START 26
143#define OCD_WT_PTE_SIZE 3
144#define OCD_WT_PTS_START 29
145#define OCD_WT_PTS_SIZE 3
146
147/* Bits in DTC */
148#define OCD_DTC_T0WP_BIT 0
149#define OCD_DTC_T1WP_BIT 1
150#define OCD_DTC_ASID0EN_BIT 2
151#define OCD_DTC_ASID0_START 3
152#define OCD_DTC_ASID0_SIZE 8
153#define OCD_DTC_ASID1EN_BIT 11
154#define OCD_DTC_ASID1_START 12
155#define OCD_DTC_ASID1_SIZE 8
156#define OCD_DTC_RWT1_START 28
157#define OCD_DTC_RWT1_SIZE 2
158#define OCD_DTC_RWT0_START 30
159#define OCD_DTC_RWT0_SIZE 2
160
161/* Bits in DTSA0 */
162#define OCD_DTSA0_DTSA_START 0
163#define OCD_DTSA0_DTSA_SIZE 32
164
165/* Bits in DTSA1 */
166#define OCD_DTSA1_DTSA_START 0
167#define OCD_DTSA1_DTSA_SIZE 32
168
169/* Bits in DTEA0 */
170#define OCD_DTEA0_DTEA_START 0
171#define OCD_DTEA0_DTEA_SIZE 32
172
173/* Bits in DTEA1 */
174#define OCD_DTEA1_DTEA_START 0
175#define OCD_DTEA1_DTEA_SIZE 32
176
177/* Bits in BWC0A */
178#define OCD_BWC0A_ASIDEN_BIT 0
179#define OCD_BWC0A_ASID_START 1
180#define OCD_BWC0A_ASID_SIZE 8
181#define OCD_BWC0A_EOC_BIT 14
182#define OCD_BWC0A_AME_BIT 25
183#define OCD_BWC0A_BWE_START 30
184#define OCD_BWC0A_BWE_SIZE 2
185
186/* Bits in BWC0B */
187#define OCD_BWC0B_ASIDEN_BIT 0
188#define OCD_BWC0B_ASID_START 1
189#define OCD_BWC0B_ASID_SIZE 8
190#define OCD_BWC0B_EOC_BIT 14
191#define OCD_BWC0B_AME_BIT 25
192#define OCD_BWC0B_BWE_START 30
193#define OCD_BWC0B_BWE_SIZE 2
194
195/* Bits in BWC1A */
196#define OCD_BWC1A_ASIDEN_BIT 0
197#define OCD_BWC1A_ASID_START 1
198#define OCD_BWC1A_ASID_SIZE 8
199#define OCD_BWC1A_EOC_BIT 14
200#define OCD_BWC1A_AME_BIT 25
201#define OCD_BWC1A_BWE_START 30
202#define OCD_BWC1A_BWE_SIZE 2
203
204/* Bits in BWC1B */
205#define OCD_BWC1B_ASIDEN_BIT 0
206#define OCD_BWC1B_ASID_START 1
207#define OCD_BWC1B_ASID_SIZE 8
208#define OCD_BWC1B_EOC_BIT 14
209#define OCD_BWC1B_AME_BIT 25
210#define OCD_BWC1B_BWE_START 30
211#define OCD_BWC1B_BWE_SIZE 2
212
213/* Bits in BWC2A */
214#define OCD_BWC2A_ASIDEN_BIT 0
215#define OCD_BWC2A_ASID_START 1
216#define OCD_BWC2A_ASID_SIZE 8
217#define OCD_BWC2A_EOC_BIT 14
218#define OCD_BWC2A_AMB_START 20
219#define OCD_BWC2A_AMB_SIZE 5
220#define OCD_BWC2A_AME_BIT 25
221#define OCD_BWC2A_BWE_START 30
222#define OCD_BWC2A_BWE_SIZE 2
223
224/* Bits in BWC2B */
225#define OCD_BWC2B_ASIDEN_BIT 0
226#define OCD_BWC2B_ASID_START 1
227#define OCD_BWC2B_ASID_SIZE 8
228#define OCD_BWC2B_EOC_BIT 14
229#define OCD_BWC2B_AME_BIT 25
230#define OCD_BWC2B_BWE_START 30
231#define OCD_BWC2B_BWE_SIZE 2
232
233/* Bits in BWC3A */
234#define OCD_BWC3A_ASIDEN_BIT 0
235#define OCD_BWC3A_ASID_START 1
236#define OCD_BWC3A_ASID_SIZE 8
237#define OCD_BWC3A_SIZE_START 9
238#define OCD_BWC3A_SIZE_SIZE 3
239#define OCD_BWC3A_EOC_BIT 14
240#define OCD_BWC3A_BWO_START 16
241#define OCD_BWC3A_BWO_SIZE 2
242#define OCD_BWC3A_BME_START 20
243#define OCD_BWC3A_BME_SIZE 4
244#define OCD_BWC3A_BRW_START 28
245#define OCD_BWC3A_BRW_SIZE 2
246#define OCD_BWC3A_BWE_START 30
247#define OCD_BWC3A_BWE_SIZE 2
248
249/* Bits in BWC3B */
250#define OCD_BWC3B_ASIDEN_BIT 0
251#define OCD_BWC3B_ASID_START 1
252#define OCD_BWC3B_ASID_SIZE 8
253#define OCD_BWC3B_SIZE_START 9
254#define OCD_BWC3B_SIZE_SIZE 3
255#define OCD_BWC3B_EOC_BIT 14
256#define OCD_BWC3B_BWO_START 16
257#define OCD_BWC3B_BWO_SIZE 2
258#define OCD_BWC3B_BME_START 20
259#define OCD_BWC3B_BME_SIZE 4
260#define OCD_BWC3B_BRW_START 28
261#define OCD_BWC3B_BRW_SIZE 2
262#define OCD_BWC3B_BWE_START 30
263#define OCD_BWC3B_BWE_SIZE 2
264
265/* Bits in BWA0A */
266#define OCD_BWA0A_BWA_START 0
267#define OCD_BWA0A_BWA_SIZE 32
268
269/* Bits in BWA0B */
270#define OCD_BWA0B_BWA_START 0
271#define OCD_BWA0B_BWA_SIZE 32
272
273/* Bits in BWA1A */
274#define OCD_BWA1A_BWA_START 0
275#define OCD_BWA1A_BWA_SIZE 32
276
277/* Bits in BWA1B */
278#define OCD_BWA1B_BWA_START 0
279#define OCD_BWA1B_BWA_SIZE 32
280
281/* Bits in BWA2A */
282#define OCD_BWA2A_BWA_START 0
283#define OCD_BWA2A_BWA_SIZE 32
284
285/* Bits in BWA2B */
286#define OCD_BWA2B_BWA_START 0
287#define OCD_BWA2B_BWA_SIZE 32
288
289/* Bits in BWA3A */
290#define OCD_BWA3A_BWA_START 0
291#define OCD_BWA3A_BWA_SIZE 32
292
293/* Bits in BWA3B */
294#define OCD_BWA3B_BWA_START 0
295#define OCD_BWA3B_BWA_SIZE 32
296
297/* Bits in NXCFG */
298#define OCD_NXCFG_NXARCH_START 0
299#define OCD_NXCFG_NXARCH_SIZE 4
300#define OCD_NXCFG_NXOCD_START 4
301#define OCD_NXCFG_NXOCD_SIZE 4
302#define OCD_NXCFG_NXPCB_START 8
303#define OCD_NXCFG_NXPCB_SIZE 4
304#define OCD_NXCFG_NXDB_START 12
305#define OCD_NXCFG_NXDB_SIZE 4
306#define OCD_NXCFG_MXMSEO_BIT 16
307#define OCD_NXCFG_NXMDO_START 17
308#define OCD_NXCFG_NXMDO_SIZE 4
309#define OCD_NXCFG_NXPT_BIT 21
310#define OCD_NXCFG_NXOT_BIT 22
311#define OCD_NXCFG_NXDWT_BIT 23
312#define OCD_NXCFG_NXDRT_BIT 24
313#define OCD_NXCFG_NXDTC_START 25
314#define OCD_NXCFG_NXDTC_SIZE 3
315#define OCD_NXCFG_NXDMA_BIT 28
316
317/* Bits in DINST */
318#define OCD_DINST_DINST_START 0
319#define OCD_DINST_DINST_SIZE 32
320
321/* Bits in CPUCM */
322#define OCD_CPUCM_BEM_BIT 1
323#define OCD_CPUCM_FEM_BIT 2
324#define OCD_CPUCM_REM_BIT 3
325#define OCD_CPUCM_IBEM_BIT 4
326#define OCD_CPUCM_IEEM_BIT 5
327
328/* Bits in DCCPU */
329#define OCD_DCCPU_DATA_START 0
330#define OCD_DCCPU_DATA_SIZE 32
331
332/* Bits in DCEMU */
333#define OCD_DCEMU_DATA_START 0
334#define OCD_DCEMU_DATA_SIZE 32
335
336/* Bits in DCSR */
337#define OCD_DCSR_CPUD_BIT 0
338#define OCD_DCSR_EMUD_BIT 1
339
340/* Bits in PID */
341#define OCD_PID_PROCESS_START 0
342#define OCD_PID_PROCESS_SIZE 32
343
344/* Bits in EPC0 */
345#define OCD_EPC0_RNG_START 0
346#define OCD_EPC0_RNG_SIZE 2
347#define OCD_EPC0_CE_BIT 4
348#define OCD_EPC0_ECNT_START 16
349#define OCD_EPC0_ECNT_SIZE 16
350
351/* Bits in EPC1 */
352#define OCD_EPC1_RNG_START 0
353#define OCD_EPC1_RNG_SIZE 2
354#define OCD_EPC1_ATB_BIT 5
355#define OCD_EPC1_AM_BIT 6
356
357/* Bits in EPC2 */
358#define OCD_EPC2_RNG_START 0
359#define OCD_EPC2_RNG_SIZE 2
360#define OCD_EPC2_DB_START 2
361#define OCD_EPC2_DB_SIZE 2
362
363/* Bits in EPC3 */
364#define OCD_EPC3_RNG_START 0
365#define OCD_EPC3_RNG_SIZE 2
366#define OCD_EPC3_DWE_BIT 2
367
368/* Bits in AXC */
369#define OCD_AXC_DIV_START 0
370#define OCD_AXC_DIV_SIZE 4
371#define OCD_AXC_AXE_BIT 8
372#define OCD_AXC_AXS_BIT 9
373#define OCD_AXC_DDR_BIT 10
374#define OCD_AXC_LS_BIT 11
375#define OCD_AXC_REX_BIT 12
376#define OCD_AXC_REXTEN_BIT 13
377
378/* Constants for DC:EIC */
379#define OCD_EIC_PROGRAM_AND_DATA_TRACE 0
380#define OCD_EIC_BREAKPOINT 1
381#define OCD_EIC_NOP 2
382
383/* Constants for DC:OVC */
384#define OCD_OVC_OVERRUN 0
385#define OCD_OVC_DELAY_CPU_BTM 1
386#define OCD_OVC_DELAY_CPU_DTM 2
387#define OCD_OVC_DELAY_CPU_BTM_DTM 3
388
389/* Constants for DC:EOS */
390#define OCD_EOS_NOP 0
391#define OCD_EOS_DEBUG_MODE 1
392#define OCD_EOS_BREAKPOINT_WATCHPOINT 2
393#define OCD_EOS_THQ 3
394
395/* Constants for RWCS:NTBC */
396#define OCD_NTBC_OVERWRITE 0
397#define OCD_NTBC_DISABLE 1
398#define OCD_NTBC_BREAKPOINT 2
399
400/* Constants for RWCS:CCTRL */
401#define OCD_CCTRL_AUTO 0
402#define OCD_CCTRL_CACHED 1
403#define OCD_CCTRL_UNCACHED 2
404
405/* Constants for RWCS:SZ */
406#define OCD_SZ_BYTE 0
407#define OCD_SZ_HALFWORD 1
408#define OCD_SZ_WORD 2
409
410/* Constants for WT:PTS */
411#define OCD_PTS_DISABLED 0
412#define OCD_PTS_PROGRAM_0B 1
413#define OCD_PTS_PROGRAM_1A 2
414#define OCD_PTS_PROGRAM_1B 3
415#define OCD_PTS_PROGRAM_2A 4
416#define OCD_PTS_PROGRAM_2B 5
417#define OCD_PTS_DATA_3A 6
418#define OCD_PTS_DATA_3B 7
419
420/* Constants for DTC:RWT1 */
421#define OCD_RWT1_NO_TRACE 0
422#define OCD_RWT1_DATA_READ 1
423#define OCD_RWT1_DATA_WRITE 2
424#define OCD_RWT1_DATA_READ_WRITE 3
425
426/* Constants for DTC:RWT0 */
427#define OCD_RWT0_NO_TRACE 0
428#define OCD_RWT0_DATA_READ 1
429#define OCD_RWT0_DATA_WRITE 2
430#define OCD_RWT0_DATA_READ_WRITE 3
431
432/* Constants for BWC0A:BWE */
433#define OCD_BWE_DISABLED 0
434#define OCD_BWE_BREAKPOINT_ENABLED 1
435#define OCD_BWE_WATCHPOINT_ENABLED 3
436
437/* Constants for BWC0B:BWE */
438#define OCD_BWE_DISABLED 0
439#define OCD_BWE_BREAKPOINT_ENABLED 1
440#define OCD_BWE_WATCHPOINT_ENABLED 3
441
442/* Constants for BWC1A:BWE */
443#define OCD_BWE_DISABLED 0
444#define OCD_BWE_BREAKPOINT_ENABLED 1
445#define OCD_BWE_WATCHPOINT_ENABLED 3
446
447/* Constants for BWC1B:BWE */
448#define OCD_BWE_DISABLED 0
449#define OCD_BWE_BREAKPOINT_ENABLED 1
450#define OCD_BWE_WATCHPOINT_ENABLED 3
451
452/* Constants for BWC2A:BWE */
453#define OCD_BWE_DISABLED 0
454#define OCD_BWE_BREAKPOINT_ENABLED 1
455#define OCD_BWE_WATCHPOINT_ENABLED 3
456
457/* Constants for BWC2B:BWE */
458#define OCD_BWE_DISABLED 0
459#define OCD_BWE_BREAKPOINT_ENABLED 1
460#define OCD_BWE_WATCHPOINT_ENABLED 3
461
462/* Constants for BWC3A:SIZE */
463#define OCD_SIZE_BYTE_ACCESS 4
464#define OCD_SIZE_HALFWORD_ACCESS 5
465#define OCD_SIZE_WORD_ACCESS 6
466#define OCD_SIZE_DOUBLE_WORD_ACCESS 7
467
468/* Constants for BWC3A:BRW */
469#define OCD_BRW_READ_BREAK 0
470#define OCD_BRW_WRITE_BREAK 1
471#define OCD_BRW_ANY_ACCES_BREAK 2
472
473/* Constants for BWC3A:BWE */
474#define OCD_BWE_DISABLED 0
475#define OCD_BWE_BREAKPOINT_ENABLED 1
476#define OCD_BWE_WATCHPOINT_ENABLED 3
477
478/* Constants for BWC3B:SIZE */
479#define OCD_SIZE_BYTE_ACCESS 4
480#define OCD_SIZE_HALFWORD_ACCESS 5
481#define OCD_SIZE_WORD_ACCESS 6
482#define OCD_SIZE_DOUBLE_WORD_ACCESS 7
483
484/* Constants for BWC3B:BRW */
485#define OCD_BRW_READ_BREAK 0
486#define OCD_BRW_WRITE_BREAK 1
487#define OCD_BRW_ANY_ACCES_BREAK 2
488
489/* Constants for BWC3B:BWE */
490#define OCD_BWE_DISABLED 0
491#define OCD_BWE_BREAKPOINT_ENABLED 1
492#define OCD_BWE_WATCHPOINT_ENABLED 3
493
494/* Constants for EPC0:RNG */
495#define OCD_RNG_DISABLED 0
496#define OCD_RNG_EXCLUSIVE 1
497#define OCD_RNG_INCLUSIVE 2
498
499/* Constants for EPC1:RNG */
500#define OCD_RNG_DISABLED 0
501#define OCD_RNG_EXCLUSIVE 1
502#define OCD_RNG_INCLUSIVE 2
503
504/* Constants for EPC2:RNG */
505#define OCD_RNG_DISABLED 0
506#define OCD_RNG_EXCLUSIVE 1
507#define OCD_RNG_INCLUSIVE 2
508
509/* Constants for EPC2:DB */
510#define OCD_DB_DISABLED 0
511#define OCD_DB_CHAINED_B 1
512#define OCD_DB_CHAINED_A 2
513#define OCD_DB_AHAINED_A_AND_B 3
514
515/* Constants for EPC3:RNG */
516#define OCD_RNG_DISABLED 0
517#define OCD_RNG_EXCLUSIVE 1
518#define OCD_RNG_INCLUSIVE 2
519
520#ifndef __ASSEMBLER__
521
522/* Register access macros */
523static inline unsigned long __ocd_read(unsigned int reg)
524{
525 return __builtin_mfdr(reg);
526}
527
528static inline void __ocd_write(unsigned int reg, unsigned long value)
529{
530 __builtin_mtdr(reg, value);
531}
532
533#define ocd_read(reg) __ocd_read(OCD_##reg)
534#define ocd_write(reg, value) __ocd_write(OCD_##reg, value)
535
536#endif /* !__ASSEMBLER__ */
77 537
78#endif /* __ASM_AVR32_OCD_H */ 538#endif /* __ASM_AVR32_OCD_H */
diff --git a/include/asm-avr32/processor.h b/include/asm-avr32/processor.h
index 6a64833756a6..a52576b25afe 100644
--- a/include/asm-avr32/processor.h
+++ b/include/asm-avr32/processor.h
@@ -139,6 +139,9 @@ extern void show_regs_log_lvl(struct pt_regs *regs, const char *log_lvl);
139extern void show_stack_log_lvl(struct task_struct *tsk, unsigned long sp, 139extern void show_stack_log_lvl(struct task_struct *tsk, unsigned long sp,
140 struct pt_regs *regs, const char *log_lvl); 140 struct pt_regs *regs, const char *log_lvl);
141 141
142#define task_pt_regs(p) \
143 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
144
142#define KSTK_EIP(tsk) ((tsk)->thread.cpu_context.pc) 145#define KSTK_EIP(tsk) ((tsk)->thread.cpu_context.pc)
143#define KSTK_ESP(tsk) ((tsk)->thread.cpu_context.ksp) 146#define KSTK_ESP(tsk) ((tsk)->thread.cpu_context.ksp)
144 147
diff --git a/include/asm-avr32/ptrace.h b/include/asm-avr32/ptrace.h
index 60f0f19a81f1..8c5dba5e33df 100644
--- a/include/asm-avr32/ptrace.h
+++ b/include/asm-avr32/ptrace.h
@@ -14,8 +14,7 @@
14/* 14/*
15 * Status Register bits 15 * Status Register bits
16 */ 16 */
17#define SR_H 0x40000000 17#define SR_H 0x20000000
18#define SR_R 0x20000000
19#define SR_J 0x10000000 18#define SR_J 0x10000000
20#define SR_DM 0x08000000 19#define SR_DM 0x08000000
21#define SR_D 0x04000000 20#define SR_D 0x04000000
@@ -35,8 +34,7 @@
35#define SR_I0M 0x00020000 34#define SR_I0M 0x00020000
36#define SR_GM 0x00010000 35#define SR_GM 0x00010000
37 36
38#define SR_H_BIT 30 37#define SR_H_BIT 29
39#define SR_R_BIT 29
40#define SR_J_BIT 28 38#define SR_J_BIT 28
41#define SR_DM_BIT 27 39#define SR_DM_BIT 27
42#define SR_D_BIT 26 40#define SR_D_BIT 26
diff --git a/include/asm-avr32/sysreg.h b/include/asm-avr32/sysreg.h
index dd21182b60e0..d4e0950170ca 100644
--- a/include/asm-avr32/sysreg.h
+++ b/include/asm-avr32/sysreg.h
@@ -93,6 +93,8 @@
93#define SYSREG_I3M_SIZE 1 93#define SYSREG_I3M_SIZE 1
94#define SYSREG_EM_OFFSET 21 94#define SYSREG_EM_OFFSET 21
95#define SYSREG_EM_SIZE 1 95#define SYSREG_EM_SIZE 1
96#define SYSREG_MODE_OFFSET 22
97#define SYSREG_MODE_SIZE 3
96#define SYSREG_M0_OFFSET 22 98#define SYSREG_M0_OFFSET 22
97#define SYSREG_M0_SIZE 1 99#define SYSREG_M0_SIZE 1
98#define SYSREG_M1_OFFSET 23 100#define SYSREG_M1_OFFSET 23
diff --git a/include/asm-avr32/system.h b/include/asm-avr32/system.h
index dc2d527cef41..c600cc15cbcb 100644
--- a/include/asm-avr32/system.h
+++ b/include/asm-avr32/system.h
@@ -35,8 +35,8 @@
35#include <asm/ocd.h> 35#include <asm/ocd.h>
36#define finish_arch_switch(prev) \ 36#define finish_arch_switch(prev) \
37 do { \ 37 do { \
38 __mtdr(DBGREG_PID, prev->pid); \ 38 ocd_write(PID, prev->pid); \
39 __mtdr(DBGREG_PID, current->pid); \ 39 ocd_write(PID, current->pid); \
40 } while(0) 40 } while(0)
41#endif 41#endif
42 42
diff --git a/include/asm-avr32/thread_info.h b/include/asm-avr32/thread_info.h
index 17dacf3f36d3..184b574289b4 100644
--- a/include/asm-avr32/thread_info.h
+++ b/include/asm-avr32/thread_info.h
@@ -25,6 +25,11 @@ struct thread_info {
25 unsigned long flags; /* low level flags */ 25 unsigned long flags; /* low level flags */
26 __u32 cpu; 26 __u32 cpu;
27 __s32 preempt_count; /* 0 => preemptable, <0 => BUG */ 27 __s32 preempt_count; /* 0 => preemptable, <0 => BUG */
28 __u32 rar_saved; /* return address... */
29 __u32 rsr_saved; /* ...and status register
30 saved by debug handler
31 when setting up
32 trampoline */
28 struct restart_block restart_block; 33 struct restart_block restart_block;
29 __u8 supervisor_stack[0]; 34 __u8 supervisor_stack[0];
30}; 35};
@@ -78,8 +83,8 @@ static inline struct thread_info *current_thread_info(void)
78#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ 83#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
79#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling 84#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling
80 TIF_NEED_RESCHED */ 85 TIF_NEED_RESCHED */
81#define TIF_BREAKPOINT 4 /* true if we should break after return */ 86#define TIF_BREAKPOINT 4 /* enter monitor mode on return */
82#define TIF_SINGLE_STEP 5 /* single step after next break */ 87#define TIF_SINGLE_STEP 5 /* single step in progress */
83#define TIF_MEMDIE 6 88#define TIF_MEMDIE 6
84#define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal */ 89#define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal */
85#define TIF_CPU_GOING_TO_SLEEP 8 /* CPU is entering sleep 0 mode */ 90#define TIF_CPU_GOING_TO_SLEEP 8 /* CPU is entering sleep 0 mode */
@@ -89,18 +94,24 @@ static inline struct thread_info *current_thread_info(void)
89#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) 94#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
90#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) 95#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
91#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) 96#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
92#define _TIF_BREAKPOINT (1 << TIF_BREAKPOINT)
93#define _TIF_SINGLE_STEP (1 << TIF_SINGLE_STEP) 97#define _TIF_SINGLE_STEP (1 << TIF_SINGLE_STEP)
94#define _TIF_MEMDIE (1 << TIF_MEMDIE) 98#define _TIF_MEMDIE (1 << TIF_MEMDIE)
95#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) 99#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK)
96#define _TIF_CPU_GOING_TO_SLEEP (1 << TIF_CPU_GOING_TO_SLEEP) 100#define _TIF_CPU_GOING_TO_SLEEP (1 << TIF_CPU_GOING_TO_SLEEP)
97 101
98/* XXX: These two masks must never span more than 16 bits! */ 102/* Note: The masks below must never span more than 16 bits! */
103
99/* work to do on interrupt/exception return */ 104/* work to do on interrupt/exception return */
100#define _TIF_WORK_MASK 0x0000013e 105#define _TIF_WORK_MASK \
106 ((1 << TIF_SIGPENDING) \
107 | (1 << TIF_NEED_RESCHED) \
108 | (1 << TIF_POLLING_NRFLAG) \
109 | (1 << TIF_BREAKPOINT) \
110 | (1 << TIF_RESTORE_SIGMASK))
111
101/* work to do on any return to userspace */ 112/* work to do on any return to userspace */
102#define _TIF_ALLWORK_MASK 0x0000013f 113#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | (1 << TIF_SYSCALL_TRACE))
103/* work to do on return from debug mode */ 114/* work to do on return from debug mode */
104#define _TIF_DBGWORK_MASK 0x0000017e 115#define _TIF_DBGWORK_MASK (_TIF_WORK_MASK & ~(1 << TIF_BREAKPOINT))
105 116
106#endif /* __ASM_AVR32_THREAD_INFO_H */ 117#endif /* __ASM_AVR32_THREAD_INFO_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 15:58:33 -0500