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authorPaul Gortmaker <paul.gortmaker@windriver.com>2008-01-28 16:09:36 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 17:16:38 -0500
commitcda13dd164f91df79ba797ab84848352b03de115 (patch)
treef366a541f2358c4b74b3e4c8b7ec04994c23d3e8
parenta6f71745969d495d697d1ccd96385d2f7a963375 (diff)
[POWERPC] 83xx: Clean up / convert mpc83xx board DTS files to v1 format.
This patch converts the remaining 83xx boards to the dts-v1 format. This includes the mpc8313_rdb, mpc832x_mds, mpc8323_rdb, mpc8349emitx, mpc8349emitxgp and the mpc836x_mds. The mpc8315_rdb mpc834x_mds, mpc837[789]_*, and sbc8349 were already dts-v1 and only undergo minor changes for the sake of formatting consistency across the whole group of boards; i.e. the idea being that you can do a "diff -u board_A.dts board_B.dts" and see something meaningful. The general rule I've applied is that entries for values normally parsed by humans are left in decimal (i.e. IRQ, cache size, clock rates, basic counts and indexes) and all other data (i.e. reg and ranges, IRQ flags etc.) remain in hex. I've used dtc to confirm that the output prior to this changeset matches the output after this changeset is applied for all boards. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts152
-rw-r--r--arch/powerpc/boot/dts/mpc8315erdb.dts100
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts252
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts154
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts155
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitxgp.dts109
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts36
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts260
-rw-r--r--arch/powerpc/boot/dts/mpc8377_mds.dts138
-rw-r--r--arch/powerpc/boot/dts/mpc8377_rdb.dts102
-rw-r--r--arch/powerpc/boot/dts/mpc8378_mds.dts130
-rw-r--r--arch/powerpc/boot/dts/mpc8378_rdb.dts94
-rw-r--r--arch/powerpc/boot/dts/mpc8379_mds.dts146
-rw-r--r--arch/powerpc/boot/dts/mpc8379_rdb.dts112
-rw-r--r--arch/powerpc/boot/dts/sbc8349.dts44
15 files changed, 999 insertions, 985 deletions
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 20a03f5b5bb7..2d6653fe72ff 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -9,6 +9,8 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 model = "MPC8313ERDB"; 15 model = "MPC8313ERDB";
14 compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB"; 16 compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
@@ -29,11 +31,11 @@
29 31
30 PowerPC,8313@0 { 32 PowerPC,8313@0 {
31 device_type = "cpu"; 33 device_type = "cpu";
32 reg = <0>; 34 reg = <0x0>;
33 d-cache-line-size = <20>; // 32 bytes 35 d-cache-line-size = <32>;
34 i-cache-line-size = <20>; // 32 bytes 36 i-cache-line-size = <32>;
35 d-cache-size = <4000>; // L1, 16K 37 d-cache-size = <16384>;
36 i-cache-size = <4000>; // L1, 16K 38 i-cache-size = <16384>;
37 timebase-frequency = <0>; // from bootloader 39 timebase-frequency = <0>; // from bootloader
38 bus-frequency = <0>; // from bootloader 40 bus-frequency = <0>; // from bootloader
39 clock-frequency = <0>; // from bootloader 41 clock-frequency = <0>; // from bootloader
@@ -42,30 +44,30 @@
42 44
43 memory { 45 memory {
44 device_type = "memory"; 46 device_type = "memory";
45 reg = <00000000 08000000>; // 128MB at 0 47 reg = <0x00000000 0x08000000>; // 128MB at 0
46 }; 48 };
47 49
48 localbus@e0005000 { 50 localbus@e0005000 {
49 #address-cells = <2>; 51 #address-cells = <2>;
50 #size-cells = <1>; 52 #size-cells = <1>;
51 compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus"; 53 compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
52 reg = <e0005000 1000>; 54 reg = <0xe0005000 0x1000>;
53 interrupts = <d#77 8>; 55 interrupts = <77 0x8>;
54 interrupt-parent = <&ipic>; 56 interrupt-parent = <&ipic>;
55 57
56 // CS0 and CS1 are swapped when 58 // CS0 and CS1 are swapped when
57 // booting from nand, but the 59 // booting from nand, but the
58 // addresses are the same. 60 // addresses are the same.
59 ranges = <0 0 fe000000 00800000 61 ranges = <0x0 0x0 0xfe000000 0x00800000
60 1 0 e2800000 00008000 62 0x1 0x0 0xe2800000 0x00008000
61 2 0 f0000000 00020000 63 0x2 0x0 0xf0000000 0x00020000
62 3 0 fa000000 00008000>; 64 0x3 0x0 0xfa000000 0x00008000>;
63 65
64 flash@0,0 { 66 flash@0,0 {
65 #address-cells = <1>; 67 #address-cells = <1>;
66 #size-cells = <1>; 68 #size-cells = <1>;
67 compatible = "cfi-flash"; 69 compatible = "cfi-flash";
68 reg = <0 0 800000>; 70 reg = <0x0 0x0 0x800000>;
69 bank-width = <2>; 71 bank-width = <2>;
70 device-width = <1>; 72 device-width = <1>;
71 }; 73 };
@@ -75,19 +77,19 @@
75 #size-cells = <1>; 77 #size-cells = <1>;
76 compatible = "fsl,mpc8313-fcm-nand", 78 compatible = "fsl,mpc8313-fcm-nand",
77 "fsl,elbc-fcm-nand"; 79 "fsl,elbc-fcm-nand";
78 reg = <1 0 2000>; 80 reg = <0x1 0x0 0x2000>;
79 81
80 u-boot@0 { 82 u-boot@0 {
81 reg = <0 100000>; 83 reg = <0x0 0x100000>;
82 read-only; 84 read-only;
83 }; 85 };
84 86
85 kernel@100000 { 87 kernel@100000 {
86 reg = <100000 300000>; 88 reg = <0x100000 0x300000>;
87 }; 89 };
88 90
89 fs@400000 { 91 fs@400000 {
90 reg = <400000 1c00000>; 92 reg = <0x400000 0x1c00000>;
91 }; 93 };
92 }; 94 };
93 }; 95 };
@@ -97,14 +99,14 @@
97 #size-cells = <1>; 99 #size-cells = <1>;
98 device_type = "soc"; 100 device_type = "soc";
99 compatible = "simple-bus"; 101 compatible = "simple-bus";
100 ranges = <0 e0000000 00100000>; 102 ranges = <0x0 0xe0000000 0x00100000>;
101 reg = <e0000000 00000200>; 103 reg = <0xe0000000 0x00000200>;
102 bus-frequency = <0>; 104 bus-frequency = <0>;
103 105
104 wdt@200 { 106 wdt@200 {
105 device_type = "watchdog"; 107 device_type = "watchdog";
106 compatible = "mpc83xx_wdt"; 108 compatible = "mpc83xx_wdt";
107 reg = <200 100>; 109 reg = <0x200 0x100>;
108 }; 110 };
109 111
110 i2c@3000 { 112 i2c@3000 {
@@ -112,9 +114,9 @@
112 #size-cells = <0>; 114 #size-cells = <0>;
113 cell-index = <0>; 115 cell-index = <0>;
114 compatible = "fsl-i2c"; 116 compatible = "fsl-i2c";
115 reg = <3000 100>; 117 reg = <0x3000 0x100>;
116 interrupts = <e 8>; 118 interrupts = <14 0x8>;
117 interrupt-parent = < &ipic >; 119 interrupt-parent = <&ipic>;
118 dfsrr; 120 dfsrr;
119 }; 121 };
120 122
@@ -123,29 +125,29 @@
123 #size-cells = <0>; 125 #size-cells = <0>;
124 cell-index = <1>; 126 cell-index = <1>;
125 compatible = "fsl-i2c"; 127 compatible = "fsl-i2c";
126 reg = <3100 100>; 128 reg = <0x3100 0x100>;
127 interrupts = <f 8>; 129 interrupts = <15 0x8>;
128 interrupt-parent = < &ipic >; 130 interrupt-parent = <&ipic>;
129 dfsrr; 131 dfsrr;
130 }; 132 };
131 133
132 spi@7000 { 134 spi@7000 {
133 cell-index = <0>; 135 cell-index = <0>;
134 compatible = "fsl,spi"; 136 compatible = "fsl,spi";
135 reg = <7000 1000>; 137 reg = <0x7000 0x1000>;
136 interrupts = <10 8>; 138 interrupts = <16 0x8>;
137 interrupt-parent = < &ipic >; 139 interrupt-parent = <&ipic>;
138 mode = "cpu"; 140 mode = "cpu";
139 }; 141 };
140 142
141 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 143 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
142 usb@23000 { 144 usb@23000 {
143 compatible = "fsl-usb2-dr"; 145 compatible = "fsl-usb2-dr";
144 reg = <23000 1000>; 146 reg = <0x23000 0x1000>;
145 #address-cells = <1>; 147 #address-cells = <1>;
146 #size-cells = <0>; 148 #size-cells = <0>;
147 interrupt-parent = < &ipic >; 149 interrupt-parent = <&ipic>;
148 interrupts = <26 8>; 150 interrupts = <38 0x8>;
149 phy_type = "utmi_wide"; 151 phy_type = "utmi_wide";
150 }; 152 };
151 153
@@ -153,17 +155,17 @@
153 #address-cells = <1>; 155 #address-cells = <1>;
154 #size-cells = <0>; 156 #size-cells = <0>;
155 compatible = "fsl,gianfar-mdio"; 157 compatible = "fsl,gianfar-mdio";
156 reg = <24520 20>; 158 reg = <0x24520 0x20>;
157 phy1: ethernet-phy@1 { 159 phy1: ethernet-phy@1 {
158 interrupt-parent = < &ipic >; 160 interrupt-parent = <&ipic>;
159 interrupts = <13 8>; 161 interrupts = <19 0x8>;
160 reg = <1>; 162 reg = <0x1>;
161 device_type = "ethernet-phy"; 163 device_type = "ethernet-phy";
162 }; 164 };
163 phy4: ethernet-phy@4 { 165 phy4: ethernet-phy@4 {
164 interrupt-parent = < &ipic >; 166 interrupt-parent = <&ipic>;
165 interrupts = <14 8>; 167 interrupts = <20 0x8>;
166 reg = <4>; 168 reg = <0x4>;
167 device_type = "ethernet-phy"; 169 device_type = "ethernet-phy";
168 }; 170 };
169 }; 171 };
@@ -173,10 +175,10 @@
173 device_type = "network"; 175 device_type = "network";
174 model = "eTSEC"; 176 model = "eTSEC";
175 compatible = "gianfar"; 177 compatible = "gianfar";
176 reg = <24000 1000>; 178 reg = <0x24000 0x1000>;
177 local-mac-address = [ 00 00 00 00 00 00 ]; 179 local-mac-address = [ 00 00 00 00 00 00 ];
178 interrupts = <25 8 24 8 23 8>; 180 interrupts = <37 0x8 36 0x8 35 0x8>;
179 interrupt-parent = < &ipic >; 181 interrupt-parent = <&ipic>;
180 phy-handle = < &phy1 >; 182 phy-handle = < &phy1 >;
181 }; 183 };
182 184
@@ -185,10 +187,10 @@
185 device_type = "network"; 187 device_type = "network";
186 model = "eTSEC"; 188 model = "eTSEC";
187 compatible = "gianfar"; 189 compatible = "gianfar";
188 reg = <25000 1000>; 190 reg = <0x25000 0x1000>;
189 local-mac-address = [ 00 00 00 00 00 00 ]; 191 local-mac-address = [ 00 00 00 00 00 00 ];
190 interrupts = <22 8 21 8 20 8>; 192 interrupts = <34 0x8 33 0x8 32 0x8>;
191 interrupt-parent = < &ipic >; 193 interrupt-parent = <&ipic>;
192 phy-handle = < &phy4 >; 194 phy-handle = < &phy4 >;
193 }; 195 };
194 196
@@ -196,34 +198,34 @@
196 cell-index = <0>; 198 cell-index = <0>;
197 device_type = "serial"; 199 device_type = "serial";
198 compatible = "ns16550"; 200 compatible = "ns16550";
199 reg = <4500 100>; 201 reg = <0x4500 0x100>;
200 clock-frequency = <0>; 202 clock-frequency = <0>;
201 interrupts = <9 8>; 203 interrupts = <9 0x8>;
202 interrupt-parent = < &ipic >; 204 interrupt-parent = <&ipic>;
203 }; 205 };
204 206
205 serial1: serial@4600 { 207 serial1: serial@4600 {
206 cell-index = <1>; 208 cell-index = <1>;
207 device_type = "serial"; 209 device_type = "serial";
208 compatible = "ns16550"; 210 compatible = "ns16550";
209 reg = <4600 100>; 211 reg = <0x4600 0x100>;
210 clock-frequency = <0>; 212 clock-frequency = <0>;
211 interrupts = <a 8>; 213 interrupts = <10 0x8>;
212 interrupt-parent = < &ipic >; 214 interrupt-parent = <&ipic>;
213 }; 215 };
214 216
215 crypto@30000 { 217 crypto@30000 {
216 device_type = "crypto"; 218 device_type = "crypto";
217 model = "SEC2"; 219 model = "SEC2";
218 compatible = "talitos"; 220 compatible = "talitos";
219 reg = <30000 7000>; 221 reg = <0x30000 0x7000>;
220 interrupts = <b 8>; 222 interrupts = <11 0x8>;
221 interrupt-parent = < &ipic >; 223 interrupt-parent = <&ipic>;
222 /* Rev. 2.2 */ 224 /* Rev. 2.2 */
223 num-channels = <1>; 225 num-channels = <1>;
224 channel-fifo-len = <18>; 226 channel-fifo-len = <24>;
225 exec-units-mask = <0000004c>; 227 exec-units-mask = <0x0000004c>;
226 descriptor-types-mask = <0122003f>; 228 descriptor-types-mask = <0x0122003f>;
227 }; 229 };
228 230
229 /* IPIC 231 /* IPIC
@@ -236,38 +238,38 @@
236 interrupt-controller; 238 interrupt-controller;
237 #address-cells = <0>; 239 #address-cells = <0>;
238 #interrupt-cells = <2>; 240 #interrupt-cells = <2>;
239 reg = <700 100>; 241 reg = <0x700 0x100>;
240 device_type = "ipic"; 242 device_type = "ipic";
241 }; 243 };
242 }; 244 };
243 245
244 pci0: pci@e0008500 { 246 pci0: pci@e0008500 {
245 cell-index = <1>; 247 cell-index = <1>;
246 interrupt-map-mask = <f800 0 0 7>; 248 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
247 interrupt-map = < 249 interrupt-map = <
248 250
249 /* IDSEL 0x0E -mini PCI */ 251 /* IDSEL 0x0E -mini PCI */
250 7000 0 0 1 &ipic 12 8 252 0x7000 0x0 0x0 0x1 &ipic 18 0x8
251 7000 0 0 2 &ipic 12 8 253 0x7000 0x0 0x0 0x2 &ipic 18 0x8
252 7000 0 0 3 &ipic 12 8 254 0x7000 0x0 0x0 0x3 &ipic 18 0x8
253 7000 0 0 4 &ipic 12 8 255 0x7000 0x0 0x0 0x4 &ipic 18 0x8
254 256
255 /* IDSEL 0x0F - PCI slot */ 257 /* IDSEL 0x0F - PCI slot */
256 7800 0 0 1 &ipic 11 8 258 0x7800 0x0 0x0 0x1 &ipic 17 0x8
257 7800 0 0 2 &ipic 12 8 259 0x7800 0x0 0x0 0x2 &ipic 18 0x8
258 7800 0 0 3 &ipic 11 8 260 0x7800 0x0 0x0 0x3 &ipic 17 0x8
259 7800 0 0 4 &ipic 12 8>; 261 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
260 interrupt-parent = < &ipic >; 262 interrupt-parent = <&ipic>;
261 interrupts = <42 8>; 263 interrupts = <66 0x8>;
262 bus-range = <0 0>; 264 bus-range = <0x0 0x0>;
263 ranges = <02000000 0 90000000 90000000 0 10000000 265 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
264 42000000 0 80000000 80000000 0 10000000 266 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
265 01000000 0 00000000 e2000000 0 00100000>; 267 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
266 clock-frequency = <3f940aa>; 268 clock-frequency = <66666666>;
267 #interrupt-cells = <1>; 269 #interrupt-cells = <1>;
268 #size-cells = <2>; 270 #size-cells = <2>;
269 #address-cells = <3>; 271 #address-cells = <3>;
270 reg = <e0008500 100>; 272 reg = <0xe0008500 0x100>;
271 compatible = "fsl,mpc8349-pci"; 273 compatible = "fsl,mpc8349-pci";
272 device_type = "pci"; 274 device_type = "pci";
273 }; 275 };
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index e157f2342ea0..b582032ba3d6 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -30,7 +30,7 @@
30 30
31 PowerPC,8315@0 { 31 PowerPC,8315@0 {
32 device_type = "cpu"; 32 device_type = "cpu";
33 reg = <0>; 33 reg = <0x0>;
34 d-cache-line-size = <32>; 34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>; 35 i-cache-line-size = <32>;
36 d-cache-size = <16384>; 36 d-cache-size = <16384>;
@@ -51,22 +51,22 @@
51 #size-cells = <1>; 51 #size-cells = <1>;
52 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; 52 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>; 53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 8>; 54 interrupts = <77 0x8>;
55 interrupt-parent = <&ipic>; 55 interrupt-parent = <&ipic>;
56 56
57 // CS0 and CS1 are swapped when 57 // CS0 and CS1 are swapped when
58 // booting from nand, but the 58 // booting from nand, but the
59 // addresses are the same. 59 // addresses are the same.
60 ranges = <0 0 0xfe000000 0x00800000 60 ranges = <0x0 0x0 0xfe000000 0x00800000
61 1 0 0xe0600000 0x00002000 61 0x1 0x0 0xe0600000 0x00002000
62 2 0 0xf0000000 0x00020000 62 0x2 0x0 0xf0000000 0x00020000
63 3 0 0xfa000000 0x00008000>; 63 0x3 0x0 0xfa000000 0x00008000>;
64 64
65 flash@0,0 { 65 flash@0,0 {
66 #address-cells = <1>; 66 #address-cells = <1>;
67 #size-cells = <1>; 67 #size-cells = <1>;
68 compatible = "cfi-flash"; 68 compatible = "cfi-flash";
69 reg = <0 0 0x800000>; 69 reg = <0x0 0x0 0x800000>;
70 bank-width = <2>; 70 bank-width = <2>;
71 device-width = <1>; 71 device-width = <1>;
72 }; 72 };
@@ -76,7 +76,7 @@
76 #size-cells = <1>; 76 #size-cells = <1>;
77 compatible = "fsl,mpc8315-fcm-nand", 77 compatible = "fsl,mpc8315-fcm-nand",
78 "fsl,elbc-fcm-nand"; 78 "fsl,elbc-fcm-nand";
79 reg = <1 0 0x2000>; 79 reg = <0x1 0x0 0x2000>;
80 80
81 u-boot@0 { 81 u-boot@0 {
82 reg = <0x0 0x100000>; 82 reg = <0x0 0x100000>;
@@ -113,8 +113,8 @@
113 cell-index = <0>; 113 cell-index = <0>;
114 compatible = "fsl-i2c"; 114 compatible = "fsl-i2c";
115 reg = <0x3000 0x100>; 115 reg = <0x3000 0x100>;
116 interrupts = <14 8>; 116 interrupts = <14 0x8>;
117 interrupt-parent = < &ipic >; 117 interrupt-parent = <&ipic>;
118 dfsrr; 118 dfsrr;
119 rtc@68 { 119 rtc@68 {
120 device_type = "rtc"; 120 device_type = "rtc";
@@ -127,8 +127,8 @@
127 cell-index = <0>; 127 cell-index = <0>;
128 compatible = "fsl,spi"; 128 compatible = "fsl,spi";
129 reg = <0x7000 0x1000>; 129 reg = <0x7000 0x1000>;
130 interrupts = <16 8>; 130 interrupts = <16 0x8>;
131 interrupt-parent = < &ipic >; 131 interrupt-parent = <&ipic>;
132 mode = "cpu"; 132 mode = "cpu";
133 }; 133 };
134 134
@@ -137,8 +137,8 @@
137 reg = <0x23000 0x1000>; 137 reg = <0x23000 0x1000>;
138 #address-cells = <1>; 138 #address-cells = <1>;
139 #size-cells = <0>; 139 #size-cells = <0>;
140 interrupt-parent = < &ipic >; 140 interrupt-parent = <&ipic>;
141 interrupts = <38 8>; 141 interrupts = <38 0x8>;
142 phy_type = "utmi"; 142 phy_type = "utmi";
143 }; 143 };
144 144
@@ -148,15 +148,15 @@
148 compatible = "fsl,gianfar-mdio"; 148 compatible = "fsl,gianfar-mdio";
149 reg = <0x24520 0x20>; 149 reg = <0x24520 0x20>;
150 phy0: ethernet-phy@0 { 150 phy0: ethernet-phy@0 {
151 interrupt-parent = < &ipic >; 151 interrupt-parent = <&ipic>;
152 interrupts = <20 8>; 152 interrupts = <20 0x8>;
153 reg = <0>; 153 reg = <0x0>;
154 device_type = "ethernet-phy"; 154 device_type = "ethernet-phy";
155 }; 155 };
156 phy1: ethernet-phy@1 { 156 phy1: ethernet-phy@1 {
157 interrupt-parent = < &ipic >; 157 interrupt-parent = <&ipic>;
158 interrupts = <19 8>; 158 interrupts = <19 0x8>;
159 reg = <1>; 159 reg = <0x1>;
160 device_type = "ethernet-phy"; 160 device_type = "ethernet-phy";
161 }; 161 };
162 }; 162 };
@@ -168,8 +168,8 @@
168 compatible = "gianfar"; 168 compatible = "gianfar";
169 reg = <0x24000 0x1000>; 169 reg = <0x24000 0x1000>;
170 local-mac-address = [ 00 00 00 00 00 00 ]; 170 local-mac-address = [ 00 00 00 00 00 00 ];
171 interrupts = <32 8 33 8 34 8>; 171 interrupts = <32 0x8 33 0x8 34 0x8>;
172 interrupt-parent = < &ipic >; 172 interrupt-parent = <&ipic>;
173 phy-handle = < &phy0 >; 173 phy-handle = < &phy0 >;
174 }; 174 };
175 175
@@ -180,8 +180,8 @@
180 compatible = "gianfar"; 180 compatible = "gianfar";
181 reg = <0x25000 0x1000>; 181 reg = <0x25000 0x1000>;
182 local-mac-address = [ 00 00 00 00 00 00 ]; 182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <35 8 36 8 37 8>; 183 interrupts = <35 0x8 36 0x8 37 0x8>;
184 interrupt-parent = < &ipic >; 184 interrupt-parent = <&ipic>;
185 phy-handle = < &phy1 >; 185 phy-handle = < &phy1 >;
186 }; 186 };
187 187
@@ -191,8 +191,8 @@
191 compatible = "ns16550"; 191 compatible = "ns16550";
192 reg = <0x4500 0x100>; 192 reg = <0x4500 0x100>;
193 clock-frequency = <0>; 193 clock-frequency = <0>;
194 interrupts = <9 8>; 194 interrupts = <9 0x8>;
195 interrupt-parent = < &ipic >; 195 interrupt-parent = <&ipic>;
196 }; 196 };
197 197
198 serial1: serial@4600 { 198 serial1: serial@4600 {
@@ -201,8 +201,8 @@
201 compatible = "ns16550"; 201 compatible = "ns16550";
202 reg = <0x4600 0x100>; 202 reg = <0x4600 0x100>;
203 clock-frequency = <0>; 203 clock-frequency = <0>;
204 interrupts = <10 8>; 204 interrupts = <10 0x8>;
205 interrupt-parent = < &ipic >; 205 interrupt-parent = <&ipic>;
206 }; 206 };
207 207
208 crypto@30000 { 208 crypto@30000 {
@@ -210,8 +210,8 @@
210 device_type = "crypto"; 210 device_type = "crypto";
211 compatible = "talitos"; 211 compatible = "talitos";
212 reg = <0x30000 0x10000>; 212 reg = <0x30000 0x10000>;
213 interrupts = <11 8>; 213 interrupts = <11 0x8>;
214 interrupt-parent = < &ipic >; 214 interrupt-parent = <&ipic>;
215 /* Rev. 3.0 geometry */ 215 /* Rev. 3.0 geometry */
216 num-channels = <4>; 216 num-channels = <4>;
217 channel-fifo-len = <24>; 217 channel-fifo-len = <24>;
@@ -223,16 +223,16 @@
223 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 223 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
224 reg = <0x18000 0x1000>; 224 reg = <0x18000 0x1000>;
225 cell-index = <1>; 225 cell-index = <1>;
226 interrupts = <44 8>; 226 interrupts = <44 0x8>;
227 interrupt-parent = < &ipic >; 227 interrupt-parent = <&ipic>;
228 }; 228 };
229 229
230 sata@19000 { 230 sata@19000 {
231 compatible = "fsl,mpc8315-sata", "fsl,pq-sata"; 231 compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
232 reg = <0x19000 0x1000>; 232 reg = <0x19000 0x1000>;
233 cell-index = <2>; 233 cell-index = <2>;
234 interrupts = <45 8>; 234 interrupts = <45 0x8>;
235 interrupt-parent = < &ipic >; 235 interrupt-parent = <&ipic>;
236 }; 236 };
237 237
238 /* IPIC 238 /* IPIC
@@ -251,28 +251,28 @@
251 }; 251 };
252 252
253 pci0: pci@e0008500 { 253 pci0: pci@e0008500 {
254 interrupt-map-mask = <0xf800 0 0 7>; 254 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
255 interrupt-map = < 255 interrupt-map = <
256 /* IDSEL 0x0E -mini PCI */ 256 /* IDSEL 0x0E -mini PCI */
257 0x7000 0 0 1 &ipic 18 8 257 0x7000 0x0 0x0 0x1 &ipic 18 0x8
258 0x7000 0 0 2 &ipic 18 8 258 0x7000 0x0 0x0 0x2 &ipic 18 0x8
259 0x7000 0 0 3 &ipic 18 8 259 0x7000 0x0 0x0 0x3 &ipic 18 0x8
260 0x7000 0 0 4 &ipic 18 8 260 0x7000 0x0 0x0 0x4 &ipic 18 0x8
261 261
262 /* IDSEL 0x0F -mini PCI */ 262 /* IDSEL 0x0F -mini PCI */
263 0x7800 0 0 1 &ipic 17 8 263 0x7800 0x0 0x0 0x1 &ipic 17 0x8
264 0x7800 0 0 2 &ipic 17 8 264 0x7800 0x0 0x0 0x2 &ipic 17 0x8
265 0x7800 0 0 3 &ipic 17 8 265 0x7800 0x0 0x0 0x3 &ipic 17 0x8
266 0x7800 0 0 4 &ipic 17 8 266 0x7800 0x0 0x0 0x4 &ipic 17 0x8
267 267
268 /* IDSEL 0x10 - PCI slot */ 268 /* IDSEL 0x10 - PCI slot */
269 0x8000 0 0 1 &ipic 48 8 269 0x8000 0x0 0x0 0x1 &ipic 48 0x8
270 0x8000 0 0 2 &ipic 17 8 270 0x8000 0x0 0x0 0x2 &ipic 17 0x8
271 0x8000 0 0 3 &ipic 48 8 271 0x8000 0x0 0x0 0x3 &ipic 48 0x8
272 0x8000 0 0 4 &ipic 17 8>; 272 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
273 interrupt-parent = < &ipic >; 273 interrupt-parent = <&ipic>;
274 interrupts = <66 8>; 274 interrupts = <66 0x8>;
275 bus-range = <0 0>; 275 bus-range = <0x0 0x0>;
276 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 276 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
277 0x42000000 0 0x80000000 0x80000000 0 0x10000000 277 0x42000000 0 0x80000000 0x80000000 0 0x10000000
278 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>; 278 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 7c3c52cea75c..9bb408371bcd 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -21,6 +21,8 @@
21 * you're going by the schematic, the pin is called "P19J-K22". 21 * you're going by the schematic, the pin is called "P19J-K22".
22 */ 22 */
23 23
24/dts-v1/;
25
24/ { 26/ {
25 model = "MPC8323EMDS"; 27 model = "MPC8323EMDS";
26 compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS"; 28 compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
@@ -41,11 +43,11 @@
41 43
42 PowerPC,8323@0 { 44 PowerPC,8323@0 {
43 device_type = "cpu"; 45 device_type = "cpu";
44 reg = <0>; 46 reg = <0x0>;
45 d-cache-line-size = <20>; // 32 bytes 47 d-cache-line-size = <32>; // 32 bytes
46 i-cache-line-size = <20>; // 32 bytes 48 i-cache-line-size = <32>; // 32 bytes
47 d-cache-size = <4000>; // L1, 16K 49 d-cache-size = <16384>; // L1, 16K
48 i-cache-size = <4000>; // L1, 16K 50 i-cache-size = <16384>; // L1, 16K
49 timebase-frequency = <0>; 51 timebase-frequency = <0>;
50 bus-frequency = <0>; 52 bus-frequency = <0>;
51 clock-frequency = <0>; 53 clock-frequency = <0>;
@@ -54,26 +56,26 @@
54 56
55 memory { 57 memory {
56 device_type = "memory"; 58 device_type = "memory";
57 reg = <00000000 08000000>; 59 reg = <0x00000000 0x08000000>;
58 }; 60 };
59 61
60 bcsr@f8000000 { 62 bcsr@f8000000 {
61 device_type = "board-control"; 63 device_type = "board-control";
62 reg = <f8000000 8000>; 64 reg = <0xf8000000 0x8000>;
63 }; 65 };
64 66
65 soc8323@e0000000 { 67 soc8323@e0000000 {
66 #address-cells = <1>; 68 #address-cells = <1>;
67 #size-cells = <1>; 69 #size-cells = <1>;
68 device_type = "soc"; 70 device_type = "soc";
69 ranges = <0 e0000000 00100000>; 71 ranges = <0x0 0xe0000000 0x00100000>;
70 reg = <e0000000 00000200>; 72 reg = <0xe0000000 0x00000200>;
71 bus-frequency = <7DE2900>; 73 bus-frequency = <132000000>;
72 74
73 wdt@200 { 75 wdt@200 {
74 device_type = "watchdog"; 76 device_type = "watchdog";
75 compatible = "mpc83xx_wdt"; 77 compatible = "mpc83xx_wdt";
76 reg = <200 100>; 78 reg = <0x200 0x100>;
77 }; 79 };
78 80
79 i2c@3000 { 81 i2c@3000 {
@@ -81,14 +83,14 @@
81 #size-cells = <0>; 83 #size-cells = <0>;
82 cell-index = <0>; 84 cell-index = <0>;
83 compatible = "fsl-i2c"; 85 compatible = "fsl-i2c";
84 reg = <3000 100>; 86 reg = <0x3000 0x100>;
85 interrupts = <e 8>; 87 interrupts = <14 0x8>;
86 interrupt-parent = < &ipic >; 88 interrupt-parent = <&ipic>;
87 dfsrr; 89 dfsrr;
88 90
89 rtc@68 { 91 rtc@68 {
90 compatible = "dallas,ds1374"; 92 compatible = "dallas,ds1374";
91 reg = <68>; 93 reg = <0x68>;
92 }; 94 };
93 }; 95 };
94 96
@@ -96,46 +98,46 @@
96 cell-index = <0>; 98 cell-index = <0>;
97 device_type = "serial"; 99 device_type = "serial";
98 compatible = "ns16550"; 100 compatible = "ns16550";
99 reg = <4500 100>; 101 reg = <0x4500 0x100>;
100 clock-frequency = <0>; 102 clock-frequency = <0>;
101 interrupts = <9 8>; 103 interrupts = <9 0x8>;
102 interrupt-parent = < &ipic >; 104 interrupt-parent = <&ipic>;
103 }; 105 };
104 106
105 serial1: serial@4600 { 107 serial1: serial@4600 {
106 cell-index = <1>; 108 cell-index = <1>;
107 device_type = "serial"; 109 device_type = "serial";
108 compatible = "ns16550"; 110 compatible = "ns16550";
109 reg = <4600 100>; 111 reg = <0x4600 0x100>;
110 clock-frequency = <0>; 112 clock-frequency = <0>;
111 interrupts = <a 8>; 113 interrupts = <10 0x8>;
112 interrupt-parent = < &ipic >; 114 interrupt-parent = <&ipic>;
113 }; 115 };
114 116
115 crypto@30000 { 117 crypto@30000 {
116 device_type = "crypto"; 118 device_type = "crypto";
117 model = "SEC2"; 119 model = "SEC2";
118 compatible = "talitos"; 120 compatible = "talitos";
119 reg = <30000 7000>; 121 reg = <0x30000 0x7000>;
120 interrupts = <b 8>; 122 interrupts = <11 0x8>;
121 interrupt-parent = < &ipic >; 123 interrupt-parent = <&ipic>;
122 /* Rev. 2.2 */ 124 /* Rev. 2.2 */
123 num-channels = <1>; 125 num-channels = <1>;
124 channel-fifo-len = <18>; 126 channel-fifo-len = <24>;
125 exec-units-mask = <0000004c>; 127 exec-units-mask = <0x0000004c>;
126 descriptor-types-mask = <0122003f>; 128 descriptor-types-mask = <0x0122003f>;
127 }; 129 };
128 130
129 ipic: pic@700 { 131 ipic: pic@700 {
130 interrupt-controller; 132 interrupt-controller;
131 #address-cells = <0>; 133 #address-cells = <0>;
132 #interrupt-cells = <2>; 134 #interrupt-cells = <2>;
133 reg = <700 100>; 135 reg = <0x700 0x100>;
134 device_type = "ipic"; 136 device_type = "ipic";
135 }; 137 };
136 138
137 par_io@1400 { 139 par_io@1400 {
138 reg = <1400 100>; 140 reg = <0x1400 0x100>;
139 device_type = "par_io"; 141 device_type = "par_io";
140 num-ports = <7>; 142 num-ports = <7>;
141 143
@@ -144,8 +146,8 @@
144 /* port pin dir open_drain assignment has_irq */ 146 /* port pin dir open_drain assignment has_irq */
145 3 4 3 0 2 0 /* MDIO */ 147 3 4 3 0 2 0 /* MDIO */
146 3 5 1 0 2 0 /* MDC */ 148 3 5 1 0 2 0 /* MDC */
147 0 d 2 0 1 0 /* RX_CLK (CLK9) */ 149 0 13 2 0 1 0 /* RX_CLK (CLK9) */
148 3 18 2 0 1 0 /* TX_CLK (CLK10) */ 150 3 24 2 0 1 0 /* TX_CLK (CLK10) */
149 1 0 1 0 1 0 /* TxD0 */ 151 1 0 1 0 1 0 /* TxD0 */
150 1 1 1 0 1 0 /* TxD1 */ 152 1 1 1 0 1 0 /* TxD1 */
151 1 2 1 0 1 0 /* TxD2 */ 153 1 2 1 0 1 0 /* TxD2 */
@@ -156,30 +158,30 @@
156 1 7 2 0 1 0 /* RxD3 */ 158 1 7 2 0 1 0 /* RxD3 */
157 1 8 2 0 1 0 /* RX_ER */ 159 1 8 2 0 1 0 /* RX_ER */
158 1 9 1 0 1 0 /* TX_ER */ 160 1 9 1 0 1 0 /* TX_ER */
159 1 a 2 0 1 0 /* RX_DV */ 161 1 10 2 0 1 0 /* RX_DV */
160 1 b 2 0 1 0 /* COL */ 162 1 11 2 0 1 0 /* COL */
161 1 c 1 0 1 0 /* TX_EN */ 163 1 12 1 0 1 0 /* TX_EN */
162 1 d 2 0 1 0>;/* CRS */ 164 1 13 2 0 1 0>; /* CRS */
163 }; 165 };
164 pio4: ucc_pin@04 { 166 pio4: ucc_pin@04 {
165 pio-map = < 167 pio-map = <
166 /* port pin dir open_drain assignment has_irq */ 168 /* port pin dir open_drain assignment has_irq */
167 3 1f 2 0 1 0 /* RX_CLK (CLK7) */ 169 3 31 2 0 1 0 /* RX_CLK (CLK7) */
168 3 6 2 0 1 0 /* TX_CLK (CLK8) */ 170 3 6 2 0 1 0 /* TX_CLK (CLK8) */
169 1 12 1 0 1 0 /* TxD0 */ 171 1 18 1 0 1 0 /* TxD0 */
170 1 13 1 0 1 0 /* TxD1 */ 172 1 19 1 0 1 0 /* TxD1 */
171 1 14 1 0 1 0 /* TxD2 */ 173 1 20 1 0 1 0 /* TxD2 */
172 1 15 1 0 1 0 /* TxD3 */ 174 1 21 1 0 1 0 /* TxD3 */
173 1 16 2 0 1 0 /* RxD0 */ 175 1 22 2 0 1 0 /* RxD0 */
174 1 17 2 0 1 0 /* RxD1 */ 176 1 23 2 0 1 0 /* RxD1 */
175 1 18 2 0 1 0 /* RxD2 */ 177 1 24 2 0 1 0 /* RxD2 */
176 1 19 2 0 1 0 /* RxD3 */ 178 1 25 2 0 1 0 /* RxD3 */
177 1 1a 2 0 1 0 /* RX_ER */ 179 1 26 2 0 1 0 /* RX_ER */
178 1 1b 1 0 1 0 /* TX_ER */ 180 1 27 1 0 1 0 /* TX_ER */
179 1 1c 2 0 1 0 /* RX_DV */ 181 1 28 2 0 1 0 /* RX_DV */
180 1 1d 2 0 1 0 /* COL */ 182 1 29 2 0 1 0 /* COL */
181 1 1e 1 0 1 0 /* TX_EN */ 183 1 30 1 0 1 0 /* TX_EN */
182 1 1f 2 0 1 0>;/* CRS */ 184 1 31 2 0 1 0>; /* CRS */
183 }; 185 };
184 pio5: ucc_pin@05 { 186 pio5: ucc_pin@05 {
185 pio-map = < 187 pio-map = <
@@ -190,10 +192,10 @@
190 2 0 1 0 2 0 /* TxD5 */ 192 2 0 1 0 2 0 /* TxD5 */
191 2 8 2 0 2 0 /* RxD5 */ 193 2 8 2 0 2 0 /* RxD5 */
192 194
193 2 1d 2 0 0 0 /* CTS5 */ 195 2 29 2 0 0 0 /* CTS5 */
194 2 1f 1 0 2 0 /* RTS5 */ 196 2 31 1 0 2 0 /* RTS5 */
195 197
196 2 18 2 0 0 0 /* CD */ 198 2 24 2 0 0 0 /* CD */
197 199
198 >; 200 >;
199 }; 201 };
@@ -206,47 +208,47 @@
206 #size-cells = <1>; 208 #size-cells = <1>;
207 device_type = "qe"; 209 device_type = "qe";
208 compatible = "fsl,qe"; 210 compatible = "fsl,qe";
209 ranges = <0 e0100000 00100000>; 211 ranges = <0x0 0xe0100000 0x00100000>;
210 reg = <e0100000 480>; 212 reg = <0xe0100000 0x480>;
211 brg-frequency = <0>; 213 brg-frequency = <0>;
212 bus-frequency = <BCD3D80>; 214 bus-frequency = <198000000>;
213 215
214 muram@10000 { 216 muram@10000 {
215 #address-cells = <1>; 217 #address-cells = <1>;
216 #size-cells = <1>; 218 #size-cells = <1>;
217 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 219 compatible = "fsl,qe-muram", "fsl,cpm-muram";
218 ranges = <0 00010000 00004000>; 220 ranges = <0x0 0x00010000 0x00004000>;
219 221
220 data-only@0 { 222 data-only@0 {
221 compatible = "fsl,qe-muram-data", 223 compatible = "fsl,qe-muram-data",
222 "fsl,cpm-muram-data"; 224 "fsl,cpm-muram-data";
223 reg = <0 4000>; 225 reg = <0x0 0x4000>;
224 }; 226 };
225 }; 227 };
226 228
227 spi@4c0 { 229 spi@4c0 {
228 cell-index = <0>; 230 cell-index = <0>;
229 compatible = "fsl,spi"; 231 compatible = "fsl,spi";
230 reg = <4c0 40>; 232 reg = <0x4c0 0x40>;
231 interrupts = <2>; 233 interrupts = <2>;
232 interrupt-parent = < &qeic >; 234 interrupt-parent = <&qeic>;
233 mode = "cpu"; 235 mode = "cpu";
234 }; 236 };
235 237
236 spi@500 { 238 spi@500 {
237 cell-index = <1>; 239 cell-index = <1>;
238 compatible = "fsl,spi"; 240 compatible = "fsl,spi";
239 reg = <500 40>; 241 reg = <0x500 0x40>;
240 interrupts = <1>; 242 interrupts = <1>;
241 interrupt-parent = < &qeic >; 243 interrupt-parent = <&qeic>;
242 mode = "cpu"; 244 mode = "cpu";
243 }; 245 };
244 246
245 usb@6c0 { 247 usb@6c0 {
246 compatible = "qe_udc"; 248 compatible = "qe_udc";
247 reg = <6c0 40 8B00 100>; 249 reg = <0x6c0 0x40 0x8b00 0x100>;
248 interrupts = <b>; 250 interrupts = <11>;
249 interrupt-parent = < &qeic >; 251 interrupt-parent = <&qeic>;
250 mode = "slave"; 252 mode = "slave";
251 }; 253 };
252 254
@@ -256,14 +258,14 @@
256 model = "UCC"; 258 model = "UCC";
257 cell-index = <3>; 259 cell-index = <3>;
258 device-id = <3>; 260 device-id = <3>;
259 reg = <2200 200>; 261 reg = <0x2200 0x200>;
260 interrupts = <22>; 262 interrupts = <34>;
261 interrupt-parent = < &qeic >; 263 interrupt-parent = <&qeic>;
262 local-mac-address = [ 00 00 00 00 00 00 ]; 264 local-mac-address = [ 00 00 00 00 00 00 ];
263 rx-clock-name = "clk9"; 265 rx-clock-name = "clk9";
264 tx-clock-name = "clk10"; 266 tx-clock-name = "clk10";
265 phy-handle = < &phy3 >; 267 phy-handle = <&phy3>;
266 pio-handle = < &pio3 >; 268 pio-handle = <&pio3>;
267 }; 269 };
268 270
269 enet1: ucc@3200 { 271 enet1: ucc@3200 {
@@ -272,14 +274,14 @@
272 model = "UCC"; 274 model = "UCC";
273 cell-index = <4>; 275 cell-index = <4>;
274 device-id = <4>; 276 device-id = <4>;
275 reg = <3200 200>; 277 reg = <0x3200 0x200>;
276 interrupts = <23>; 278 interrupts = <35>;
277 interrupt-parent = < &qeic >; 279 interrupt-parent = <&qeic>;
278 local-mac-address = [ 00 00 00 00 00 00 ]; 280 local-mac-address = [ 00 00 00 00 00 00 ];
279 rx-clock-name = "clk7"; 281 rx-clock-name = "clk7";
280 tx-clock-name = "clk8"; 282 tx-clock-name = "clk8";
281 phy-handle = < &phy4 >; 283 phy-handle = <&phy4>;
282 pio-handle = < &pio4 >; 284 pio-handle = <&pio4>;
283 }; 285 };
284 286
285 ucc@2400 { 287 ucc@2400 {
@@ -289,8 +291,8 @@
289 device-id = <5>; /* The UCC number, 1-7*/ 291 device-id = <5>; /* The UCC number, 1-7*/
290 port-number = <0>; /* Which ttyQEx device */ 292 port-number = <0>; /* Which ttyQEx device */
291 soft-uart; /* We need Soft-UART */ 293 soft-uart; /* We need Soft-UART */
292 reg = <2400 200>; 294 reg = <0x2400 0x200>;
293 interrupts = <28>; /* From Table 18-12 */ 295 interrupts = <40>; /* From Table 18-12 */
294 interrupt-parent = < &qeic >; 296 interrupt-parent = < &qeic >;
295 /* 297 /*
296 * For Soft-UART, we need to set TX to 1X, which 298 * For Soft-UART, we need to set TX to 1X, which
@@ -305,19 +307,19 @@
305 mdio@2320 { 307 mdio@2320 {
306 #address-cells = <1>; 308 #address-cells = <1>;
307 #size-cells = <0>; 309 #size-cells = <0>;
308 reg = <2320 18>; 310 reg = <0x2320 0x18>;
309 compatible = "fsl,ucc-mdio"; 311 compatible = "fsl,ucc-mdio";
310 312
311 phy3: ethernet-phy@03 { 313 phy3: ethernet-phy@03 {
312 interrupt-parent = < &ipic >; 314 interrupt-parent = <&ipic>;
313 interrupts = <11 8>; 315 interrupts = <17 0x8>;
314 reg = <3>; 316 reg = <0x3>;
315 device_type = "ethernet-phy"; 317 device_type = "ethernet-phy";
316 }; 318 };
317 phy4: ethernet-phy@04 { 319 phy4: ethernet-phy@04 {
318 interrupt-parent = < &ipic >; 320 interrupt-parent = <&ipic>;
319 interrupts = <12 8>; 321 interrupts = <18 0x8>;
320 reg = <4>; 322 reg = <0x4>;
321 device_type = "ethernet-phy"; 323 device_type = "ethernet-phy";
322 }; 324 };
323 }; 325 };
@@ -327,69 +329,69 @@
327 compatible = "fsl,qe-ic"; 329 compatible = "fsl,qe-ic";
328 #address-cells = <0>; 330 #address-cells = <0>;
329 #interrupt-cells = <1>; 331 #interrupt-cells = <1>;
330 reg = <80 80>; 332 reg = <0x80 0x80>;
331 big-endian; 333 big-endian;
332 interrupts = <20 8 21 8>; //high:32 low:33 334 interrupts = <32 0x8 33 0x8>; //high:32 low:33
333 interrupt-parent = < &ipic >; 335 interrupt-parent = <&ipic>;
334 }; 336 };
335 }; 337 };
336 338
337 pci0: pci@e0008500 { 339 pci0: pci@e0008500 {
338 cell-index = <1>; 340 cell-index = <1>;
339 interrupt-map-mask = <f800 0 0 7>; 341 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
340 interrupt-map = < 342 interrupt-map = <
341 /* IDSEL 0x11 AD17 */ 343 /* IDSEL 0x11 AD17 */
342 8800 0 0 1 &ipic 14 8 344 0x8800 0x0 0x0 0x1 &ipic 20 0x8
343 8800 0 0 2 &ipic 15 8 345 0x8800 0x0 0x0 0x2 &ipic 21 0x8
344 8800 0 0 3 &ipic 16 8 346 0x8800 0x0 0x0 0x3 &ipic 22 0x8
345 8800 0 0 4 &ipic 17 8 347 0x8800 0x0 0x0 0x4 &ipic 23 0x8
346 348
347 /* IDSEL 0x12 AD18 */ 349 /* IDSEL 0x12 AD18 */
348 9000 0 0 1 &ipic 16 8 350 0x9000 0x0 0x0 0x1 &ipic 22 0x8
349 9000 0 0 2 &ipic 17 8 351 0x9000 0x0 0x0 0x2 &ipic 23 0x8
350 9000 0 0 3 &ipic 14 8 352 0x9000 0x0 0x0 0x3 &ipic 20 0x8
351 9000 0 0 4 &ipic 15 8 353 0x9000 0x0 0x0 0x4 &ipic 21 0x8
352 354
353 /* IDSEL 0x13 AD19 */ 355 /* IDSEL 0x13 AD19 */
354 9800 0 0 1 &ipic 17 8 356 0x9800 0x0 0x0 0x1 &ipic 23 0x8
355 9800 0 0 2 &ipic 14 8 357 0x9800 0x0 0x0 0x2 &ipic 20 0x8
356 9800 0 0 3 &ipic 15 8 358 0x9800 0x0 0x0 0x3 &ipic 21 0x8
357 9800 0 0 4 &ipic 16 8 359 0x9800 0x0 0x0 0x4 &ipic 22 0x8
358 360
359 /* IDSEL 0x15 AD21*/ 361 /* IDSEL 0x15 AD21*/
360 a800 0 0 1 &ipic 14 8 362 0xa800 0x0 0x0 0x1 &ipic 20 0x8
361 a800 0 0 2 &ipic 15 8 363 0xa800 0x0 0x0 0x2 &ipic 21 0x8
362 a800 0 0 3 &ipic 16 8 364 0xa800 0x0 0x0 0x3 &ipic 22 0x8
363 a800 0 0 4 &ipic 17 8 365 0xa800 0x0 0x0 0x4 &ipic 23 0x8
364 366
365 /* IDSEL 0x16 AD22*/ 367 /* IDSEL 0x16 AD22*/
366 b000 0 0 1 &ipic 17 8 368 0xb000 0x0 0x0 0x1 &ipic 23 0x8
367 b000 0 0 2 &ipic 14 8 369 0xb000 0x0 0x0 0x2 &ipic 20 0x8
368 b000 0 0 3 &ipic 15 8 370 0xb000 0x0 0x0 0x3 &ipic 21 0x8
369 b000 0 0 4 &ipic 16 8 371 0xb000 0x0 0x0 0x4 &ipic 22 0x8
370 372
371 /* IDSEL 0x17 AD23*/ 373 /* IDSEL 0x17 AD23*/
372 b800 0 0 1 &ipic 16 8 374 0xb800 0x0 0x0 0x1 &ipic 22 0x8
373 b800 0 0 2 &ipic 17 8 375 0xb800 0x0 0x0 0x2 &ipic 23 0x8
374 b800 0 0 3 &ipic 14 8 376 0xb800 0x0 0x0 0x3 &ipic 20 0x8
375 b800 0 0 4 &ipic 15 8 377 0xb800 0x0 0x0 0x4 &ipic 21 0x8
376 378
377 /* IDSEL 0x18 AD24*/ 379 /* IDSEL 0x18 AD24*/
378 c000 0 0 1 &ipic 15 8 380 0xc000 0x0 0x0 0x1 &ipic 21 0x8
379 c000 0 0 2 &ipic 16 8 381 0xc000 0x0 0x0 0x2 &ipic 22 0x8
380 c000 0 0 3 &ipic 17 8 382 0xc000 0x0 0x0 0x3 &ipic 23 0x8
381 c000 0 0 4 &ipic 14 8>; 383 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
382 interrupt-parent = < &ipic >; 384 interrupt-parent = <&ipic>;
383 interrupts = <42 8>; 385 interrupts = <66 0x8>;
384 bus-range = <0 0>; 386 bus-range = <0x0 0x0>;
385 ranges = <02000000 0 90000000 90000000 0 10000000 387 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
386 42000000 0 80000000 80000000 0 10000000 388 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
387 01000000 0 00000000 d0000000 0 00100000>; 389 0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
388 clock-frequency = <0>; 390 clock-frequency = <0>;
389 #interrupt-cells = <1>; 391 #interrupt-cells = <1>;
390 #size-cells = <2>; 392 #size-cells = <2>;
391 #address-cells = <3>; 393 #address-cells = <3>;
392 reg = <e0008500 100>; 394 reg = <0xe0008500 0x100>;
393 compatible = "fsl,mpc8349-pci"; 395 compatible = "fsl,mpc8349-pci";
394 device_type = "pci"; 396 device_type = "pci";
395 }; 397 };
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 551fc595075a..94f93d209de8 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -9,6 +9,8 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
13
12/ { 14/ {
13 model = "MPC8323ERDB"; 15 model = "MPC8323ERDB";
14 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB"; 16 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
@@ -29,11 +31,11 @@
29 31
30 PowerPC,8323@0 { 32 PowerPC,8323@0 {
31 device_type = "cpu"; 33 device_type = "cpu";
32 reg = <0>; 34 reg = <0x0>;
33 d-cache-line-size = <20>; // 32 bytes 35 d-cache-line-size = <0x20>; // 32 bytes
34 i-cache-line-size = <20>; // 32 bytes 36 i-cache-line-size = <0x20>; // 32 bytes
35 d-cache-size = <4000>; // L1, 16K 37 d-cache-size = <16384>; // L1, 16K
36 i-cache-size = <4000>; // L1, 16K 38 i-cache-size = <16384>; // L1, 16K
37 timebase-frequency = <0>; 39 timebase-frequency = <0>;
38 bus-frequency = <0>; 40 bus-frequency = <0>;
39 clock-frequency = <0>; 41 clock-frequency = <0>;
@@ -42,21 +44,21 @@
42 44
43 memory { 45 memory {
44 device_type = "memory"; 46 device_type = "memory";
45 reg = <00000000 04000000>; 47 reg = <0x00000000 0x04000000>;
46 }; 48 };
47 49
48 soc8323@e0000000 { 50 soc8323@e0000000 {
49 #address-cells = <1>; 51 #address-cells = <1>;
50 #size-cells = <1>; 52 #size-cells = <1>;
51 device_type = "soc"; 53 device_type = "soc";
52 ranges = <0 e0000000 00100000>; 54 ranges = <0x0 0xe0000000 0x00100000>;
53 reg = <e0000000 00000200>; 55 reg = <0xe0000000 0x00000200>;
54 bus-frequency = <0>; 56 bus-frequency = <0>;
55 57
56 wdt@200 { 58 wdt@200 {
57 device_type = "watchdog"; 59 device_type = "watchdog";
58 compatible = "mpc83xx_wdt"; 60 compatible = "mpc83xx_wdt";
59 reg = <200 100>; 61 reg = <0x200 0x100>;
60 }; 62 };
61 63
62 i2c@3000 { 64 i2c@3000 {
@@ -64,8 +66,8 @@
64 #size-cells = <0>; 66 #size-cells = <0>;
65 cell-index = <0>; 67 cell-index = <0>;
66 compatible = "fsl-i2c"; 68 compatible = "fsl-i2c";
67 reg = <3000 100>; 69 reg = <0x3000 0x100>;
68 interrupts = <e 8>; 70 interrupts = <14 0x8>;
69 interrupt-parent = <&pic>; 71 interrupt-parent = <&pic>;
70 dfsrr; 72 dfsrr;
71 }; 73 };
@@ -74,9 +76,9 @@
74 cell-index = <0>; 76 cell-index = <0>;
75 device_type = "serial"; 77 device_type = "serial";
76 compatible = "ns16550"; 78 compatible = "ns16550";
77 reg = <4500 100>; 79 reg = <0x4500 0x100>;
78 clock-frequency = <0>; 80 clock-frequency = <0>;
79 interrupts = <9 8>; 81 interrupts = <9 0x8>;
80 interrupt-parent = <&pic>; 82 interrupt-parent = <&pic>;
81 }; 83 };
82 84
@@ -84,9 +86,9 @@
84 cell-index = <1>; 86 cell-index = <1>;
85 device_type = "serial"; 87 device_type = "serial";
86 compatible = "ns16550"; 88 compatible = "ns16550";
87 reg = <4600 100>; 89 reg = <0x4600 0x100>;
88 clock-frequency = <0>; 90 clock-frequency = <0>;
89 interrupts = <a 8>; 91 interrupts = <10 0x8>;
90 interrupt-parent = <&pic>; 92 interrupt-parent = <&pic>;
91 }; 93 };
92 94
@@ -94,26 +96,26 @@
94 device_type = "crypto"; 96 device_type = "crypto";
95 model = "SEC2"; 97 model = "SEC2";
96 compatible = "talitos"; 98 compatible = "talitos";
97 reg = <30000 7000>; 99 reg = <0x30000 0x7000>;
98 interrupts = <b 8>; 100 interrupts = <11 0x8>;
99 interrupt-parent = <&pic>; 101 interrupt-parent = <&pic>;
100 /* Rev. 2.2 */ 102 /* Rev. 2.2 */
101 num-channels = <1>; 103 num-channels = <1>;
102 channel-fifo-len = <18>; 104 channel-fifo-len = <24>;
103 exec-units-mask = <0000004c>; 105 exec-units-mask = <0x0000004c>;
104 descriptor-types-mask = <0122003f>; 106 descriptor-types-mask = <0x0122003f>;
105 }; 107 };
106 108
107 pic:pic@700 { 109 pic:pic@700 {
108 interrupt-controller; 110 interrupt-controller;
109 #address-cells = <0>; 111 #address-cells = <0>;
110 #interrupt-cells = <2>; 112 #interrupt-cells = <2>;
111 reg = <700 100>; 113 reg = <0x700 0x100>;
112 device_type = "ipic"; 114 device_type = "ipic";
113 }; 115 };
114 116
115 par_io@1400 { 117 par_io@1400 {
116 reg = <1400 100>; 118 reg = <0x1400 0x100>;
117 device_type = "par_io"; 119 device_type = "par_io";
118 num-ports = <7>; 120 num-ports = <7>;
119 121
@@ -122,28 +124,28 @@
122 /* port pin dir open_drain assignment has_irq */ 124 /* port pin dir open_drain assignment has_irq */
123 3 4 3 0 2 0 /* MDIO */ 125 3 4 3 0 2 0 /* MDIO */
124 3 5 1 0 2 0 /* MDC */ 126 3 5 1 0 2 0 /* MDC */
125 3 15 2 0 1 0 /* RX_CLK (CLK16) */ 127 3 21 2 0 1 0 /* RX_CLK (CLK16) */
126 3 17 2 0 1 0 /* TX_CLK (CLK3) */ 128 3 23 2 0 1 0 /* TX_CLK (CLK3) */
127 0 12 1 0 1 0 /* TxD0 */ 129 0 18 1 0 1 0 /* TxD0 */
128 0 13 1 0 1 0 /* TxD1 */ 130 0 19 1 0 1 0 /* TxD1 */
129 0 14 1 0 1 0 /* TxD2 */ 131 0 20 1 0 1 0 /* TxD2 */
130 0 15 1 0 1 0 /* TxD3 */ 132 0 21 1 0 1 0 /* TxD3 */
131 0 16 2 0 1 0 /* RxD0 */ 133 0 22 2 0 1 0 /* RxD0 */
132 0 17 2 0 1 0 /* RxD1 */ 134 0 23 2 0 1 0 /* RxD1 */
133 0 18 2 0 1 0 /* RxD2 */ 135 0 24 2 0 1 0 /* RxD2 */
134 0 19 2 0 1 0 /* RxD3 */ 136 0 25 2 0 1 0 /* RxD3 */
135 0 1a 2 0 1 0 /* RX_ER */ 137 0 26 2 0 1 0 /* RX_ER */
136 0 1b 1 0 1 0 /* TX_ER */ 138 0 27 1 0 1 0 /* TX_ER */
137 0 1c 2 0 1 0 /* RX_DV */ 139 0 28 2 0 1 0 /* RX_DV */
138 0 1d 2 0 1 0 /* COL */ 140 0 29 2 0 1 0 /* COL */
139 0 1e 1 0 1 0 /* TX_EN */ 141 0 30 1 0 1 0 /* TX_EN */
140 0 1f 2 0 1 0>; /* CRS */ 142 0 31 2 0 1 0>; /* CRS */
141 }; 143 };
142 ucc3pio:ucc_pin@03 { 144 ucc3pio:ucc_pin@03 {
143 pio-map = < 145 pio-map = <
144 /* port pin dir open_drain assignment has_irq */ 146 /* port pin dir open_drain assignment has_irq */
145 0 d 2 0 1 0 /* RX_CLK (CLK9) */ 147 0 13 2 0 1 0 /* RX_CLK (CLK9) */
146 3 18 2 0 1 0 /* TX_CLK (CLK10) */ 148 3 24 2 0 1 0 /* TX_CLK (CLK10) */
147 1 0 1 0 1 0 /* TxD0 */ 149 1 0 1 0 1 0 /* TxD0 */
148 1 1 1 0 1 0 /* TxD1 */ 150 1 1 1 0 1 0 /* TxD1 */
149 1 2 1 0 1 0 /* TxD2 */ 151 1 2 1 0 1 0 /* TxD2 */
@@ -154,10 +156,10 @@
154 1 7 2 0 1 0 /* RxD3 */ 156 1 7 2 0 1 0 /* RxD3 */
155 1 8 2 0 1 0 /* RX_ER */ 157 1 8 2 0 1 0 /* RX_ER */
156 1 9 1 0 1 0 /* TX_ER */ 158 1 9 1 0 1 0 /* TX_ER */
157 1 a 2 0 1 0 /* RX_DV */ 159 1 10 2 0 1 0 /* RX_DV */
158 1 b 2 0 1 0 /* COL */ 160 1 11 2 0 1 0 /* COL */
159 1 c 1 0 1 0 /* TX_EN */ 161 1 12 1 0 1 0 /* TX_EN */
160 1 d 2 0 1 0>; /* CRS */ 162 1 13 2 0 1 0>; /* CRS */
161 }; 163 };
162 }; 164 };
163 }; 165 };
@@ -167,28 +169,28 @@
167 #size-cells = <1>; 169 #size-cells = <1>;
168 device_type = "qe"; 170 device_type = "qe";
169 compatible = "fsl,qe"; 171 compatible = "fsl,qe";
170 ranges = <0 e0100000 00100000>; 172 ranges = <0x0 0xe0100000 0x00100000>;
171 reg = <e0100000 480>; 173 reg = <0xe0100000 0x480>;
172 brg-frequency = <0>; 174 brg-frequency = <0>;
173 bus-frequency = <BCD3D80>; 175 bus-frequency = <198000000>;
174 176
175 muram@10000 { 177 muram@10000 {
176 #address-cells = <1>; 178 #address-cells = <1>;
177 #size-cells = <1>; 179 #size-cells = <1>;
178 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 180 compatible = "fsl,qe-muram", "fsl,cpm-muram";
179 ranges = <0 00010000 00004000>; 181 ranges = <0x0 0x00010000 0x00004000>;
180 182
181 data-only@0 { 183 data-only@0 {
182 compatible = "fsl,qe-muram-data", 184 compatible = "fsl,qe-muram-data",
183 "fsl,cpm-muram-data"; 185 "fsl,cpm-muram-data";
184 reg = <0 4000>; 186 reg = <0x0 0x4000>;
185 }; 187 };
186 }; 188 };
187 189
188 spi@4c0 { 190 spi@4c0 {
189 cell-index = <0>; 191 cell-index = <0>;
190 compatible = "fsl,spi"; 192 compatible = "fsl,spi";
191 reg = <4c0 40>; 193 reg = <0x4c0 0x40>;
192 interrupts = <2>; 194 interrupts = <2>;
193 interrupt-parent = <&qeic>; 195 interrupt-parent = <&qeic>;
194 mode = "cpu-qe"; 196 mode = "cpu-qe";
@@ -197,7 +199,7 @@
197 spi@500 { 199 spi@500 {
198 cell-index = <1>; 200 cell-index = <1>;
199 compatible = "fsl,spi"; 201 compatible = "fsl,spi";
200 reg = <500 40>; 202 reg = <0x500 0x40>;
201 interrupts = <1>; 203 interrupts = <1>;
202 interrupt-parent = <&qeic>; 204 interrupt-parent = <&qeic>;
203 mode = "cpu"; 205 mode = "cpu";
@@ -209,8 +211,8 @@
209 model = "UCC"; 211 model = "UCC";
210 cell-index = <2>; 212 cell-index = <2>;
211 device-id = <2>; 213 device-id = <2>;
212 reg = <3000 200>; 214 reg = <0x3000 0x200>;
213 interrupts = <21>; 215 interrupts = <33>;
214 interrupt-parent = <&qeic>; 216 interrupt-parent = <&qeic>;
215 local-mac-address = [ 00 00 00 00 00 00 ]; 217 local-mac-address = [ 00 00 00 00 00 00 ];
216 rx-clock-name = "clk16"; 218 rx-clock-name = "clk16";
@@ -225,8 +227,8 @@
225 model = "UCC"; 227 model = "UCC";
226 cell-index = <3>; 228 cell-index = <3>;
227 device-id = <3>; 229 device-id = <3>;
228 reg = <2200 200>; 230 reg = <0x2200 0x200>;
229 interrupts = <22>; 231 interrupts = <34>;
230 interrupt-parent = <&qeic>; 232 interrupt-parent = <&qeic>;
231 local-mac-address = [ 00 00 00 00 00 00 ]; 233 local-mac-address = [ 00 00 00 00 00 00 ];
232 rx-clock-name = "clk9"; 234 rx-clock-name = "clk9";
@@ -238,19 +240,19 @@
238 mdio@3120 { 240 mdio@3120 {
239 #address-cells = <1>; 241 #address-cells = <1>;
240 #size-cells = <0>; 242 #size-cells = <0>;
241 reg = <3120 18>; 243 reg = <0x3120 0x18>;
242 compatible = "fsl,ucc-mdio"; 244 compatible = "fsl,ucc-mdio";
243 245
244 phy00:ethernet-phy@00 { 246 phy00:ethernet-phy@00 {
245 interrupt-parent = <&pic>; 247 interrupt-parent = <&pic>;
246 interrupts = <0>; 248 interrupts = <0>;
247 reg = <0>; 249 reg = <0x0>;
248 device_type = "ethernet-phy"; 250 device_type = "ethernet-phy";
249 }; 251 };
250 phy04:ethernet-phy@04 { 252 phy04:ethernet-phy@04 {
251 interrupt-parent = <&pic>; 253 interrupt-parent = <&pic>;
252 interrupts = <0>; 254 interrupts = <0>;
253 reg = <4>; 255 reg = <0x4>;
254 device_type = "ethernet-phy"; 256 device_type = "ethernet-phy";
255 }; 257 };
256 }; 258 };
@@ -260,43 +262,43 @@
260 compatible = "fsl,qe-ic"; 262 compatible = "fsl,qe-ic";
261 #address-cells = <0>; 263 #address-cells = <0>;
262 #interrupt-cells = <1>; 264 #interrupt-cells = <1>;
263 reg = <80 80>; 265 reg = <0x80 0x80>;
264 big-endian; 266 big-endian;
265 interrupts = <20 8 21 8>; //high:32 low:33 267 interrupts = <32 0x8 33 0x8>; //high:32 low:33
266 interrupt-parent = <&pic>; 268 interrupt-parent = <&pic>;
267 }; 269 };
268 }; 270 };
269 271
270 pci0: pci@e0008500 { 272 pci0: pci@e0008500 {
271 cell-index = <1>; 273 cell-index = <1>;
272 interrupt-map-mask = <f800 0 0 7>; 274 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
273 interrupt-map = < 275 interrupt-map = <
274 /* IDSEL 0x10 AD16 (USB) */ 276 /* IDSEL 0x10 AD16 (USB) */
275 8000 0 0 1 &pic 11 8 277 0x8000 0x0 0x0 0x1 &pic 17 0x8
276 278
277 /* IDSEL 0x11 AD17 (Mini1)*/ 279 /* IDSEL 0x11 AD17 (Mini1)*/
278 8800 0 0 1 &pic 12 8 280 0x8800 0x0 0x0 0x1 &pic 18 0x8
279 8800 0 0 2 &pic 13 8 281 0x8800 0x0 0x0 0x2 &pic 19 0x8
280 8800 0 0 3 &pic 14 8 282 0x8800 0x0 0x0 0x3 &pic 20 0x8
281 8800 0 0 4 &pic 30 8 283 0x8800 0x0 0x0 0x4 &pic 48 0x8
282 284
283 /* IDSEL 0x12 AD18 (PCI/Mini2) */ 285 /* IDSEL 0x12 AD18 (PCI/Mini2) */
284 9000 0 0 1 &pic 13 8 286 0x9000 0x0 0x0 0x1 &pic 19 0x8
285 9000 0 0 2 &pic 14 8 287 0x9000 0x0 0x0 0x2 &pic 20 0x8
286 9000 0 0 3 &pic 30 8 288 0x9000 0x0 0x0 0x3 &pic 48 0x8
287 9000 0 0 4 &pic 11 8>; 289 0x9000 0x0 0x0 0x4 &pic 17 0x8>;
288 290
289 interrupt-parent = <&pic>; 291 interrupt-parent = <&pic>;
290 interrupts = <42 8>; 292 interrupts = <66 0x8>;
291 bus-range = <0 0>; 293 bus-range = <0x0 0x0>;
292 ranges = <42000000 0 80000000 80000000 0 10000000 294 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
293 02000000 0 90000000 90000000 0 10000000 295 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
294 01000000 0 d0000000 d0000000 0 04000000>; 296 0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
295 clock-frequency = <0>; 297 clock-frequency = <0>;
296 #interrupt-cells = <1>; 298 #interrupt-cells = <1>;
297 #size-cells = <2>; 299 #size-cells = <2>;
298 #address-cells = <3>; 300 #address-cells = <3>;
299 reg = <e0008500 100>; 301 reg = <0xe0008500 0x100>;
300 compatible = "fsl,mpc8349-pci"; 302 compatible = "fsl,mpc8349-pci";
301 device_type = "pci"; 303 device_type = "pci";
302 }; 304 };
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 4a4ddea2d99c..9426676b0b7d 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -8,6 +8,9 @@
8 * Free Software Foundation; either version 2 of the License, or (at your 8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11
12/dts-v1/;
13
11/ { 14/ {
12 model = "MPC8349EMITX"; 15 model = "MPC8349EMITX";
13 compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX"; 16 compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX";
@@ -29,11 +32,11 @@
29 32
30 PowerPC,8349@0 { 33 PowerPC,8349@0 {
31 device_type = "cpu"; 34 device_type = "cpu";
32 reg = <0>; 35 reg = <0x0>;
33 d-cache-line-size = <20>; 36 d-cache-line-size = <32>;
34 i-cache-line-size = <20>; 37 i-cache-line-size = <32>;
35 d-cache-size = <8000>; 38 d-cache-size = <32768>;
36 i-cache-size = <8000>; 39 i-cache-size = <32768>;
37 timebase-frequency = <0>; // from bootloader 40 timebase-frequency = <0>; // from bootloader
38 bus-frequency = <0>; // from bootloader 41 bus-frequency = <0>; // from bootloader
39 clock-frequency = <0>; // from bootloader 42 clock-frequency = <0>; // from bootloader
@@ -42,21 +45,21 @@
42 45
43 memory { 46 memory {
44 device_type = "memory"; 47 device_type = "memory";
45 reg = <00000000 10000000>; 48 reg = <0x00000000 0x10000000>;
46 }; 49 };
47 50
48 soc8349@e0000000 { 51 soc8349@e0000000 {
49 #address-cells = <1>; 52 #address-cells = <1>;
50 #size-cells = <1>; 53 #size-cells = <1>;
51 device_type = "soc"; 54 device_type = "soc";
52 ranges = <0 e0000000 00100000>; 55 ranges = <0x0 0xe0000000 0x00100000>;
53 reg = <e0000000 00000200>; 56 reg = <0xe0000000 0x00000200>;
54 bus-frequency = <0>; // from bootloader 57 bus-frequency = <0>; // from bootloader
55 58
56 wdt@200 { 59 wdt@200 {
57 device_type = "watchdog"; 60 device_type = "watchdog";
58 compatible = "mpc83xx_wdt"; 61 compatible = "mpc83xx_wdt";
59 reg = <200 100>; 62 reg = <0x200 0x100>;
60 }; 63 };
61 64
62 i2c@3000 { 65 i2c@3000 {
@@ -64,9 +67,9 @@
64 #size-cells = <0>; 67 #size-cells = <0>;
65 cell-index = <0>; 68 cell-index = <0>;
66 compatible = "fsl-i2c"; 69 compatible = "fsl-i2c";
67 reg = <3000 100>; 70 reg = <0x3000 0x100>;
68 interrupts = <e 8>; 71 interrupts = <14 0x8>;
69 interrupt-parent = < &ipic >; 72 interrupt-parent = <&ipic>;
70 dfsrr; 73 dfsrr;
71 }; 74 };
72 75
@@ -75,39 +78,39 @@
75 #size-cells = <0>; 78 #size-cells = <0>;
76 cell-index = <1>; 79 cell-index = <1>;
77 compatible = "fsl-i2c"; 80 compatible = "fsl-i2c";
78 reg = <3100 100>; 81 reg = <0x3100 0x100>;
79 interrupts = <f 8>; 82 interrupts = <15 0x8>;
80 interrupt-parent = < &ipic >; 83 interrupt-parent = <&ipic>;
81 dfsrr; 84 dfsrr;
82 }; 85 };
83 86
84 spi@7000 { 87 spi@7000 {
85 cell-index = <0>; 88 cell-index = <0>;
86 compatible = "fsl,spi"; 89 compatible = "fsl,spi";
87 reg = <7000 1000>; 90 reg = <0x7000 0x1000>;
88 interrupts = <10 8>; 91 interrupts = <16 0x8>;
89 interrupt-parent = < &ipic >; 92 interrupt-parent = <&ipic>;
90 mode = "cpu"; 93 mode = "cpu";
91 }; 94 };
92 95
93 usb@22000 { 96 usb@22000 {
94 compatible = "fsl-usb2-mph"; 97 compatible = "fsl-usb2-mph";
95 reg = <22000 1000>; 98 reg = <0x22000 0x1000>;
96 #address-cells = <1>; 99 #address-cells = <1>;
97 #size-cells = <0>; 100 #size-cells = <0>;
98 interrupt-parent = < &ipic >; 101 interrupt-parent = <&ipic>;
99 interrupts = <27 8>; 102 interrupts = <39 0x8>;
100 phy_type = "ulpi"; 103 phy_type = "ulpi";
101 port1; 104 port1;
102 }; 105 };
103 106
104 usb@23000 { 107 usb@23000 {
105 compatible = "fsl-usb2-dr"; 108 compatible = "fsl-usb2-dr";
106 reg = <23000 1000>; 109 reg = <0x23000 0x1000>;
107 #address-cells = <1>; 110 #address-cells = <1>;
108 #size-cells = <0>; 111 #size-cells = <0>;
109 interrupt-parent = < &ipic >; 112 interrupt-parent = <&ipic>;
110 interrupts = <26 8>; 113 interrupts = <38 0x8>;
111 dr_mode = "peripheral"; 114 dr_mode = "peripheral";
112 phy_type = "ulpi"; 115 phy_type = "ulpi";
113 }; 116 };
@@ -116,13 +119,13 @@
116 #address-cells = <1>; 119 #address-cells = <1>;
117 #size-cells = <0>; 120 #size-cells = <0>;
118 compatible = "fsl,gianfar-mdio"; 121 compatible = "fsl,gianfar-mdio";
119 reg = <24520 20>; 122 reg = <0x24520 0x20>;
120 123
121 /* Vitesse 8201 */ 124 /* Vitesse 8201 */
122 phy1c: ethernet-phy@1c { 125 phy1c: ethernet-phy@1c {
123 interrupt-parent = < &ipic >; 126 interrupt-parent = <&ipic>;
124 interrupts = <12 8>; 127 interrupts = <18 0x8>;
125 reg = <1c>; 128 reg = <0x1c>;
126 device_type = "ethernet-phy"; 129 device_type = "ethernet-phy";
127 }; 130 };
128 }; 131 };
@@ -132,11 +135,11 @@
132 device_type = "network"; 135 device_type = "network";
133 model = "TSEC"; 136 model = "TSEC";
134 compatible = "gianfar"; 137 compatible = "gianfar";
135 reg = <24000 1000>; 138 reg = <0x24000 0x1000>;
136 local-mac-address = [ 00 00 00 00 00 00 ]; 139 local-mac-address = [ 00 00 00 00 00 00 ];
137 interrupts = <20 8 21 8 22 8>; 140 interrupts = <32 0x8 33 0x8 34 0x8>;
138 interrupt-parent = < &ipic >; 141 interrupt-parent = <&ipic>;
139 phy-handle = < &phy1c >; 142 phy-handle = <&phy1c>;
140 linux,network-index = <0>; 143 linux,network-index = <0>;
141 }; 144 };
142 145
@@ -145,12 +148,12 @@
145 device_type = "network"; 148 device_type = "network";
146 model = "TSEC"; 149 model = "TSEC";
147 compatible = "gianfar"; 150 compatible = "gianfar";
148 reg = <25000 1000>; 151 reg = <0x25000 0x1000>;
149 local-mac-address = [ 00 00 00 00 00 00 ]; 152 local-mac-address = [ 00 00 00 00 00 00 ];
150 interrupts = <23 8 24 8 25 8>; 153 interrupts = <35 0x8 36 0x8 37 0x8>;
151 interrupt-parent = < &ipic >; 154 interrupt-parent = <&ipic>;
152 /* Vitesse 7385 isn't on the MDIO bus */ 155 /* Vitesse 7385 isn't on the MDIO bus */
153 fixed-link = <1 1 d#1000 0 0>; 156 fixed-link = <1 1 1000 0 0>;
154 linux,network-index = <1>; 157 linux,network-index = <1>;
155 }; 158 };
156 159
@@ -158,88 +161,88 @@
158 cell-index = <0>; 161 cell-index = <0>;
159 device_type = "serial"; 162 device_type = "serial";
160 compatible = "ns16550"; 163 compatible = "ns16550";
161 reg = <4500 100>; 164 reg = <0x4500 0x100>;
162 clock-frequency = <0>; // from bootloader 165 clock-frequency = <0>; // from bootloader
163 interrupts = <9 8>; 166 interrupts = <9 0x8>;
164 interrupt-parent = < &ipic >; 167 interrupt-parent = <&ipic>;
165 }; 168 };
166 169
167 serial1: serial@4600 { 170 serial1: serial@4600 {
168 cell-index = <1>; 171 cell-index = <1>;
169 device_type = "serial"; 172 device_type = "serial";
170 compatible = "ns16550"; 173 compatible = "ns16550";
171 reg = <4600 100>; 174 reg = <0x4600 0x100>;
172 clock-frequency = <0>; // from bootloader 175 clock-frequency = <0>; // from bootloader
173 interrupts = <a 8>; 176 interrupts = <10 0x8>;
174 interrupt-parent = < &ipic >; 177 interrupt-parent = <&ipic>;
175 }; 178 };
176 179
177 crypto@30000 { 180 crypto@30000 {
178 device_type = "crypto"; 181 device_type = "crypto";
179 model = "SEC2"; 182 model = "SEC2";
180 compatible = "talitos"; 183 compatible = "talitos";
181 reg = <30000 10000>; 184 reg = <0x30000 0x10000>;
182 interrupts = <b 8>; 185 interrupts = <11 0x8>;
183 interrupt-parent = < &ipic >; 186 interrupt-parent = <&ipic>;
184 num-channels = <4>; 187 num-channels = <4>;
185 channel-fifo-len = <18>; 188 channel-fifo-len = <24>;
186 exec-units-mask = <0000007e>; 189 exec-units-mask = <0x0000007e>;
187 descriptor-types-mask = <01010ebf>; 190 descriptor-types-mask = <0x01010ebf>;
188 }; 191 };
189 192
190 ipic: pic@700 { 193 ipic: pic@700 {
191 interrupt-controller; 194 interrupt-controller;
192 #address-cells = <0>; 195 #address-cells = <0>;
193 #interrupt-cells = <2>; 196 #interrupt-cells = <2>;
194 reg = <700 100>; 197 reg = <0x700 0x100>;
195 device_type = "ipic"; 198 device_type = "ipic";
196 }; 199 };
197 }; 200 };
198 201
199 pci0: pci@e0008500 { 202 pci0: pci@e0008500 {
200 cell-index = <1>; 203 cell-index = <1>;
201 interrupt-map-mask = <f800 0 0 7>; 204 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
202 interrupt-map = < 205 interrupt-map = <
203 /* IDSEL 0x10 - SATA */ 206 /* IDSEL 0x10 - SATA */
204 8000 0 0 1 &ipic 16 8 /* SATA_INTA */ 207 0x8000 0x0 0x0 0x1 &ipic 22 0x8 /* SATA_INTA */
205 >; 208 >;
206 interrupt-parent = < &ipic >; 209 interrupt-parent = <&ipic>;
207 interrupts = <42 8>; 210 interrupts = <66 0x8>;
208 bus-range = <0 0>; 211 bus-range = <0x0 0x0>;
209 ranges = <42000000 0 80000000 80000000 0 10000000 212 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
210 02000000 0 90000000 90000000 0 10000000 213 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
211 01000000 0 00000000 e2000000 0 01000000>; 214 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
212 clock-frequency = <3f940aa>; 215 clock-frequency = <66666666>;
213 #interrupt-cells = <1>; 216 #interrupt-cells = <1>;
214 #size-cells = <2>; 217 #size-cells = <2>;
215 #address-cells = <3>; 218 #address-cells = <3>;
216 reg = <e0008500 100>; 219 reg = <0xe0008500 0x100>;
217 compatible = "fsl,mpc8349-pci"; 220 compatible = "fsl,mpc8349-pci";
218 device_type = "pci"; 221 device_type = "pci";
219 }; 222 };
220 223
221 pci1: pci@e0008600 { 224 pci1: pci@e0008600 {
222 cell-index = <2>; 225 cell-index = <2>;
223 interrupt-map-mask = <f800 0 0 7>; 226 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
224 interrupt-map = < 227 interrupt-map = <
225 /* IDSEL 0x0E - MiniPCI Slot */ 228 /* IDSEL 0x0E - MiniPCI Slot */
226 7000 0 0 1 &ipic 15 8 /* PCI_INTA */ 229 0x7000 0x0 0x0 0x1 &ipic 21 0x8 /* PCI_INTA */
227 230
228 /* IDSEL 0x0F - PCI Slot */ 231 /* IDSEL 0x0F - PCI Slot */
229 7800 0 0 1 &ipic 14 8 /* PCI_INTA */ 232 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
230 7800 0 0 2 &ipic 15 8 /* PCI_INTB */ 233 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
231 >; 234 >;
232 interrupt-parent = < &ipic >; 235 interrupt-parent = <&ipic>;
233 interrupts = <43 8>; 236 interrupts = <67 0x8>;
234 bus-range = <0 0>; 237 bus-range = <0x0 0x0>;
235 ranges = <42000000 0 a0000000 a0000000 0 10000000 238 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
236 02000000 0 b0000000 b0000000 0 10000000 239 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
237 01000000 0 00000000 e3000000 0 01000000>; 240 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
238 clock-frequency = <3f940aa>; 241 clock-frequency = <66666666>;
239 #interrupt-cells = <1>; 242 #interrupt-cells = <1>;
240 #size-cells = <2>; 243 #size-cells = <2>;
241 #address-cells = <3>; 244 #address-cells = <3>;
242 reg = <e0008600 100>; 245 reg = <0xe0008600 0x100>;
243 compatible = "fsl,mpc8349-pci"; 246 compatible = "fsl,mpc8349-pci";
244 device_type = "pci"; 247 device_type = "pci";
245 }; 248 };
@@ -249,15 +252,15 @@
249 #size-cells = <1>; 252 #size-cells = <1>;
250 compatible = "fsl,mpc8349e-localbus", 253 compatible = "fsl,mpc8349e-localbus",
251 "fsl,pq2pro-localbus"; 254 "fsl,pq2pro-localbus";
252 reg = <e0005000 d8>; 255 reg = <0xe0005000 0xd8>;
253 ranges = <3 0 f0000000 210>; 256 ranges = <0x3 0x0 0xf0000000 0x210>;
254 257
255 pata@3,0 { 258 pata@3,0 {
256 compatible = "fsl,mpc8349emitx-pata", "ata-generic"; 259 compatible = "fsl,mpc8349emitx-pata", "ata-generic";
257 reg = <3 0 10 3 20c 4>; 260 reg = <0x3 0x0 0x10 0x3 0x20c 0x4>;
258 reg-shift = <1>; 261 reg-shift = <1>;
259 pio-mode = <6>; 262 pio-mode = <6>;
260 interrupts = <17 8>; 263 interrupts = <23 0x8>;
261 interrupt-parent = <&ipic>; 264 interrupt-parent = <&ipic>;
262 }; 265 };
263 }; 266 };
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index 79983d74eee4..f81d735e6e72 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -8,6 +8,9 @@
8 * Free Software Foundation; either version 2 of the License, or (at your 8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11
12/dts-v1/;
13
11/ { 14/ {
12 model = "MPC8349EMITXGP"; 15 model = "MPC8349EMITXGP";
13 compatible = "MPC8349EMITXGP", "MPC834xMITX", "MPC83xxMITX"; 16 compatible = "MPC8349EMITXGP", "MPC834xMITX", "MPC83xxMITX";
@@ -27,11 +30,11 @@
27 30
28 PowerPC,8349@0 { 31 PowerPC,8349@0 {
29 device_type = "cpu"; 32 device_type = "cpu";
30 reg = <0>; 33 reg = <0x0>;
31 d-cache-line-size = <20>; 34 d-cache-line-size = <32>;
32 i-cache-line-size = <20>; 35 i-cache-line-size = <32>;
33 d-cache-size = <8000>; 36 d-cache-size = <32768>;
34 i-cache-size = <8000>; 37 i-cache-size = <32768>;
35 timebase-frequency = <0>; // from bootloader 38 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader 39 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader 40 clock-frequency = <0>; // from bootloader
@@ -40,21 +43,21 @@
40 43
41 memory { 44 memory {
42 device_type = "memory"; 45 device_type = "memory";
43 reg = <00000000 10000000>; 46 reg = <0x00000000 0x10000000>;
44 }; 47 };
45 48
46 soc8349@e0000000 { 49 soc8349@e0000000 {
47 #address-cells = <1>; 50 #address-cells = <1>;
48 #size-cells = <1>; 51 #size-cells = <1>;
49 device_type = "soc"; 52 device_type = "soc";
50 ranges = <0 e0000000 00100000>; 53 ranges = <0x0 0xe0000000 0x00100000>;
51 reg = <e0000000 00000200>; 54 reg = <0xe0000000 0x00000200>;
52 bus-frequency = <0>; // from bootloader 55 bus-frequency = <0>; // from bootloader
53 56
54 wdt@200 { 57 wdt@200 {
55 device_type = "watchdog"; 58 device_type = "watchdog";
56 compatible = "mpc83xx_wdt"; 59 compatible = "mpc83xx_wdt";
57 reg = <200 100>; 60 reg = <0x200 0x100>;
58 }; 61 };
59 62
60 i2c@3000 { 63 i2c@3000 {
@@ -62,9 +65,9 @@
62 #size-cells = <0>; 65 #size-cells = <0>;
63 cell-index = <0>; 66 cell-index = <0>;
64 compatible = "fsl-i2c"; 67 compatible = "fsl-i2c";
65 reg = <3000 100>; 68 reg = <0x3000 0x100>;
66 interrupts = <e 8>; 69 interrupts = <14 0x8>;
67 interrupt-parent = < &ipic >; 70 interrupt-parent = <&ipic>;
68 dfsrr; 71 dfsrr;
69 }; 72 };
70 73
@@ -73,28 +76,28 @@
73 #size-cells = <0>; 76 #size-cells = <0>;
74 cell-index = <1>; 77 cell-index = <1>;
75 compatible = "fsl-i2c"; 78 compatible = "fsl-i2c";
76 reg = <3100 100>; 79 reg = <0x3100 0x100>;
77 interrupts = <f 8>; 80 interrupts = <15 0x8>;
78 interrupt-parent = < &ipic >; 81 interrupt-parent = <&ipic>;
79 dfsrr; 82 dfsrr;
80 }; 83 };
81 84
82 spi@7000 { 85 spi@7000 {
83 cell-index = <0>; 86 cell-index = <0>;
84 compatible = "fsl,spi"; 87 compatible = "fsl,spi";
85 reg = <7000 1000>; 88 reg = <0x7000 0x1000>;
86 interrupts = <10 8>; 89 interrupts = <16 0x8>;
87 interrupt-parent = < &ipic >; 90 interrupt-parent = <&ipic>;
88 mode = "cpu"; 91 mode = "cpu";
89 }; 92 };
90 93
91 usb@23000 { 94 usb@23000 {
92 compatible = "fsl-usb2-dr"; 95 compatible = "fsl-usb2-dr";
93 reg = <23000 1000>; 96 reg = <0x23000 0x1000>;
94 #address-cells = <1>; 97 #address-cells = <1>;
95 #size-cells = <0>; 98 #size-cells = <0>;
96 interrupt-parent = < &ipic >; 99 interrupt-parent = <&ipic>;
97 interrupts = <26 8>; 100 interrupts = <38 0x8>;
98 dr_mode = "otg"; 101 dr_mode = "otg";
99 phy_type = "ulpi"; 102 phy_type = "ulpi";
100 }; 103 };
@@ -103,13 +106,13 @@
103 #address-cells = <1>; 106 #address-cells = <1>;
104 #size-cells = <0>; 107 #size-cells = <0>;
105 compatible = "fsl,gianfar-mdio"; 108 compatible = "fsl,gianfar-mdio";
106 reg = <24520 20>; 109 reg = <0x24520 0x20>;
107 110
108 /* Vitesse 8201 */ 111 /* Vitesse 8201 */
109 phy1c: ethernet-phy@1c { 112 phy1c: ethernet-phy@1c {
110 interrupt-parent = < &ipic >; 113 interrupt-parent = <&ipic>;
111 interrupts = <12 8>; 114 interrupts = <18 0x8>;
112 reg = <1c>; 115 reg = <0x1c>;
113 device_type = "ethernet-phy"; 116 device_type = "ethernet-phy";
114 }; 117 };
115 }; 118 };
@@ -119,11 +122,11 @@
119 device_type = "network"; 122 device_type = "network";
120 model = "TSEC"; 123 model = "TSEC";
121 compatible = "gianfar"; 124 compatible = "gianfar";
122 reg = <24000 1000>; 125 reg = <0x24000 0x1000>;
123 local-mac-address = [ 00 00 00 00 00 00 ]; 126 local-mac-address = [ 00 00 00 00 00 00 ];
124 interrupts = <20 8 21 8 22 8>; 127 interrupts = <32 0x8 33 0x8 34 0x8>;
125 interrupt-parent = < &ipic >; 128 interrupt-parent = <&ipic>;
126 phy-handle = < &phy1c >; 129 phy-handle = <&phy1c>;
127 linux,network-index = <0>; 130 linux,network-index = <0>;
128 }; 131 };
129 132
@@ -131,63 +134,63 @@
131 cell-index = <0>; 134 cell-index = <0>;
132 device_type = "serial"; 135 device_type = "serial";
133 compatible = "ns16550"; 136 compatible = "ns16550";
134 reg = <4500 100>; 137 reg = <0x4500 0x100>;
135 clock-frequency = <0>; // from bootloader 138 clock-frequency = <0>; // from bootloader
136 interrupts = <9 8>; 139 interrupts = <9 0x8>;
137 interrupt-parent = < &ipic >; 140 interrupt-parent = <&ipic>;
138 }; 141 };
139 142
140 serial1: serial@4600 { 143 serial1: serial@4600 {
141 cell-index = <1>; 144 cell-index = <1>;
142 device_type = "serial"; 145 device_type = "serial";
143 compatible = "ns16550"; 146 compatible = "ns16550";
144 reg = <4600 100>; 147 reg = <0x4600 0x100>;
145 clock-frequency = <0>; // from bootloader 148 clock-frequency = <0>; // from bootloader
146 interrupts = <a 8>; 149 interrupts = <10 0x8>;
147 interrupt-parent = < &ipic >; 150 interrupt-parent = <&ipic>;
148 }; 151 };
149 152
150 crypto@30000 { 153 crypto@30000 {
151 device_type = "crypto"; 154 device_type = "crypto";
152 model = "SEC2"; 155 model = "SEC2";
153 compatible = "talitos"; 156 compatible = "talitos";
154 reg = <30000 10000>; 157 reg = <0x30000 0x10000>;
155 interrupts = <b 8>; 158 interrupts = <11 0x8>;
156 interrupt-parent = < &ipic >; 159 interrupt-parent = <&ipic>;
157 num-channels = <4>; 160 num-channels = <4>;
158 channel-fifo-len = <18>; 161 channel-fifo-len = <24>;
159 exec-units-mask = <0000007e>; 162 exec-units-mask = <0x0000007e>;
160 descriptor-types-mask = <01010ebf>; 163 descriptor-types-mask = <0x01010ebf>;
161 }; 164 };
162 165
163 ipic: pic@700 { 166 ipic: pic@700 {
164 interrupt-controller; 167 interrupt-controller;
165 #address-cells = <0>; 168 #address-cells = <0>;
166 #interrupt-cells = <2>; 169 #interrupt-cells = <2>;
167 reg = <700 100>; 170 reg = <0x700 0x100>;
168 device_type = "ipic"; 171 device_type = "ipic";
169 }; 172 };
170 }; 173 };
171 174
172 pci0: pci@e0008600 { 175 pci0: pci@e0008600 {
173 cell-index = <2>; 176 cell-index = <2>;
174 interrupt-map-mask = <f800 0 0 7>; 177 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
175 interrupt-map = < 178 interrupt-map = <
176 /* IDSEL 0x0F - PCI Slot */ 179 /* IDSEL 0x0F - PCI Slot */
177 7800 0 0 1 &ipic 14 8 /* PCI_INTA */ 180 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
178 7800 0 0 2 &ipic 15 8 /* PCI_INTB */ 181 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
179 >; 182 >;
180 interrupt-parent = < &ipic >; 183 interrupt-parent = <&ipic>;
181 interrupts = <43 8>; 184 interrupts = <67 0x8>;
182 bus-range = <1 1>; 185 bus-range = <0x1 0x1>;
183 ranges = <42000000 0 a0000000 a0000000 0 10000000 186 ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
184 02000000 0 b0000000 b0000000 0 10000000 187 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
185 01000000 0 00000000 e3000000 0 01000000>; 188 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
186 clock-frequency = <3f940aa>; 189 clock-frequency = <66666666>;
187 #interrupt-cells = <1>; 190 #interrupt-cells = <1>;
188 #size-cells = <2>; 191 #size-cells = <2>;
189 #address-cells = <3>; 192 #address-cells = <3>;
190 reg = <e0008600 100>; 193 reg = <0xe0008600 0x100>;
191 compatible = "fsl,mpc8349-pci"; 194 compatible = "fsl,mpc8349-pci";
192 device_type = "pci"; 195 device_type = "pci";
193 }; 196 };
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 8faa8bd6ed64..7480edae85ed 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -32,7 +32,7 @@
32 32
33 PowerPC,8349@0 { 33 PowerPC,8349@0 {
34 device_type = "cpu"; 34 device_type = "cpu";
35 reg = <0>; 35 reg = <0x0>;
36 d-cache-line-size = <32>; 36 d-cache-line-size = <32>;
37 i-cache-line-size = <32>; 37 i-cache-line-size = <32>;
38 d-cache-size = <32768>; 38 d-cache-size = <32768>;
@@ -73,7 +73,7 @@
73 cell-index = <0>; 73 cell-index = <0>;
74 compatible = "fsl-i2c"; 74 compatible = "fsl-i2c";
75 reg = <0x3000 0x100>; 75 reg = <0x3000 0x100>;
76 interrupts = <14 8>; 76 interrupts = <14 0x8>;
77 interrupt-parent = <&ipic>; 77 interrupt-parent = <&ipic>;
78 dfsrr; 78 dfsrr;
79 79
@@ -89,7 +89,7 @@
89 cell-index = <1>; 89 cell-index = <1>;
90 compatible = "fsl-i2c"; 90 compatible = "fsl-i2c";
91 reg = <0x3100 0x100>; 91 reg = <0x3100 0x100>;
92 interrupts = <15 8>; 92 interrupts = <15 0x8>;
93 interrupt-parent = <&ipic>; 93 interrupt-parent = <&ipic>;
94 dfsrr; 94 dfsrr;
95 }; 95 };
@@ -98,7 +98,7 @@
98 cell-index = <0>; 98 cell-index = <0>;
99 compatible = "fsl,spi"; 99 compatible = "fsl,spi";
100 reg = <0x7000 0x1000>; 100 reg = <0x7000 0x1000>;
101 interrupts = <16 8>; 101 interrupts = <16 0x8>;
102 interrupt-parent = <&ipic>; 102 interrupt-parent = <&ipic>;
103 mode = "cpu"; 103 mode = "cpu";
104 }; 104 };
@@ -111,7 +111,7 @@
111 #address-cells = <1>; 111 #address-cells = <1>;
112 #size-cells = <0>; 112 #size-cells = <0>;
113 interrupt-parent = <&ipic>; 113 interrupt-parent = <&ipic>;
114 interrupts = <39 8>; 114 interrupts = <39 0x8>;
115 phy_type = "ulpi"; 115 phy_type = "ulpi";
116 port1; 116 port1;
117 }; 117 };
@@ -122,7 +122,7 @@
122 #address-cells = <1>; 122 #address-cells = <1>;
123 #size-cells = <0>; 123 #size-cells = <0>;
124 interrupt-parent = <&ipic>; 124 interrupt-parent = <&ipic>;
125 interrupts = <38 8>; 125 interrupts = <38 0x8>;
126 dr_mode = "otg"; 126 dr_mode = "otg";
127 phy_type = "ulpi"; 127 phy_type = "ulpi";
128 }; 128 };
@@ -135,13 +135,13 @@
135 135
136 phy0: ethernet-phy@0 { 136 phy0: ethernet-phy@0 {
137 interrupt-parent = <&ipic>; 137 interrupt-parent = <&ipic>;
138 interrupts = <17 8>; 138 interrupts = <17 0x8>;
139 reg = <0x0>; 139 reg = <0x0>;
140 device_type = "ethernet-phy"; 140 device_type = "ethernet-phy";
141 }; 141 };
142 phy1: ethernet-phy@1 { 142 phy1: ethernet-phy@1 {
143 interrupt-parent = <&ipic>; 143 interrupt-parent = <&ipic>;
144 interrupts = <18 8>; 144 interrupts = <18 0x8>;
145 reg = <0x1>; 145 reg = <0x1>;
146 device_type = "ethernet-phy"; 146 device_type = "ethernet-phy";
147 }; 147 };
@@ -154,7 +154,7 @@
154 compatible = "gianfar"; 154 compatible = "gianfar";
155 reg = <0x24000 0x1000>; 155 reg = <0x24000 0x1000>;
156 local-mac-address = [ 00 00 00 00 00 00 ]; 156 local-mac-address = [ 00 00 00 00 00 00 ];
157 interrupts = <32 8 33 8 34 8>; 157 interrupts = <32 0x8 33 0x8 34 0x8>;
158 interrupt-parent = <&ipic>; 158 interrupt-parent = <&ipic>;
159 phy-handle = <&phy0>; 159 phy-handle = <&phy0>;
160 linux,network-index = <0>; 160 linux,network-index = <0>;
@@ -167,7 +167,7 @@
167 compatible = "gianfar"; 167 compatible = "gianfar";
168 reg = <0x25000 0x1000>; 168 reg = <0x25000 0x1000>;
169 local-mac-address = [ 00 00 00 00 00 00 ]; 169 local-mac-address = [ 00 00 00 00 00 00 ];
170 interrupts = <35 8 36 8 37 8>; 170 interrupts = <35 0x8 36 0x8 37 0x8>;
171 interrupt-parent = <&ipic>; 171 interrupt-parent = <&ipic>;
172 phy-handle = <&phy1>; 172 phy-handle = <&phy1>;
173 linux,network-index = <1>; 173 linux,network-index = <1>;
@@ -179,7 +179,7 @@
179 compatible = "ns16550"; 179 compatible = "ns16550";
180 reg = <0x4500 0x100>; 180 reg = <0x4500 0x100>;
181 clock-frequency = <0>; 181 clock-frequency = <0>;
182 interrupts = <9 8>; 182 interrupts = <9 0x8>;
183 interrupt-parent = <&ipic>; 183 interrupt-parent = <&ipic>;
184 }; 184 };
185 185
@@ -189,7 +189,7 @@
189 compatible = "ns16550"; 189 compatible = "ns16550";
190 reg = <0x4600 0x100>; 190 reg = <0x4600 0x100>;
191 clock-frequency = <0>; 191 clock-frequency = <0>;
192 interrupts = <10 8>; 192 interrupts = <10 0x8>;
193 interrupt-parent = <&ipic>; 193 interrupt-parent = <&ipic>;
194 }; 194 };
195 195
@@ -199,10 +199,10 @@
199 model = "SEC2"; 199 model = "SEC2";
200 compatible = "talitos"; 200 compatible = "talitos";
201 reg = <0x30000 0x10000>; 201 reg = <0x30000 0x10000>;
202 interrupts = <11 8>; 202 interrupts = <11 0x8>;
203 interrupt-parent = <&ipic>; 203 interrupt-parent = <&ipic>;
204 num-channels = <4>; 204 num-channels = <4>;
205 channel-fifo-len = <0x18>; 205 channel-fifo-len = <24>;
206 exec-units-mask = <0x0000007e>; 206 exec-units-mask = <0x0000007e>;
207 /* desc mask is for rev2.0, 207 /* desc mask is for rev2.0,
208 * we need runtime fixup for >2.0 */ 208 * we need runtime fixup for >2.0 */
@@ -269,9 +269,9 @@
269 0xc000 0x0 0x0 0x1 &ipic 21 0x8 269 0xc000 0x0 0x0 0x1 &ipic 21 0x8
270 0xc000 0x0 0x0 0x2 &ipic 22 0x8 270 0xc000 0x0 0x0 0x2 &ipic 22 0x8
271 0xc000 0x0 0x0 0x3 &ipic 23 0x8 271 0xc000 0x0 0x0 0x3 &ipic 23 0x8
272 0xc000 0x0 0x0 0x4 &ipic 20 8>; 272 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
273 interrupt-parent = <&ipic>; 273 interrupt-parent = <&ipic>;
274 interrupts = <66 8>; 274 interrupts = <66 0x8>;
275 bus-range = <0 0>; 275 bus-range = <0 0>;
276 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 276 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
277 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 277 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
@@ -330,9 +330,9 @@
330 0xc000 0x0 0x0 0x1 &ipic 21 0x8 330 0xc000 0x0 0x0 0x1 &ipic 21 0x8
331 0xc000 0x0 0x0 0x2 &ipic 22 0x8 331 0xc000 0x0 0x0 0x2 &ipic 22 0x8
332 0xc000 0x0 0x0 0x3 &ipic 23 0x8 332 0xc000 0x0 0x0 0x3 &ipic 23 0x8
333 0xc000 0x0 0x0 0x4 &ipic 20 8>; 333 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
334 interrupt-parent = <&ipic>; 334 interrupt-parent = <&ipic>;
335 interrupts = <66 8>; 335 interrupts = <66 0x8>;
336 bus-range = <0 0>; 336 bus-range = <0 0>;
337 ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 337 ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
338 0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 338 0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index dc6caf0b4c2d..55f03e8dc97f 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -14,6 +14,8 @@
14/memreserve/ 00000000 1000000; 14/memreserve/ 00000000 1000000;
15*/ 15*/
16 16
17/dts-v1/;
18
17/ { 19/ {
18 model = "MPC8360MDS"; 20 model = "MPC8360MDS";
19 compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS"; 21 compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
@@ -34,39 +36,39 @@
34 36
35 PowerPC,8360@0 { 37 PowerPC,8360@0 {
36 device_type = "cpu"; 38 device_type = "cpu";
37 reg = <0>; 39 reg = <0x0>;
38 d-cache-line-size = <20>; // 32 bytes 40 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <20>; // 32 bytes 41 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <8000>; // L1, 32K 42 d-cache-size = <32768>; // L1, 32K
41 i-cache-size = <8000>; // L1, 32K 43 i-cache-size = <32768>; // L1, 32K
42 timebase-frequency = <3EF1480>; 44 timebase-frequency = <66000000>;
43 bus-frequency = <FBC5200>; 45 bus-frequency = <264000000>;
44 clock-frequency = <1F78A400>; 46 clock-frequency = <528000000>;
45 }; 47 };
46 }; 48 };
47 49
48 memory { 50 memory {
49 device_type = "memory"; 51 device_type = "memory";
50 reg = <00000000 10000000>; 52 reg = <0x00000000 0x10000000>;
51 }; 53 };
52 54
53 bcsr@f8000000 { 55 bcsr@f8000000 {
54 device_type = "board-control"; 56 device_type = "board-control";
55 reg = <f8000000 8000>; 57 reg = <0xf8000000 0x8000>;
56 }; 58 };
57 59
58 soc8360@e0000000 { 60 soc8360@e0000000 {
59 #address-cells = <1>; 61 #address-cells = <1>;
60 #size-cells = <1>; 62 #size-cells = <1>;
61 device_type = "soc"; 63 device_type = "soc";
62 ranges = <0 e0000000 00100000>; 64 ranges = <0x0 0xe0000000 0x00100000>;
63 reg = <e0000000 00000200>; 65 reg = <0xe0000000 0x00000200>;
64 bus-frequency = <FBC5200>; 66 bus-frequency = <264000000>;
65 67
66 wdt@200 { 68 wdt@200 {
67 device_type = "watchdog"; 69 device_type = "watchdog";
68 compatible = "mpc83xx_wdt"; 70 compatible = "mpc83xx_wdt";
69 reg = <200 100>; 71 reg = <0x200 0x100>;
70 }; 72 };
71 73
72 i2c@3000 { 74 i2c@3000 {
@@ -74,14 +76,14 @@
74 #size-cells = <0>; 76 #size-cells = <0>;
75 cell-index = <0>; 77 cell-index = <0>;
76 compatible = "fsl-i2c"; 78 compatible = "fsl-i2c";
77 reg = <3000 100>; 79 reg = <0x3000 0x100>;
78 interrupts = <e 8>; 80 interrupts = <14 0x8>;
79 interrupt-parent = < &ipic >; 81 interrupt-parent = <&ipic>;
80 dfsrr; 82 dfsrr;
81 83
82 rtc@68 { 84 rtc@68 {
83 compatible = "dallas,ds1374"; 85 compatible = "dallas,ds1374";
84 reg = <68>; 86 reg = <0x68>;
85 }; 87 };
86 }; 88 };
87 89
@@ -90,9 +92,9 @@
90 #size-cells = <0>; 92 #size-cells = <0>;
91 cell-index = <1>; 93 cell-index = <1>;
92 compatible = "fsl-i2c"; 94 compatible = "fsl-i2c";
93 reg = <3100 100>; 95 reg = <0x3100 0x100>;
94 interrupts = <f 8>; 96 interrupts = <15 0x8>;
95 interrupt-parent = < &ipic >; 97 interrupt-parent = <&ipic>;
96 dfsrr; 98 dfsrr;
97 }; 99 };
98 100
@@ -100,46 +102,46 @@
100 cell-index = <0>; 102 cell-index = <0>;
101 device_type = "serial"; 103 device_type = "serial";
102 compatible = "ns16550"; 104 compatible = "ns16550";
103 reg = <4500 100>; 105 reg = <0x4500 0x100>;
104 clock-frequency = <FBC5200>; 106 clock-frequency = <264000000>;
105 interrupts = <9 8>; 107 interrupts = <9 0x8>;
106 interrupt-parent = < &ipic >; 108 interrupt-parent = <&ipic>;
107 }; 109 };
108 110
109 serial1: serial@4600 { 111 serial1: serial@4600 {
110 cell-index = <1>; 112 cell-index = <1>;
111 device_type = "serial"; 113 device_type = "serial";
112 compatible = "ns16550"; 114 compatible = "ns16550";
113 reg = <4600 100>; 115 reg = <0x4600 0x100>;
114 clock-frequency = <FBC5200>; 116 clock-frequency = <264000000>;
115 interrupts = <a 8>; 117 interrupts = <10 0x8>;
116 interrupt-parent = < &ipic >; 118 interrupt-parent = <&ipic>;
117 }; 119 };
118 120
119 crypto@30000 { 121 crypto@30000 {
120 device_type = "crypto"; 122 device_type = "crypto";
121 model = "SEC2"; 123 model = "SEC2";
122 compatible = "talitos"; 124 compatible = "talitos";
123 reg = <30000 10000>; 125 reg = <0x30000 0x10000>;
124 interrupts = <b 8>; 126 interrupts = <11 0x8>;
125 interrupt-parent = < &ipic >; 127 interrupt-parent = <&ipic>;
126 num-channels = <4>; 128 num-channels = <4>;
127 channel-fifo-len = <18>; 129 channel-fifo-len = <24>;
128 exec-units-mask = <0000007e>; 130 exec-units-mask = <0x0000007e>;
129 /* desc mask is for rev1.x, we need runtime fixup for >=2.x */ 131 /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
130 descriptor-types-mask = <01010ebf>; 132 descriptor-types-mask = <0x01010ebf>;
131 }; 133 };
132 134
133 ipic: pic@700 { 135 ipic: pic@700 {
134 interrupt-controller; 136 interrupt-controller;
135 #address-cells = <0>; 137 #address-cells = <0>;
136 #interrupt-cells = <2>; 138 #interrupt-cells = <2>;
137 reg = <700 100>; 139 reg = <0x700 0x100>;
138 device_type = "ipic"; 140 device_type = "ipic";
139 }; 141 };
140 142
141 par_io@1400 { 143 par_io@1400 {
142 reg = <1400 100>; 144 reg = <0x1400 0x100>;
143 device_type = "par_io"; 145 device_type = "par_io";
144 num-ports = <7>; 146 num-ports = <7>;
145 147
@@ -153,19 +155,19 @@
153 1 6 1 0 3 0 /* TxD4 */ 155 1 6 1 0 3 0 /* TxD4 */
154 1 7 1 0 1 0 /* TxD5 */ 156 1 7 1 0 1 0 /* TxD5 */
155 1 9 1 0 2 0 /* TxD6 */ 157 1 9 1 0 2 0 /* TxD6 */
156 1 a 1 0 2 0 /* TxD7 */ 158 1 10 1 0 2 0 /* TxD7 */
157 0 9 2 0 1 0 /* RxD0 */ 159 0 9 2 0 1 0 /* RxD0 */
158 0 a 2 0 1 0 /* RxD1 */ 160 0 10 2 0 1 0 /* RxD1 */
159 0 b 2 0 1 0 /* RxD2 */ 161 0 11 2 0 1 0 /* RxD2 */
160 0 c 2 0 1 0 /* RxD3 */ 162 0 12 2 0 1 0 /* RxD3 */
161 0 d 2 0 1 0 /* RxD4 */ 163 0 13 2 0 1 0 /* RxD4 */
162 1 1 2 0 2 0 /* RxD5 */ 164 1 1 2 0 2 0 /* RxD5 */
163 1 0 2 0 2 0 /* RxD6 */ 165 1 0 2 0 2 0 /* RxD6 */
164 1 4 2 0 2 0 /* RxD7 */ 166 1 4 2 0 2 0 /* RxD7 */
165 0 7 1 0 1 0 /* TX_EN */ 167 0 7 1 0 1 0 /* TX_EN */
166 0 8 1 0 1 0 /* TX_ER */ 168 0 8 1 0 1 0 /* TX_ER */
167 0 f 2 0 1 0 /* RX_DV */ 169 0 15 2 0 1 0 /* RX_DV */
168 0 10 2 0 1 0 /* RX_ER */ 170 0 16 2 0 1 0 /* RX_ER */
169 0 0 2 0 1 0 /* RX_CLK */ 171 0 0 2 0 1 0 /* RX_CLK */
170 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ 172 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
171 2 8 2 0 1 0>; /* GTX125 - CLK9 */ 173 2 8 2 0 1 0>; /* GTX125 - CLK9 */
@@ -173,27 +175,27 @@
173 pio2: ucc_pin@02 { 175 pio2: ucc_pin@02 {
174 pio-map = < 176 pio-map = <
175 /* port pin dir open_drain assignment has_irq */ 177 /* port pin dir open_drain assignment has_irq */
176 0 11 1 0 1 0 /* TxD0 */ 178 0 17 1 0 1 0 /* TxD0 */
177 0 12 1 0 1 0 /* TxD1 */ 179 0 18 1 0 1 0 /* TxD1 */
178 0 13 1 0 1 0 /* TxD2 */ 180 0 19 1 0 1 0 /* TxD2 */
179 0 14 1 0 1 0 /* TxD3 */ 181 0 20 1 0 1 0 /* TxD3 */
180 1 2 1 0 1 0 /* TxD4 */ 182 1 2 1 0 1 0 /* TxD4 */
181 1 3 1 0 2 0 /* TxD5 */ 183 1 3 1 0 2 0 /* TxD5 */
182 1 5 1 0 3 0 /* TxD6 */ 184 1 5 1 0 3 0 /* TxD6 */
183 1 8 1 0 3 0 /* TxD7 */ 185 1 8 1 0 3 0 /* TxD7 */
184 0 17 2 0 1 0 /* RxD0 */ 186 0 23 2 0 1 0 /* RxD0 */
185 0 18 2 0 1 0 /* RxD1 */ 187 0 24 2 0 1 0 /* RxD1 */
186 0 19 2 0 1 0 /* RxD2 */ 188 0 25 2 0 1 0 /* RxD2 */
187 0 1a 2 0 1 0 /* RxD3 */ 189 0 26 2 0 1 0 /* RxD3 */
188 0 1b 2 0 1 0 /* RxD4 */ 190 0 27 2 0 1 0 /* RxD4 */
189 1 c 2 0 2 0 /* RxD5 */ 191 1 12 2 0 2 0 /* RxD5 */
190 1 d 2 0 3 0 /* RxD6 */ 192 1 13 2 0 3 0 /* RxD6 */
191 1 b 2 0 2 0 /* RxD7 */ 193 1 11 2 0 2 0 /* RxD7 */
192 0 15 1 0 1 0 /* TX_EN */ 194 0 21 1 0 1 0 /* TX_EN */
193 0 16 1 0 1 0 /* TX_ER */ 195 0 22 1 0 1 0 /* TX_ER */
194 0 1d 2 0 1 0 /* RX_DV */ 196 0 29 2 0 1 0 /* RX_DV */
195 0 1e 2 0 1 0 /* RX_ER */ 197 0 30 2 0 1 0 /* RX_ER */
196 0 1f 2 0 1 0 /* RX_CLK */ 198 0 31 2 0 1 0 /* RX_CLK */
197 2 2 1 0 2 0 /* GTX_CLK - CLK10 */ 199 2 2 1 0 2 0 /* GTX_CLK - CLK10 */
198 2 3 2 0 1 0 /* GTX125 - CLK4 */ 200 2 3 2 0 1 0 /* GTX125 - CLK4 */
199 0 1 3 0 2 0 /* MDIO */ 201 0 1 3 0 2 0 /* MDIO */
@@ -208,47 +210,47 @@
208 #size-cells = <1>; 210 #size-cells = <1>;
209 device_type = "qe"; 211 device_type = "qe";
210 compatible = "fsl,qe"; 212 compatible = "fsl,qe";
211 ranges = <0 e0100000 00100000>; 213 ranges = <0x0 0xe0100000 0x00100000>;
212 reg = <e0100000 480>; 214 reg = <0xe0100000 0x480>;
213 brg-frequency = <0>; 215 brg-frequency = <0>;
214 bus-frequency = <179A7B00>; 216 bus-frequency = <396000000>;
215 217
216 muram@10000 { 218 muram@10000 {
217 #address-cells = <1>; 219 #address-cells = <1>;
218 #size-cells = <1>; 220 #size-cells = <1>;
219 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 221 compatible = "fsl,qe-muram", "fsl,cpm-muram";
220 ranges = <0 00010000 0000c000>; 222 ranges = <0x0 0x00010000 0x0000c000>;
221 223
222 data-only@0 { 224 data-only@0 {
223 compatible = "fsl,qe-muram-data", 225 compatible = "fsl,qe-muram-data",
224 "fsl,cpm-muram-data"; 226 "fsl,cpm-muram-data";
225 reg = <0 c000>; 227 reg = <0x0 0xc000>;
226 }; 228 };
227 }; 229 };
228 230
229 spi@4c0 { 231 spi@4c0 {
230 cell-index = <0>; 232 cell-index = <0>;
231 compatible = "fsl,spi"; 233 compatible = "fsl,spi";
232 reg = <4c0 40>; 234 reg = <0x4c0 0x40>;
233 interrupts = <2>; 235 interrupts = <2>;
234 interrupt-parent = < &qeic >; 236 interrupt-parent = <&qeic>;
235 mode = "cpu"; 237 mode = "cpu";
236 }; 238 };
237 239
238 spi@500 { 240 spi@500 {
239 cell-index = <1>; 241 cell-index = <1>;
240 compatible = "fsl,spi"; 242 compatible = "fsl,spi";
241 reg = <500 40>; 243 reg = <0x500 0x40>;
242 interrupts = <1>; 244 interrupts = <1>;
243 interrupt-parent = < &qeic >; 245 interrupt-parent = <&qeic>;
244 mode = "cpu"; 246 mode = "cpu";
245 }; 247 };
246 248
247 usb@6c0 { 249 usb@6c0 {
248 compatible = "qe_udc"; 250 compatible = "qe_udc";
249 reg = <6c0 40 8B00 100>; 251 reg = <0x6c0 0x40 0x8b00 0x100>;
250 interrupts = <b>; 252 interrupts = <11>;
251 interrupt-parent = < &qeic >; 253 interrupt-parent = <&qeic>;
252 mode = "slave"; 254 mode = "slave";
253 }; 255 };
254 256
@@ -258,15 +260,15 @@
258 model = "UCC"; 260 model = "UCC";
259 cell-index = <1>; 261 cell-index = <1>;
260 device-id = <1>; 262 device-id = <1>;
261 reg = <2000 200>; 263 reg = <0x2000 0x200>;
262 interrupts = <20>; 264 interrupts = <32>;
263 interrupt-parent = < &qeic >; 265 interrupt-parent = <&qeic>;
264 local-mac-address = [ 00 00 00 00 00 00 ]; 266 local-mac-address = [ 00 00 00 00 00 00 ];
265 rx-clock-name = "none"; 267 rx-clock-name = "none";
266 tx-clock-name = "clk9"; 268 tx-clock-name = "clk9";
267 phy-handle = < &phy0 >; 269 phy-handle = <&phy0>;
268 phy-connection-type = "rgmii-id"; 270 phy-connection-type = "rgmii-id";
269 pio-handle = < &pio1 >; 271 pio-handle = <&pio1>;
270 }; 272 };
271 273
272 enet1: ucc@3000 { 274 enet1: ucc@3000 {
@@ -275,33 +277,33 @@
275 model = "UCC"; 277 model = "UCC";
276 cell-index = <2>; 278 cell-index = <2>;
277 device-id = <2>; 279 device-id = <2>;
278 reg = <3000 200>; 280 reg = <0x3000 0x200>;
279 interrupts = <21>; 281 interrupts = <33>;
280 interrupt-parent = < &qeic >; 282 interrupt-parent = <&qeic>;
281 local-mac-address = [ 00 00 00 00 00 00 ]; 283 local-mac-address = [ 00 00 00 00 00 00 ];
282 rx-clock-name = "none"; 284 rx-clock-name = "none";
283 tx-clock-name = "clk4"; 285 tx-clock-name = "clk4";
284 phy-handle = < &phy1 >; 286 phy-handle = <&phy1>;
285 phy-connection-type = "rgmii-id"; 287 phy-connection-type = "rgmii-id";
286 pio-handle = < &pio2 >; 288 pio-handle = <&pio2>;
287 }; 289 };
288 290
289 mdio@2120 { 291 mdio@2120 {
290 #address-cells = <1>; 292 #address-cells = <1>;
291 #size-cells = <0>; 293 #size-cells = <0>;
292 reg = <2120 18>; 294 reg = <0x2120 0x18>;
293 compatible = "fsl,ucc-mdio"; 295 compatible = "fsl,ucc-mdio";
294 296
295 phy0: ethernet-phy@00 { 297 phy0: ethernet-phy@00 {
296 interrupt-parent = < &ipic >; 298 interrupt-parent = <&ipic>;
297 interrupts = <11 8>; 299 interrupts = <17 0x8>;
298 reg = <0>; 300 reg = <0x0>;
299 device_type = "ethernet-phy"; 301 device_type = "ethernet-phy";
300 }; 302 };
301 phy1: ethernet-phy@01 { 303 phy1: ethernet-phy@01 {
302 interrupt-parent = < &ipic >; 304 interrupt-parent = <&ipic>;
303 interrupts = <12 8>; 305 interrupts = <18 0x8>;
304 reg = <1>; 306 reg = <0x1>;
305 device_type = "ethernet-phy"; 307 device_type = "ethernet-phy";
306 }; 308 };
307 }; 309 };
@@ -311,70 +313,70 @@
311 compatible = "fsl,qe-ic"; 313 compatible = "fsl,qe-ic";
312 #address-cells = <0>; 314 #address-cells = <0>;
313 #interrupt-cells = <1>; 315 #interrupt-cells = <1>;
314 reg = <80 80>; 316 reg = <0x80 0x80>;
315 big-endian; 317 big-endian;
316 interrupts = <20 8 21 8>; //high:32 low:33 318 interrupts = <32 0x8 33 0x8>; // high:32 low:33
317 interrupt-parent = < &ipic >; 319 interrupt-parent = <&ipic>;
318 }; 320 };
319 }; 321 };
320 322
321 pci0: pci@e0008500 { 323 pci0: pci@e0008500 {
322 cell-index = <1>; 324 cell-index = <1>;
323 interrupt-map-mask = <f800 0 0 7>; 325 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
324 interrupt-map = < 326 interrupt-map = <
325 327
326 /* IDSEL 0x11 AD17 */ 328 /* IDSEL 0x11 AD17 */
327 8800 0 0 1 &ipic 14 8 329 0x8800 0x0 0x0 0x1 &ipic 20 0x8
328 8800 0 0 2 &ipic 15 8 330 0x8800 0x0 0x0 0x2 &ipic 21 0x8
329 8800 0 0 3 &ipic 16 8 331 0x8800 0x0 0x0 0x3 &ipic 22 0x8
330 8800 0 0 4 &ipic 17 8 332 0x8800 0x0 0x0 0x4 &ipic 23 0x8
331 333
332 /* IDSEL 0x12 AD18 */ 334 /* IDSEL 0x12 AD18 */
333 9000 0 0 1 &ipic 16 8 335 0x9000 0x0 0x0 0x1 &ipic 22 0x8
334 9000 0 0 2 &ipic 17 8 336 0x9000 0x0 0x0 0x2 &ipic 23 0x8
335 9000 0 0 3 &ipic 14 8 337 0x9000 0x0 0x0 0x3 &ipic 20 0x8
336 9000 0 0 4 &ipic 15 8 338 0x9000 0x0 0x0 0x4 &ipic 21 0x8
337 339
338 /* IDSEL 0x13 AD19 */ 340 /* IDSEL 0x13 AD19 */
339 9800 0 0 1 &ipic 17 8 341 0x9800 0x0 0x0 0x1 &ipic 23 0x8
340 9800 0 0 2 &ipic 14 8 342 0x9800 0x0 0x0 0x2 &ipic 20 0x8
341 9800 0 0 3 &ipic 15 8 343 0x9800 0x0 0x0 0x3 &ipic 21 0x8
342 9800 0 0 4 &ipic 16 8 344 0x9800 0x0 0x0 0x4 &ipic 22 0x8
343 345
344 /* IDSEL 0x15 AD21*/ 346 /* IDSEL 0x15 AD21*/
345 a800 0 0 1 &ipic 14 8 347 0xa800 0x0 0x0 0x1 &ipic 20 0x8
346 a800 0 0 2 &ipic 15 8 348 0xa800 0x0 0x0 0x2 &ipic 21 0x8
347 a800 0 0 3 &ipic 16 8 349 0xa800 0x0 0x0 0x3 &ipic 22 0x8
348 a800 0 0 4 &ipic 17 8 350 0xa800 0x0 0x0 0x4 &ipic 23 0x8
349 351
350 /* IDSEL 0x16 AD22*/ 352 /* IDSEL 0x16 AD22*/
351 b000 0 0 1 &ipic 17 8 353 0xb000 0x0 0x0 0x1 &ipic 23 0x8
352 b000 0 0 2 &ipic 14 8 354 0xb000 0x0 0x0 0x2 &ipic 20 0x8
353 b000 0 0 3 &ipic 15 8 355 0xb000 0x0 0x0 0x3 &ipic 21 0x8
354 b000 0 0 4 &ipic 16 8 356 0xb000 0x0 0x0 0x4 &ipic 22 0x8
355 357
356 /* IDSEL 0x17 AD23*/ 358 /* IDSEL 0x17 AD23*/
357 b800 0 0 1 &ipic 16 8 359 0xb800 0x0 0x0 0x1 &ipic 22 0x8
358 b800 0 0 2 &ipic 17 8 360 0xb800 0x0 0x0 0x2 &ipic 23 0x8
359 b800 0 0 3 &ipic 14 8 361 0xb800 0x0 0x0 0x3 &ipic 20 0x8
360 b800 0 0 4 &ipic 15 8 362 0xb800 0x0 0x0 0x4 &ipic 21 0x8
361 363
362 /* IDSEL 0x18 AD24*/ 364 /* IDSEL 0x18 AD24*/
363 c000 0 0 1 &ipic 15 8 365 0xc000 0x0 0x0 0x1 &ipic 21 0x8
364 c000 0 0 2 &ipic 16 8 366 0xc000 0x0 0x0 0x2 &ipic 22 0x8
365 c000 0 0 3 &ipic 17 8 367 0xc000 0x0 0x0 0x3 &ipic 23 0x8
366 c000 0 0 4 &ipic 14 8>; 368 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
367 interrupt-parent = < &ipic >; 369 interrupt-parent = <&ipic>;
368 interrupts = <42 8>; 370 interrupts = <66 0x8>;
369 bus-range = <0 0>; 371 bus-range = <0 0>;
370 ranges = <02000000 0 a0000000 a0000000 0 10000000 372 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
371 42000000 0 80000000 80000000 0 10000000 373 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
372 01000000 0 00000000 e2000000 0 00100000>; 374 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
373 clock-frequency = <3f940aa>; 375 clock-frequency = <66666666>;
374 #interrupt-cells = <1>; 376 #interrupt-cells = <1>;
375 #size-cells = <2>; 377 #size-cells = <2>;
376 #address-cells = <3>; 378 #address-cells = <3>;
377 reg = <e0008500 100>; 379 reg = <0xe0008500 0x100>;
378 compatible = "fsl,mpc8349-pci"; 380 compatible = "fsl,mpc8349-pci";
379 device_type = "pci"; 381 device_type = "pci";
380 }; 382 };
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 3b9611f189e1..a3637fff73cc 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -31,11 +31,11 @@
31 31
32 PowerPC,8377@0 { 32 PowerPC,8377@0 {
33 device_type = "cpu"; 33 device_type = "cpu";
34 reg = <0>; 34 reg = <0x0>;
35 d-cache-line-size = <0x20>; 35 d-cache-line-size = <32>;
36 i-cache-line-size = <0x20>; 36 i-cache-line-size = <32>;
37 d-cache-size = <0x8000>; // L1, 32K 37 d-cache-size = <32768>;
38 i-cache-size = <0x8000>; // L1, 32K 38 i-cache-size = <32768>;
39 timebase-frequency = <0>; 39 timebase-frequency = <0>;
40 bus-frequency = <0>; 40 bus-frequency = <0>;
41 clock-frequency = <0>; 41 clock-frequency = <0>;
@@ -66,8 +66,8 @@
66 cell-index = <0>; 66 cell-index = <0>;
67 compatible = "fsl-i2c"; 67 compatible = "fsl-i2c";
68 reg = <0x3000 0x100>; 68 reg = <0x3000 0x100>;
69 interrupts = <0xe 0x8>; 69 interrupts = <14 0x8>;
70 interrupt-parent = < &ipic >; 70 interrupt-parent = <&ipic>;
71 dfsrr; 71 dfsrr;
72 }; 72 };
73 73
@@ -77,8 +77,8 @@
77 cell-index = <1>; 77 cell-index = <1>;
78 compatible = "fsl-i2c"; 78 compatible = "fsl-i2c";
79 reg = <0x3100 0x100>; 79 reg = <0x3100 0x100>;
80 interrupts = <0xf 0x8>; 80 interrupts = <15 0x8>;
81 interrupt-parent = < &ipic >; 81 interrupt-parent = <&ipic>;
82 dfsrr; 82 dfsrr;
83 }; 83 };
84 84
@@ -86,8 +86,8 @@
86 cell-index = <0>; 86 cell-index = <0>;
87 compatible = "fsl,spi"; 87 compatible = "fsl,spi";
88 reg = <0x7000 0x1000>; 88 reg = <0x7000 0x1000>;
89 interrupts = <0x10 0x8>; 89 interrupts = <16 0x8>;
90 interrupt-parent = < &ipic >; 90 interrupt-parent = <&ipic>;
91 mode = "cpu"; 91 mode = "cpu";
92 }; 92 };
93 93
@@ -97,8 +97,8 @@
97 reg = <0x23000 0x1000>; 97 reg = <0x23000 0x1000>;
98 #address-cells = <1>; 98 #address-cells = <1>;
99 #size-cells = <0>; 99 #size-cells = <0>;
100 interrupt-parent = < &ipic >; 100 interrupt-parent = <&ipic>;
101 interrupts = <0x26 0x8>; 101 interrupts = <38 0x8>;
102 phy_type = "utmi_wide"; 102 phy_type = "utmi_wide";
103 }; 103 };
104 104
@@ -108,15 +108,15 @@
108 compatible = "fsl,gianfar-mdio"; 108 compatible = "fsl,gianfar-mdio";
109 reg = <0x24520 0x20>; 109 reg = <0x24520 0x20>;
110 phy2: ethernet-phy@2 { 110 phy2: ethernet-phy@2 {
111 interrupt-parent = < &ipic >; 111 interrupt-parent = <&ipic>;
112 interrupts = <0x11 0x8>; 112 interrupts = <17 0x8>;
113 reg = <2>; 113 reg = <0x2>;
114 device_type = "ethernet-phy"; 114 device_type = "ethernet-phy";
115 }; 115 };
116 phy3: ethernet-phy@3 { 116 phy3: ethernet-phy@3 {
117 interrupt-parent = < &ipic >; 117 interrupt-parent = <&ipic>;
118 interrupts = <0x12 0x8>; 118 interrupts = <18 0x8>;
119 reg = <3>; 119 reg = <0x3>;
120 device_type = "ethernet-phy"; 120 device_type = "ethernet-phy";
121 }; 121 };
122 }; 122 };
@@ -128,10 +128,10 @@
128 compatible = "gianfar"; 128 compatible = "gianfar";
129 reg = <0x24000 0x1000>; 129 reg = <0x24000 0x1000>;
130 local-mac-address = [ 00 00 00 00 00 00 ]; 130 local-mac-address = [ 00 00 00 00 00 00 ];
131 interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>; 131 interrupts = <32 0x8 33 0x8 34 0x8>;
132 phy-connection-type = "mii"; 132 phy-connection-type = "mii";
133 interrupt-parent = < &ipic >; 133 interrupt-parent = <&ipic>;
134 phy-handle = < &phy2 >; 134 phy-handle = <&phy2>;
135 }; 135 };
136 136
137 enet1: ethernet@25000 { 137 enet1: ethernet@25000 {
@@ -141,10 +141,10 @@
141 compatible = "gianfar"; 141 compatible = "gianfar";
142 reg = <0x25000 0x1000>; 142 reg = <0x25000 0x1000>;
143 local-mac-address = [ 00 00 00 00 00 00 ]; 143 local-mac-address = [ 00 00 00 00 00 00 ];
144 interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>; 144 interrupts = <35 0x8 36 0x8 37 0x8>;
145 phy-connection-type = "mii"; 145 phy-connection-type = "mii";
146 interrupt-parent = < &ipic >; 146 interrupt-parent = <&ipic>;
147 phy-handle = < &phy3 >; 147 phy-handle = <&phy3>;
148 }; 148 };
149 149
150 serial0: serial@4500 { 150 serial0: serial@4500 {
@@ -153,8 +153,8 @@
153 compatible = "ns16550"; 153 compatible = "ns16550";
154 reg = <0x4500 0x100>; 154 reg = <0x4500 0x100>;
155 clock-frequency = <0>; 155 clock-frequency = <0>;
156 interrupts = <0x9 0x8>; 156 interrupts = <9 0x8>;
157 interrupt-parent = < &ipic >; 157 interrupt-parent = <&ipic>;
158 }; 158 };
159 159
160 serial1: serial@4600 { 160 serial1: serial@4600 {
@@ -163,19 +163,19 @@
163 compatible = "ns16550"; 163 compatible = "ns16550";
164 reg = <0x4600 0x100>; 164 reg = <0x4600 0x100>;
165 clock-frequency = <0>; 165 clock-frequency = <0>;
166 interrupts = <0xa 0x8>; 166 interrupts = <10 0x8>;
167 interrupt-parent = < &ipic >; 167 interrupt-parent = <&ipic>;
168 }; 168 };
169 169
170 crypto@30000 { 170 crypto@30000 {
171 model = "SEC3"; 171 model = "SEC3";
172 compatible = "talitos"; 172 compatible = "talitos";
173 reg = <0x30000 0x10000>; 173 reg = <0x30000 0x10000>;
174 interrupts = <0xb 0x8>; 174 interrupts = <11 0x8>;
175 interrupt-parent = < &ipic >; 175 interrupt-parent = <&ipic>;
176 /* Rev. 3.0 geometry */ 176 /* Rev. 3.0 geometry */
177 num-channels = <4>; 177 num-channels = <4>;
178 channel-fifo-len = <0x18>; 178 channel-fifo-len = <24>;
179 exec-units-mask = <0x000001fe>; 179 exec-units-mask = <0x000001fe>;
180 descriptor-types-mask = <0x03ab0ebf>; 180 descriptor-types-mask = <0x03ab0ebf>;
181 }; 181 };
@@ -184,22 +184,22 @@
184 model = "eSDHC"; 184 model = "eSDHC";
185 compatible = "fsl,esdhc"; 185 compatible = "fsl,esdhc";
186 reg = <0x2e000 0x1000>; 186 reg = <0x2e000 0x1000>;
187 interrupts = <0x2a 0x8>; 187 interrupts = <42 0x8>;
188 interrupt-parent = < &ipic >; 188 interrupt-parent = <&ipic>;
189 }; 189 };
190 190
191 sata@18000 { 191 sata@18000 {
192 compatible = "fsl,mpc8379-sata"; 192 compatible = "fsl,mpc8379-sata";
193 reg = <0x18000 0x1000>; 193 reg = <0x18000 0x1000>;
194 interrupts = <0x2c 0x8>; 194 interrupts = <44 0x8>;
195 interrupt-parent = < &ipic >; 195 interrupt-parent = <&ipic>;
196 }; 196 };
197 197
198 sata@19000 { 198 sata@19000 {
199 compatible = "fsl,mpc8379-sata"; 199 compatible = "fsl,mpc8379-sata";
200 reg = <0x19000 0x1000>; 200 reg = <0x19000 0x1000>;
201 interrupts = <0x2d 0x8>; 201 interrupts = <45 0x8>;
202 interrupt-parent = < &ipic >; 202 interrupt-parent = <&ipic>;
203 }; 203 };
204 204
205 /* IPIC 205 /* IPIC
@@ -223,49 +223,49 @@
223 interrupt-map = < 223 interrupt-map = <
224 224
225 /* IDSEL 0x11 */ 225 /* IDSEL 0x11 */
226 0x8800 0x0 0x0 0x1 &ipic 0x14 0x8 226 0x8800 0x0 0x0 0x1 &ipic 20 0x8
227 0x8800 0x0 0x0 0x2 &ipic 0x15 0x8 227 0x8800 0x0 0x0 0x2 &ipic 21 0x8
228 0x8800 0x0 0x0 0x3 &ipic 0x16 0x8 228 0x8800 0x0 0x0 0x3 &ipic 22 0x8
229 0x8800 0x0 0x0 0x4 &ipic 0x17 0x8 229 0x8800 0x0 0x0 0x4 &ipic 23 0x8
230 230
231 /* IDSEL 0x12 */ 231 /* IDSEL 0x12 */
232 0x9000 0x0 0x0 0x1 &ipic 0x16 0x8 232 0x9000 0x0 0x0 0x1 &ipic 22 0x8
233 0x9000 0x0 0x0 0x2 &ipic 0x17 0x8 233 0x9000 0x0 0x0 0x2 &ipic 23 0x8
234 0x9000 0x0 0x0 0x3 &ipic 0x14 0x8 234 0x9000 0x0 0x0 0x3 &ipic 20 0x8
235 0x9000 0x0 0x0 0x4 &ipic 0x15 0x8 235 0x9000 0x0 0x0 0x4 &ipic 21 0x8
236 236
237 /* IDSEL 0x13 */ 237 /* IDSEL 0x13 */
238 0x9800 0x0 0x0 0x1 &ipic 0x17 0x8 238 0x9800 0x0 0x0 0x1 &ipic 23 0x8
239 0x9800 0x0 0x0 0x2 &ipic 0x14 0x8 239 0x9800 0x0 0x0 0x2 &ipic 20 0x8
240 0x9800 0x0 0x0 0x3 &ipic 0x15 0x8 240 0x9800 0x0 0x0 0x3 &ipic 21 0x8
241 0x9800 0x0 0x0 0x4 &ipic 0x16 0x8 241 0x9800 0x0 0x0 0x4 &ipic 22 0x8
242 242
243 /* IDSEL 0x15 */ 243 /* IDSEL 0x15 */
244 0xa800 0x0 0x0 0x1 &ipic 0x14 0x8 244 0xa800 0x0 0x0 0x1 &ipic 20 0x8
245 0xa800 0x0 0x0 0x2 &ipic 0x15 0x8 245 0xa800 0x0 0x0 0x2 &ipic 21 0x8
246 0xa800 0x0 0x0 0x3 &ipic 0x16 0x8 246 0xa800 0x0 0x0 0x3 &ipic 22 0x8
247 0xa800 0x0 0x0 0x4 &ipic 0x17 0x8 247 0xa800 0x0 0x0 0x4 &ipic 23 0x8
248 248
249 /* IDSEL 0x16 */ 249 /* IDSEL 0x16 */
250 0xb000 0x0 0x0 0x1 &ipic 0x17 0x8 250 0xb000 0x0 0x0 0x1 &ipic 23 0x8
251 0xb000 0x0 0x0 0x2 &ipic 0x14 0x8 251 0xb000 0x0 0x0 0x2 &ipic 20 0x8
252 0xb000 0x0 0x0 0x3 &ipic 0x15 0x8 252 0xb000 0x0 0x0 0x3 &ipic 21 0x8
253 0xb000 0x0 0x0 0x4 &ipic 0x16 0x8 253 0xb000 0x0 0x0 0x4 &ipic 22 0x8
254 254
255 /* IDSEL 0x17 */ 255 /* IDSEL 0x17 */
256 0xb800 0x0 0x0 0x1 &ipic 0x16 0x8 256 0xb800 0x0 0x0 0x1 &ipic 22 0x8
257 0xb800 0x0 0x0 0x2 &ipic 0x17 0x8 257 0xb800 0x0 0x0 0x2 &ipic 23 0x8
258 0xb800 0x0 0x0 0x3 &ipic 0x14 0x8 258 0xb800 0x0 0x0 0x3 &ipic 20 0x8
259 0xb800 0x0 0x0 0x4 &ipic 0x15 0x8 259 0xb800 0x0 0x0 0x4 &ipic 21 0x8
260 260
261 /* IDSEL 0x18 */ 261 /* IDSEL 0x18 */
262 0xc000 0x0 0x0 0x1 &ipic 0x15 0x8 262 0xc000 0x0 0x0 0x1 &ipic 21 0x8
263 0xc000 0x0 0x0 0x2 &ipic 0x16 0x8 263 0xc000 0x0 0x0 0x2 &ipic 22 0x8
264 0xc000 0x0 0x0 0x3 &ipic 0x17 0x8 264 0xc000 0x0 0x0 0x3 &ipic 23 0x8
265 0xc000 0x0 0x0 0x4 &ipic 0x14 0x8>; 265 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
266 interrupt-parent = < &ipic >; 266 interrupt-parent = <&ipic>;
267 interrupts = <0x42 0x8>; 267 interrupts = <66 0x8>;
268 bus-range = <0 0>; 268 bus-range = <0x0 0x0>;
269 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 269 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
270 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 270 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
271 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; 271 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index cd60005b2bbe..440aa4dfab0c 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -30,7 +30,7 @@
30 30
31 PowerPC,8377@0 { 31 PowerPC,8377@0 {
32 device_type = "cpu"; 32 device_type = "cpu";
33 reg = <0>; 33 reg = <0x0>;
34 d-cache-line-size = <32>; 34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>; 35 i-cache-line-size = <32>;
36 d-cache-size = <32768>; 36 d-cache-size = <32768>;
@@ -51,22 +51,22 @@
51 #size-cells = <1>; 51 #size-cells = <1>;
52 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus"; 52 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>; 53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 8>; 54 interrupts = <77 0x8>;
55 interrupt-parent = <&ipic>; 55 interrupt-parent = <&ipic>;
56 56
57 // CS0 and CS1 are swapped when 57 // CS0 and CS1 are swapped when
58 // booting from nand, but the 58 // booting from nand, but the
59 // addresses are the same. 59 // addresses are the same.
60 ranges = <0 0 0xfe000000 0x00800000 60 ranges = <0x0 0x0 0xfe000000 0x00800000
61 1 0 0xe0600000 0x00008000 61 0x1 0x0 0xe0600000 0x00008000
62 2 0 0xf0000000 0x00020000 62 0x2 0x0 0xf0000000 0x00020000
63 3 0 0xfa000000 0x00008000>; 63 0x3 0x0 0xfa000000 0x00008000>;
64 64
65 flash@0,0 { 65 flash@0,0 {
66 #address-cells = <1>; 66 #address-cells = <1>;
67 #size-cells = <1>; 67 #size-cells = <1>;
68 compatible = "cfi-flash"; 68 compatible = "cfi-flash";
69 reg = <0 0 0x800000>; 69 reg = <0x0 0x0 0x800000>;
70 bank-width = <2>; 70 bank-width = <2>;
71 device-width = <1>; 71 device-width = <1>;
72 }; 72 };
@@ -76,7 +76,7 @@
76 #size-cells = <1>; 76 #size-cells = <1>;
77 compatible = "fsl,mpc8377-fcm-nand", 77 compatible = "fsl,mpc8377-fcm-nand",
78 "fsl,elbc-fcm-nand"; 78 "fsl,elbc-fcm-nand";
79 reg = <1 0 0x8000>; 79 reg = <0x1 0x0 0x8000>;
80 80
81 u-boot@0 { 81 u-boot@0 {
82 reg = <0x0 0x100000>; 82 reg = <0x0 0x100000>;
@@ -97,7 +97,7 @@
97 #size-cells = <1>; 97 #size-cells = <1>;
98 device_type = "soc"; 98 device_type = "soc";
99 compatible = "simple-bus"; 99 compatible = "simple-bus";
100 ranges = <0 0xe0000000 0x00100000>; 100 ranges = <0x0 0xe0000000 0x00100000>;
101 reg = <0xe0000000 0x00000200>; 101 reg = <0xe0000000 0x00000200>;
102 bus-frequency = <0>; 102 bus-frequency = <0>;
103 103
@@ -113,8 +113,8 @@
113 cell-index = <0>; 113 cell-index = <0>;
114 compatible = "fsl-i2c"; 114 compatible = "fsl-i2c";
115 reg = <0x3000 0x100>; 115 reg = <0x3000 0x100>;
116 interrupts = <14 8>; 116 interrupts = <14 0x8>;
117 interrupt-parent = < &ipic >; 117 interrupt-parent = <&ipic>;
118 dfsrr; 118 dfsrr;
119 rtc@68 { 119 rtc@68 {
120 device_type = "rtc"; 120 device_type = "rtc";
@@ -129,8 +129,8 @@
129 cell-index = <1>; 129 cell-index = <1>;
130 compatible = "fsl-i2c"; 130 compatible = "fsl-i2c";
131 reg = <0x3100 0x100>; 131 reg = <0x3100 0x100>;
132 interrupts = <15 8>; 132 interrupts = <15 0x8>;
133 interrupt-parent = < &ipic >; 133 interrupt-parent = <&ipic>;
134 dfsrr; 134 dfsrr;
135 }; 135 };
136 136
@@ -138,8 +138,8 @@
138 cell-index = <0>; 138 cell-index = <0>;
139 compatible = "fsl,spi"; 139 compatible = "fsl,spi";
140 reg = <0x7000 0x1000>; 140 reg = <0x7000 0x1000>;
141 interrupts = <16 8>; 141 interrupts = <16 0x8>;
142 interrupt-parent = < &ipic >; 142 interrupt-parent = <&ipic>;
143 mode = "cpu"; 143 mode = "cpu";
144 }; 144 };
145 145
@@ -149,8 +149,8 @@
149 reg = <0x23000 0x1000>; 149 reg = <0x23000 0x1000>;
150 #address-cells = <1>; 150 #address-cells = <1>;
151 #size-cells = <0>; 151 #size-cells = <0>;
152 interrupt-parent = < &ipic >; 152 interrupt-parent = <&ipic>;
153 interrupts = <38 8>; 153 interrupts = <38 0x8>;
154 phy_type = "utmi"; 154 phy_type = "utmi";
155 }; 155 };
156 156
@@ -160,15 +160,15 @@
160 compatible = "fsl,gianfar-mdio"; 160 compatible = "fsl,gianfar-mdio";
161 reg = <0x24520 0x20>; 161 reg = <0x24520 0x20>;
162 phy2: ethernet-phy@2 { 162 phy2: ethernet-phy@2 {
163 interrupt-parent = < &ipic >; 163 interrupt-parent = <&ipic>;
164 interrupts = <17 8>; 164 interrupts = <17 0x8>;
165 reg = <2>; 165 reg = <0x2>;
166 device_type = "ethernet-phy"; 166 device_type = "ethernet-phy";
167 }; 167 };
168 phy3: ethernet-phy@3 { 168 phy3: ethernet-phy@3 {
169 interrupt-parent = < &ipic >; 169 interrupt-parent = <&ipic>;
170 interrupts = <18 8>; 170 interrupts = <18 0x8>;
171 reg = <3>; 171 reg = <0x3>;
172 device_type = "ethernet-phy"; 172 device_type = "ethernet-phy";
173 }; 173 };
174 }; 174 };
@@ -180,10 +180,10 @@
180 compatible = "gianfar"; 180 compatible = "gianfar";
181 reg = <0x24000 0x1000>; 181 reg = <0x24000 0x1000>;
182 local-mac-address = [ 00 00 00 00 00 00 ]; 182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <32 8 33 8 34 8>; 183 interrupts = <32 0x8 33 0x8 34 0x8>;
184 phy-connection-type = "mii"; 184 phy-connection-type = "mii";
185 interrupt-parent = < &ipic >; 185 interrupt-parent = <&ipic>;
186 phy-handle = < &phy2 >; 186 phy-handle = <&phy2>;
187 }; 187 };
188 188
189 enet1: ethernet@25000 { 189 enet1: ethernet@25000 {
@@ -193,10 +193,10 @@
193 compatible = "gianfar"; 193 compatible = "gianfar";
194 reg = <0x25000 0x1000>; 194 reg = <0x25000 0x1000>;
195 local-mac-address = [ 00 00 00 00 00 00 ]; 195 local-mac-address = [ 00 00 00 00 00 00 ];
196 interrupts = <35 8 36 8 37 8>; 196 interrupts = <35 0x8 36 0x8 37 0x8>;
197 phy-connection-type = "mii"; 197 phy-connection-type = "mii";
198 interrupt-parent = < &ipic >; 198 interrupt-parent = <&ipic>;
199 phy-handle = < &phy3 >; 199 phy-handle = <&phy3>;
200 }; 200 };
201 201
202 serial0: serial@4500 { 202 serial0: serial@4500 {
@@ -205,8 +205,8 @@
205 compatible = "ns16550"; 205 compatible = "ns16550";
206 reg = <0x4500 0x100>; 206 reg = <0x4500 0x100>;
207 clock-frequency = <0>; 207 clock-frequency = <0>;
208 interrupts = <9 8>; 208 interrupts = <9 0x8>;
209 interrupt-parent = < &ipic >; 209 interrupt-parent = <&ipic>;
210 }; 210 };
211 211
212 serial1: serial@4600 { 212 serial1: serial@4600 {
@@ -215,8 +215,8 @@
215 compatible = "ns16550"; 215 compatible = "ns16550";
216 reg = <0x4600 0x100>; 216 reg = <0x4600 0x100>;
217 clock-frequency = <0>; 217 clock-frequency = <0>;
218 interrupts = <10 8>; 218 interrupts = <10 0x8>;
219 interrupt-parent = < &ipic >; 219 interrupt-parent = <&ipic>;
220 }; 220 };
221 221
222 crypto@30000 { 222 crypto@30000 {
@@ -224,8 +224,8 @@
224 device_type = "crypto"; 224 device_type = "crypto";
225 compatible = "talitos"; 225 compatible = "talitos";
226 reg = <0x30000 0x10000>; 226 reg = <0x30000 0x10000>;
227 interrupts = <11 8>; 227 interrupts = <11 0x8>;
228 interrupt-parent = < &ipic >; 228 interrupt-parent = <&ipic>;
229 /* Rev. 3.0 geometry */ 229 /* Rev. 3.0 geometry */
230 num-channels = <4>; 230 num-channels = <4>;
231 channel-fifo-len = <24>; 231 channel-fifo-len = <24>;
@@ -236,15 +236,15 @@
236 sata@18000 { 236 sata@18000 {
237 compatible = "fsl,mpc8377-sata", "fsl,pq-sata"; 237 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
238 reg = <0x18000 0x1000>; 238 reg = <0x18000 0x1000>;
239 interrupts = <44 8>; 239 interrupts = <44 0x8>;
240 interrupt-parent = < &ipic >; 240 interrupt-parent = <&ipic>;
241 }; 241 };
242 242
243 sata@19000 { 243 sata@19000 {
244 compatible = "fsl,mpc8377-sata", "fsl,pq-sata"; 244 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
245 reg = <0x19000 0x1000>; 245 reg = <0x19000 0x1000>;
246 interrupts = <45 8>; 246 interrupts = <45 0x8>;
247 interrupt-parent = < &ipic >; 247 interrupt-parent = <&ipic>;
248 }; 248 };
249 249
250 /* IPIC 250 /* IPIC
@@ -268,23 +268,23 @@
268 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ 268 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
269 269
270 /* IDSEL AD14 IRQ6 inta */ 270 /* IDSEL AD14 IRQ6 inta */
271 0x7000 0 0 1 &ipic 22 8 271 0x7000 0x0 0x0 0x1 &ipic 22 0x8
272 272
273 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ 273 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
274 0x7800 0 0 1 &ipic 21 8 274 0x7800 0x0 0x0 0x1 &ipic 21 0x8
275 0x7800 0 0 2 &ipic 22 8 275 0x7800 0x0 0x0 0x2 &ipic 22 0x8
276 0x7800 0 0 4 &ipic 23 8 276 0x7800 0x0 0x0 0x4 &ipic 23 0x8
277 277
278 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ 278 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
279 0xE000 0 0 1 &ipic 23 8 279 0xE000 0x0 0x0 0x1 &ipic 23 0x8
280 0xE000 0 0 2 &ipic 21 8 280 0xE000 0x0 0x0 0x2 &ipic 21 0x8
281 0xE000 0 0 3 &ipic 22 8>; 281 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
282 interrupt-parent = < &ipic >; 282 interrupt-parent = <&ipic>;
283 interrupts = <66 8>; 283 interrupts = <66 0x8>;
284 bus-range = <0 0>; 284 bus-range = <0 0>;
285 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 285 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
286 0x42000000 0 0x80000000 0x80000000 0 0x10000000 286 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
287 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>; 287 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
288 clock-frequency = <66666666>; 288 clock-frequency = <66666666>;
289 #interrupt-cells = <1>; 289 #interrupt-cells = <1>;
290 #size-cells = <2>; 290 #size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 386f4a037b33..533e9b06cc8f 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -31,11 +31,11 @@
31 31
32 PowerPC,8378@0 { 32 PowerPC,8378@0 {
33 device_type = "cpu"; 33 device_type = "cpu";
34 reg = <0>; 34 reg = <0x0>;
35 d-cache-line-size = <0x20>; 35 d-cache-line-size = <32>;
36 i-cache-line-size = <0x20>; 36 i-cache-line-size = <32>;
37 d-cache-size = <0x8000>; // L1, 32K 37 d-cache-size = <32768>;
38 i-cache-size = <0x8000>; // L1, 32K 38 i-cache-size = <32768>;
39 timebase-frequency = <0>; 39 timebase-frequency = <0>;
40 bus-frequency = <0>; 40 bus-frequency = <0>;
41 clock-frequency = <0>; 41 clock-frequency = <0>;
@@ -66,8 +66,8 @@
66 cell-index = <0>; 66 cell-index = <0>;
67 compatible = "fsl-i2c"; 67 compatible = "fsl-i2c";
68 reg = <0x3000 0x100>; 68 reg = <0x3000 0x100>;
69 interrupts = <0xe 0x8>; 69 interrupts = <14 0x8>;
70 interrupt-parent = < &ipic >; 70 interrupt-parent = <&ipic>;
71 dfsrr; 71 dfsrr;
72 }; 72 };
73 73
@@ -77,8 +77,8 @@
77 cell-index = <1>; 77 cell-index = <1>;
78 compatible = "fsl-i2c"; 78 compatible = "fsl-i2c";
79 reg = <0x3100 0x100>; 79 reg = <0x3100 0x100>;
80 interrupts = <0xf 0x8>; 80 interrupts = <15 0x8>;
81 interrupt-parent = < &ipic >; 81 interrupt-parent = <&ipic>;
82 dfsrr; 82 dfsrr;
83 }; 83 };
84 84
@@ -86,8 +86,8 @@
86 cell-index = <0>; 86 cell-index = <0>;
87 compatible = "fsl,spi"; 87 compatible = "fsl,spi";
88 reg = <0x7000 0x1000>; 88 reg = <0x7000 0x1000>;
89 interrupts = <0x10 0x8>; 89 interrupts = <16 0x8>;
90 interrupt-parent = < &ipic >; 90 interrupt-parent = <&ipic>;
91 mode = "cpu"; 91 mode = "cpu";
92 }; 92 };
93 93
@@ -97,8 +97,8 @@
97 reg = <0x23000 0x1000>; 97 reg = <0x23000 0x1000>;
98 #address-cells = <1>; 98 #address-cells = <1>;
99 #size-cells = <0>; 99 #size-cells = <0>;
100 interrupt-parent = < &ipic >; 100 interrupt-parent = <&ipic>;
101 interrupts = <0x26 0x8>; 101 interrupts = <38 0x8>;
102 phy_type = "utmi_wide"; 102 phy_type = "utmi_wide";
103 }; 103 };
104 104
@@ -108,15 +108,15 @@
108 compatible = "fsl,gianfar-mdio"; 108 compatible = "fsl,gianfar-mdio";
109 reg = <0x24520 0x20>; 109 reg = <0x24520 0x20>;
110 phy2: ethernet-phy@2 { 110 phy2: ethernet-phy@2 {
111 interrupt-parent = < &ipic >; 111 interrupt-parent = <&ipic>;
112 interrupts = <0x11 0x8>; 112 interrupts = <17 0x8>;
113 reg = <2>; 113 reg = <0x2>;
114 device_type = "ethernet-phy"; 114 device_type = "ethernet-phy";
115 }; 115 };
116 phy3: ethernet-phy@3 { 116 phy3: ethernet-phy@3 {
117 interrupt-parent = < &ipic >; 117 interrupt-parent = <&ipic>;
118 interrupts = <0x12 0x8>; 118 interrupts = <18 0x8>;
119 reg = <3>; 119 reg = <0x3>;
120 device_type = "ethernet-phy"; 120 device_type = "ethernet-phy";
121 }; 121 };
122 }; 122 };
@@ -128,10 +128,10 @@
128 compatible = "gianfar"; 128 compatible = "gianfar";
129 reg = <0x24000 0x1000>; 129 reg = <0x24000 0x1000>;
130 local-mac-address = [ 00 00 00 00 00 00 ]; 130 local-mac-address = [ 00 00 00 00 00 00 ];
131 interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>; 131 interrupts = <32 0x8 33 0x8 34 0x8>;
132 phy-connection-type = "mii"; 132 phy-connection-type = "mii";
133 interrupt-parent = < &ipic >; 133 interrupt-parent = <&ipic>;
134 phy-handle = < &phy2 >; 134 phy-handle = <&phy2>;
135 }; 135 };
136 136
137 enet1: ethernet@25000 { 137 enet1: ethernet@25000 {
@@ -141,10 +141,10 @@
141 compatible = "gianfar"; 141 compatible = "gianfar";
142 reg = <0x25000 0x1000>; 142 reg = <0x25000 0x1000>;
143 local-mac-address = [ 00 00 00 00 00 00 ]; 143 local-mac-address = [ 00 00 00 00 00 00 ];
144 interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>; 144 interrupts = <35 0x8 36 0x8 37 0x8>;
145 phy-connection-type = "mii"; 145 phy-connection-type = "mii";
146 interrupt-parent = < &ipic >; 146 interrupt-parent = <&ipic>;
147 phy-handle = < &phy3 >; 147 phy-handle = <&phy3>;
148 }; 148 };
149 149
150 serial0: serial@4500 { 150 serial0: serial@4500 {
@@ -153,8 +153,8 @@
153 compatible = "ns16550"; 153 compatible = "ns16550";
154 reg = <0x4500 0x100>; 154 reg = <0x4500 0x100>;
155 clock-frequency = <0>; 155 clock-frequency = <0>;
156 interrupts = <0x9 0x8>; 156 interrupts = <9 0x8>;
157 interrupt-parent = < &ipic >; 157 interrupt-parent = <&ipic>;
158 }; 158 };
159 159
160 serial1: serial@4600 { 160 serial1: serial@4600 {
@@ -163,19 +163,19 @@
163 compatible = "ns16550"; 163 compatible = "ns16550";
164 reg = <0x4600 0x100>; 164 reg = <0x4600 0x100>;
165 clock-frequency = <0>; 165 clock-frequency = <0>;
166 interrupts = <0xa 0x8>; 166 interrupts = <10 0x8>;
167 interrupt-parent = < &ipic >; 167 interrupt-parent = <&ipic>;
168 }; 168 };
169 169
170 crypto@30000 { 170 crypto@30000 {
171 model = "SEC3"; 171 model = "SEC3";
172 compatible = "talitos"; 172 compatible = "talitos";
173 reg = <0x30000 0x10000>; 173 reg = <0x30000 0x10000>;
174 interrupts = <0xb 0x8>; 174 interrupts = <11 0x8>;
175 interrupt-parent = < &ipic >; 175 interrupt-parent = <&ipic>;
176 /* Rev. 3.0 geometry */ 176 /* Rev. 3.0 geometry */
177 num-channels = <4>; 177 num-channels = <4>;
178 channel-fifo-len = <0x18>; 178 channel-fifo-len = <24>;
179 exec-units-mask = <0x000001fe>; 179 exec-units-mask = <0x000001fe>;
180 descriptor-types-mask = <0x03ab0ebf>; 180 descriptor-types-mask = <0x03ab0ebf>;
181 }; 181 };
@@ -184,8 +184,8 @@
184 model = "eSDHC"; 184 model = "eSDHC";
185 compatible = "fsl,esdhc"; 185 compatible = "fsl,esdhc";
186 reg = <0x2e000 0x1000>; 186 reg = <0x2e000 0x1000>;
187 interrupts = <0x2a 0x8>; 187 interrupts = <42 0x8>;
188 interrupt-parent = < &ipic >; 188 interrupt-parent = <&ipic>;
189 }; 189 };
190 190
191 /* IPIC 191 /* IPIC
@@ -209,49 +209,49 @@
209 interrupt-map = < 209 interrupt-map = <
210 210
211 /* IDSEL 0x11 */ 211 /* IDSEL 0x11 */
212 0x8800 0x0 0x0 0x1 &ipic 0x14 0x8 212 0x8800 0x0 0x0 0x1 &ipic 20 0x8
213 0x8800 0x0 0x0 0x2 &ipic 0x15 0x8 213 0x8800 0x0 0x0 0x2 &ipic 21 0x8
214 0x8800 0x0 0x0 0x3 &ipic 0x16 0x8 214 0x8800 0x0 0x0 0x3 &ipic 22 0x8
215 0x8800 0x0 0x0 0x4 &ipic 0x17 0x8 215 0x8800 0x0 0x0 0x4 &ipic 23 0x8
216 216
217 /* IDSEL 0x12 */ 217 /* IDSEL 0x12 */
218 0x9000 0x0 0x0 0x1 &ipic 0x16 0x8 218 0x9000 0x0 0x0 0x1 &ipic 22 0x8
219 0x9000 0x0 0x0 0x2 &ipic 0x17 0x8 219 0x9000 0x0 0x0 0x2 &ipic 23 0x8
220 0x9000 0x0 0x0 0x3 &ipic 0x14 0x8 220 0x9000 0x0 0x0 0x3 &ipic 20 0x8
221 0x9000 0x0 0x0 0x4 &ipic 0x15 0x8 221 0x9000 0x0 0x0 0x4 &ipic 21 0x8
222 222
223 /* IDSEL 0x13 */ 223 /* IDSEL 0x13 */
224 0x9800 0x0 0x0 0x1 &ipic 0x17 0x8 224 0x9800 0x0 0x0 0x1 &ipic 23 0x8
225 0x9800 0x0 0x0 0x2 &ipic 0x14 0x8 225 0x9800 0x0 0x0 0x2 &ipic 20 0x8
226 0x9800 0x0 0x0 0x3 &ipic 0x15 0x8 226 0x9800 0x0 0x0 0x3 &ipic 21 0x8
227 0x9800 0x0 0x0 0x4 &ipic 0x16 0x8 227 0x9800 0x0 0x0 0x4 &ipic 22 0x8
228 228
229 /* IDSEL 0x15 */ 229 /* IDSEL 0x15 */
230 0xa800 0x0 0x0 0x1 &ipic 0x14 0x8 230 0xa800 0x0 0x0 0x1 &ipic 20 0x8
231 0xa800 0x0 0x0 0x2 &ipic 0x15 0x8 231 0xa800 0x0 0x0 0x2 &ipic 21 0x8
232 0xa800 0x0 0x0 0x3 &ipic 0x16 0x8 232 0xa800 0x0 0x0 0x3 &ipic 22 0x8
233 0xa800 0x0 0x0 0x4 &ipic 0x17 0x8 233 0xa800 0x0 0x0 0x4 &ipic 23 0x8
234 234
235 /* IDSEL 0x16 */ 235 /* IDSEL 0x16 */
236 0xb000 0x0 0x0 0x1 &ipic 0x17 0x8 236 0xb000 0x0 0x0 0x1 &ipic 23 0x8
237 0xb000 0x0 0x0 0x2 &ipic 0x14 0x8 237 0xb000 0x0 0x0 0x2 &ipic 20 0x8
238 0xb000 0x0 0x0 0x3 &ipic 0x15 0x8 238 0xb000 0x0 0x0 0x3 &ipic 21 0x8
239 0xb000 0x0 0x0 0x4 &ipic 0x16 0x8 239 0xb000 0x0 0x0 0x4 &ipic 22 0x8
240 240
241 /* IDSEL 0x17 */ 241 /* IDSEL 0x17 */
242 0xb800 0x0 0x0 0x1 &ipic 0x16 0x8 242 0xb800 0x0 0x0 0x1 &ipic 22 0x8
243 0xb800 0x0 0x0 0x2 &ipic 0x17 0x8 243 0xb800 0x0 0x0 0x2 &ipic 23 0x8
244 0xb800 0x0 0x0 0x3 &ipic 0x14 0x8 244 0xb800 0x0 0x0 0x3 &ipic 20 0x8
245 0xb800 0x0 0x0 0x4 &ipic 0x15 0x8 245 0xb800 0x0 0x0 0x4 &ipic 21 0x8
246 246
247 /* IDSEL 0x18 */ 247 /* IDSEL 0x18 */
248 0xc000 0x0 0x0 0x1 &ipic 0x15 0x8 248 0xc000 0x0 0x0 0x1 &ipic 21 0x8
249 0xc000 0x0 0x0 0x2 &ipic 0x16 0x8 249 0xc000 0x0 0x0 0x2 &ipic 22 0x8
250 0xc000 0x0 0x0 0x3 &ipic 0x17 0x8 250 0xc000 0x0 0x0 0x3 &ipic 23 0x8
251 0xc000 0x0 0x0 0x4 &ipic 0x14 0x8>; 251 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
252 interrupt-parent = < &ipic >; 252 interrupt-parent = <&ipic>;
253 interrupts = <0x42 0x8>; 253 interrupts = <66 0x8>;
254 bus-range = <0 0>; 254 bus-range = <0x0 0x0>;
255 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 255 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
256 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 256 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
257 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; 257 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index 03831a1d1cdd..92711534b179 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -30,7 +30,7 @@
30 30
31 PowerPC,8378@0 { 31 PowerPC,8378@0 {
32 device_type = "cpu"; 32 device_type = "cpu";
33 reg = <0>; 33 reg = <0x0>;
34 d-cache-line-size = <32>; 34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>; 35 i-cache-line-size = <32>;
36 d-cache-size = <32768>; 36 d-cache-size = <32768>;
@@ -51,22 +51,22 @@
51 #size-cells = <1>; 51 #size-cells = <1>;
52 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus"; 52 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>; 53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 8>; 54 interrupts = <77 0x8>;
55 interrupt-parent = <&ipic>; 55 interrupt-parent = <&ipic>;
56 56
57 // CS0 and CS1 are swapped when 57 // CS0 and CS1 are swapped when
58 // booting from nand, but the 58 // booting from nand, but the
59 // addresses are the same. 59 // addresses are the same.
60 ranges = <0 0 0xfe000000 0x00800000 60 ranges = <0x0 0x0 0xfe000000 0x00800000
61 1 0 0xe0600000 0x00008000 61 0x1 0x0 0xe0600000 0x00008000
62 2 0 0xf0000000 0x00020000 62 0x2 0x0 0xf0000000 0x00020000
63 3 0 0xfa000000 0x00008000>; 63 0x3 0x0 0xfa000000 0x00008000>;
64 64
65 flash@0,0 { 65 flash@0,0 {
66 #address-cells = <1>; 66 #address-cells = <1>;
67 #size-cells = <1>; 67 #size-cells = <1>;
68 compatible = "cfi-flash"; 68 compatible = "cfi-flash";
69 reg = <0 0 0x800000>; 69 reg = <0x0 0x0 0x800000>;
70 bank-width = <2>; 70 bank-width = <2>;
71 device-width = <1>; 71 device-width = <1>;
72 }; 72 };
@@ -76,7 +76,7 @@
76 #size-cells = <1>; 76 #size-cells = <1>;
77 compatible = "fsl,mpc8378-fcm-nand", 77 compatible = "fsl,mpc8378-fcm-nand",
78 "fsl,elbc-fcm-nand"; 78 "fsl,elbc-fcm-nand";
79 reg = <1 0 0x8000>; 79 reg = <0x1 0x0 0x8000>;
80 80
81 u-boot@0 { 81 u-boot@0 {
82 reg = <0x0 0x100000>; 82 reg = <0x0 0x100000>;
@@ -97,7 +97,7 @@
97 #size-cells = <1>; 97 #size-cells = <1>;
98 device_type = "soc"; 98 device_type = "soc";
99 compatible = "simple-bus"; 99 compatible = "simple-bus";
100 ranges = <0 0xe0000000 0x00100000>; 100 ranges = <0x0 0xe0000000 0x00100000>;
101 reg = <0xe0000000 0x00000200>; 101 reg = <0xe0000000 0x00000200>;
102 bus-frequency = <0>; 102 bus-frequency = <0>;
103 103
@@ -113,8 +113,8 @@
113 cell-index = <0>; 113 cell-index = <0>;
114 compatible = "fsl-i2c"; 114 compatible = "fsl-i2c";
115 reg = <0x3000 0x100>; 115 reg = <0x3000 0x100>;
116 interrupts = <14 8>; 116 interrupts = <14 0x8>;
117 interrupt-parent = < &ipic >; 117 interrupt-parent = <&ipic>;
118 dfsrr; 118 dfsrr;
119 rtc@68 { 119 rtc@68 {
120 device_type = "rtc"; 120 device_type = "rtc";
@@ -129,8 +129,8 @@
129 cell-index = <1>; 129 cell-index = <1>;
130 compatible = "fsl-i2c"; 130 compatible = "fsl-i2c";
131 reg = <0x3100 0x100>; 131 reg = <0x3100 0x100>;
132 interrupts = <15 8>; 132 interrupts = <15 0x8>;
133 interrupt-parent = < &ipic >; 133 interrupt-parent = <&ipic>;
134 dfsrr; 134 dfsrr;
135 }; 135 };
136 136
@@ -138,8 +138,8 @@
138 cell-index = <0>; 138 cell-index = <0>;
139 compatible = "fsl,spi"; 139 compatible = "fsl,spi";
140 reg = <0x7000 0x1000>; 140 reg = <0x7000 0x1000>;
141 interrupts = <16 8>; 141 interrupts = <16 0x8>;
142 interrupt-parent = < &ipic >; 142 interrupt-parent = <&ipic>;
143 mode = "cpu"; 143 mode = "cpu";
144 }; 144 };
145 145
@@ -149,8 +149,8 @@
149 reg = <0x23000 0x1000>; 149 reg = <0x23000 0x1000>;
150 #address-cells = <1>; 150 #address-cells = <1>;
151 #size-cells = <0>; 151 #size-cells = <0>;
152 interrupt-parent = < &ipic >; 152 interrupt-parent = <&ipic>;
153 interrupts = <38 8>; 153 interrupts = <38 0x8>;
154 phy_type = "utmi"; 154 phy_type = "utmi";
155 }; 155 };
156 156
@@ -160,15 +160,15 @@
160 compatible = "fsl,gianfar-mdio"; 160 compatible = "fsl,gianfar-mdio";
161 reg = <0x24520 0x20>; 161 reg = <0x24520 0x20>;
162 phy2: ethernet-phy@2 { 162 phy2: ethernet-phy@2 {
163 interrupt-parent = < &ipic >; 163 interrupt-parent = <&ipic>;
164 interrupts = <17 8>; 164 interrupts = <17 0x8>;
165 reg = <2>; 165 reg = <0x2>;
166 device_type = "ethernet-phy"; 166 device_type = "ethernet-phy";
167 }; 167 };
168 phy3: ethernet-phy@3 { 168 phy3: ethernet-phy@3 {
169 interrupt-parent = < &ipic >; 169 interrupt-parent = <&ipic>;
170 interrupts = <18 8>; 170 interrupts = <18 0x8>;
171 reg = <3>; 171 reg = <0x3>;
172 device_type = "ethernet-phy"; 172 device_type = "ethernet-phy";
173 }; 173 };
174 }; 174 };
@@ -180,10 +180,10 @@
180 compatible = "gianfar"; 180 compatible = "gianfar";
181 reg = <0x24000 0x1000>; 181 reg = <0x24000 0x1000>;
182 local-mac-address = [ 00 00 00 00 00 00 ]; 182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <32 8 33 8 34 8>; 183 interrupts = <32 0x8 33 0x8 34 0x8>;
184 phy-connection-type = "mii"; 184 phy-connection-type = "mii";
185 interrupt-parent = < &ipic >; 185 interrupt-parent = <&ipic>;
186 phy-handle = < &phy2 >; 186 phy-handle = <&phy2>;
187 }; 187 };
188 188
189 enet1: ethernet@25000 { 189 enet1: ethernet@25000 {
@@ -193,10 +193,10 @@
193 compatible = "gianfar"; 193 compatible = "gianfar";
194 reg = <0x25000 0x1000>; 194 reg = <0x25000 0x1000>;
195 local-mac-address = [ 00 00 00 00 00 00 ]; 195 local-mac-address = [ 00 00 00 00 00 00 ];
196 interrupts = <35 8 36 8 37 8>; 196 interrupts = <35 0x8 36 0x8 37 0x8>;
197 phy-connection-type = "mii"; 197 phy-connection-type = "mii";
198 interrupt-parent = < &ipic >; 198 interrupt-parent = <&ipic>;
199 phy-handle = < &phy3 >; 199 phy-handle = <&phy3>;
200 }; 200 };
201 201
202 serial0: serial@4500 { 202 serial0: serial@4500 {
@@ -205,8 +205,8 @@
205 compatible = "ns16550"; 205 compatible = "ns16550";
206 reg = <0x4500 0x100>; 206 reg = <0x4500 0x100>;
207 clock-frequency = <0>; 207 clock-frequency = <0>;
208 interrupts = <9 8>; 208 interrupts = <9 0x8>;
209 interrupt-parent = < &ipic >; 209 interrupt-parent = <&ipic>;
210 }; 210 };
211 211
212 serial1: serial@4600 { 212 serial1: serial@4600 {
@@ -215,8 +215,8 @@
215 compatible = "ns16550"; 215 compatible = "ns16550";
216 reg = <0x4600 0x100>; 216 reg = <0x4600 0x100>;
217 clock-frequency = <0>; 217 clock-frequency = <0>;
218 interrupts = <10 8>; 218 interrupts = <10 0x8>;
219 interrupt-parent = < &ipic >; 219 interrupt-parent = <&ipic>;
220 }; 220 };
221 221
222 crypto@30000 { 222 crypto@30000 {
@@ -224,8 +224,8 @@
224 device_type = "crypto"; 224 device_type = "crypto";
225 compatible = "talitos"; 225 compatible = "talitos";
226 reg = <0x30000 0x10000>; 226 reg = <0x30000 0x10000>;
227 interrupts = <11 8>; 227 interrupts = <11 0x8>;
228 interrupt-parent = < &ipic >; 228 interrupt-parent = <&ipic>;
229 /* Rev. 3.0 geometry */ 229 /* Rev. 3.0 geometry */
230 num-channels = <4>; 230 num-channels = <4>;
231 channel-fifo-len = <24>; 231 channel-fifo-len = <24>;
@@ -254,23 +254,23 @@
254 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ 254 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
255 255
256 /* IDSEL AD14 IRQ6 inta */ 256 /* IDSEL AD14 IRQ6 inta */
257 0x7000 0 0 1 &ipic 22 8 257 0x7000 0x0 0x0 0x1 &ipic 22 0x8
258 258
259 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ 259 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
260 0x7800 0 0 1 &ipic 21 8 260 0x7800 0x0 0x0 0x1 &ipic 21 0x8
261 0x7800 0 0 2 &ipic 22 8 261 0x7800 0x0 0x0 0x2 &ipic 22 0x8
262 0x7800 0 0 4 &ipic 23 8 262 0x7800 0x0 0x0 0x4 &ipic 23 0x8
263 263
264 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ 264 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
265 0xE000 0 0 1 &ipic 23 8 265 0xE000 0x0 0x0 0x1 &ipic 23 0x8
266 0xE000 0 0 2 &ipic 21 8 266 0xE000 0x0 0x0 0x2 &ipic 21 0x8
267 0xE000 0 0 3 &ipic 22 8>; 267 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
268 interrupt-parent = < &ipic >; 268 interrupt-parent = <&ipic>;
269 interrupts = <66 8>; 269 interrupts = <66 0x8>;
270 bus-range = <0 0>; 270 bus-range = <0 0>;
271 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 271 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
272 0x42000000 0 0x80000000 0x80000000 0 0x10000000 272 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
273 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>; 273 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
274 clock-frequency = <66666666>; 274 clock-frequency = <66666666>;
275 #interrupt-cells = <1>; 275 #interrupt-cells = <1>;
276 #size-cells = <2>; 276 #size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index da9931b6c5c0..c270685bbde4 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -31,11 +31,11 @@
31 31
32 PowerPC,8379@0 { 32 PowerPC,8379@0 {
33 device_type = "cpu"; 33 device_type = "cpu";
34 reg = <0>; 34 reg = <0x0>;
35 d-cache-line-size = <0x20>; 35 d-cache-line-size = <32>;
36 i-cache-line-size = <0x20>; 36 i-cache-line-size = <32>;
37 d-cache-size = <0x8000>; // L1, 32K 37 d-cache-size = <32768>;
38 i-cache-size = <0x8000>; // L1, 32K 38 i-cache-size = <32768>;
39 timebase-frequency = <0>; 39 timebase-frequency = <0>;
40 bus-frequency = <0>; 40 bus-frequency = <0>;
41 clock-frequency = <0>; 41 clock-frequency = <0>;
@@ -66,8 +66,8 @@
66 cell-index = <0>; 66 cell-index = <0>;
67 compatible = "fsl-i2c"; 67 compatible = "fsl-i2c";
68 reg = <0x3000 0x100>; 68 reg = <0x3000 0x100>;
69 interrupts = <0xe 0x8>; 69 interrupts = <14 0x8>;
70 interrupt-parent = < &ipic >; 70 interrupt-parent = <&ipic>;
71 dfsrr; 71 dfsrr;
72 }; 72 };
73 73
@@ -77,8 +77,8 @@
77 cell-index = <1>; 77 cell-index = <1>;
78 compatible = "fsl-i2c"; 78 compatible = "fsl-i2c";
79 reg = <0x3100 0x100>; 79 reg = <0x3100 0x100>;
80 interrupts = <0xf 0x8>; 80 interrupts = <15 0x8>;
81 interrupt-parent = < &ipic >; 81 interrupt-parent = <&ipic>;
82 dfsrr; 82 dfsrr;
83 }; 83 };
84 84
@@ -86,8 +86,8 @@
86 cell-index = <0>; 86 cell-index = <0>;
87 compatible = "fsl,spi"; 87 compatible = "fsl,spi";
88 reg = <0x7000 0x1000>; 88 reg = <0x7000 0x1000>;
89 interrupts = <0x10 0x8>; 89 interrupts = <16 0x8>;
90 interrupt-parent = < &ipic >; 90 interrupt-parent = <&ipic>;
91 mode = "cpu"; 91 mode = "cpu";
92 }; 92 };
93 93
@@ -97,8 +97,8 @@
97 reg = <0x23000 0x1000>; 97 reg = <0x23000 0x1000>;
98 #address-cells = <1>; 98 #address-cells = <1>;
99 #size-cells = <0>; 99 #size-cells = <0>;
100 interrupt-parent = < &ipic >; 100 interrupt-parent = <&ipic>;
101 interrupts = <0x26 0x8>; 101 interrupts = <38 0x8>;
102 phy_type = "utmi_wide"; 102 phy_type = "utmi_wide";
103 }; 103 };
104 104
@@ -108,15 +108,15 @@
108 compatible = "fsl,gianfar-mdio"; 108 compatible = "fsl,gianfar-mdio";
109 reg = <0x24520 0x20>; 109 reg = <0x24520 0x20>;
110 phy2: ethernet-phy@2 { 110 phy2: ethernet-phy@2 {
111 interrupt-parent = < &ipic >; 111 interrupt-parent = <&ipic>;
112 interrupts = <0x11 0x8>; 112 interrupts = <17 0x8>;
113 reg = <2>; 113 reg = <0x2>;
114 device_type = "ethernet-phy"; 114 device_type = "ethernet-phy";
115 }; 115 };
116 phy3: ethernet-phy@3 { 116 phy3: ethernet-phy@3 {
117 interrupt-parent = < &ipic >; 117 interrupt-parent = <&ipic>;
118 interrupts = <0x12 0x8>; 118 interrupts = <18 0x8>;
119 reg = <3>; 119 reg = <0x3>;
120 device_type = "ethernet-phy"; 120 device_type = "ethernet-phy";
121 }; 121 };
122 }; 122 };
@@ -128,10 +128,10 @@
128 compatible = "gianfar"; 128 compatible = "gianfar";
129 reg = <0x24000 0x1000>; 129 reg = <0x24000 0x1000>;
130 local-mac-address = [ 00 00 00 00 00 00 ]; 130 local-mac-address = [ 00 00 00 00 00 00 ];
131 interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>; 131 interrupts = <32 0x8 33 0x8 34 0x8>;
132 phy-connection-type = "mii"; 132 phy-connection-type = "mii";
133 interrupt-parent = < &ipic >; 133 interrupt-parent = <&ipic>;
134 phy-handle = < &phy2 >; 134 phy-handle = <&phy2>;
135 }; 135 };
136 136
137 enet1: ethernet@25000 { 137 enet1: ethernet@25000 {
@@ -141,10 +141,10 @@
141 compatible = "gianfar"; 141 compatible = "gianfar";
142 reg = <0x25000 0x1000>; 142 reg = <0x25000 0x1000>;
143 local-mac-address = [ 00 00 00 00 00 00 ]; 143 local-mac-address = [ 00 00 00 00 00 00 ];
144 interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>; 144 interrupts = <35 0x8 36 0x8 37 0x8>;
145 phy-connection-type = "mii"; 145 phy-connection-type = "mii";
146 interrupt-parent = < &ipic >; 146 interrupt-parent = <&ipic>;
147 phy-handle = < &phy3 >; 147 phy-handle = <&phy3>;
148 }; 148 };
149 149
150 serial0: serial@4500 { 150 serial0: serial@4500 {
@@ -153,8 +153,8 @@
153 compatible = "ns16550"; 153 compatible = "ns16550";
154 reg = <0x4500 0x100>; 154 reg = <0x4500 0x100>;
155 clock-frequency = <0>; 155 clock-frequency = <0>;
156 interrupts = <0x9 0x8>; 156 interrupts = <9 0x8>;
157 interrupt-parent = < &ipic >; 157 interrupt-parent = <&ipic>;
158 }; 158 };
159 159
160 serial1: serial@4600 { 160 serial1: serial@4600 {
@@ -163,19 +163,19 @@
163 compatible = "ns16550"; 163 compatible = "ns16550";
164 reg = <0x4600 0x100>; 164 reg = <0x4600 0x100>;
165 clock-frequency = <0>; 165 clock-frequency = <0>;
166 interrupts = <0xa 0x8>; 166 interrupts = <10 0x8>;
167 interrupt-parent = < &ipic >; 167 interrupt-parent = <&ipic>;
168 }; 168 };
169 169
170 crypto@30000 { 170 crypto@30000 {
171 model = "SEC3"; 171 model = "SEC3";
172 compatible = "talitos"; 172 compatible = "talitos";
173 reg = <0x30000 0x10000>; 173 reg = <0x30000 0x10000>;
174 interrupts = <0xb 0x8>; 174 interrupts = <11 0x8>;
175 interrupt-parent = < &ipic >; 175 interrupt-parent = <&ipic>;
176 /* Rev. 3.0 geometry */ 176 /* Rev. 3.0 geometry */
177 num-channels = <4>; 177 num-channels = <4>;
178 channel-fifo-len = <0x18>; 178 channel-fifo-len = <24>;
179 exec-units-mask = <0x000001fe>; 179 exec-units-mask = <0x000001fe>;
180 descriptor-types-mask = <0x03ab0ebf>; 180 descriptor-types-mask = <0x03ab0ebf>;
181 }; 181 };
@@ -184,36 +184,36 @@
184 model = "eSDHC"; 184 model = "eSDHC";
185 compatible = "fsl,esdhc"; 185 compatible = "fsl,esdhc";
186 reg = <0x2e000 0x1000>; 186 reg = <0x2e000 0x1000>;
187 interrupts = <0x2a 0x8>; 187 interrupts = <42 0x8>;
188 interrupt-parent = < &ipic >; 188 interrupt-parent = <&ipic>;
189 }; 189 };
190 190
191 sata@18000 { 191 sata@18000 {
192 compatible = "fsl,mpc8379-sata"; 192 compatible = "fsl,mpc8379-sata";
193 reg = <0x18000 0x1000>; 193 reg = <0x18000 0x1000>;
194 interrupts = <0x2c 0x8>; 194 interrupts = <44 0x8>;
195 interrupt-parent = < &ipic >; 195 interrupt-parent = <&ipic>;
196 }; 196 };
197 197
198 sata@19000 { 198 sata@19000 {
199 compatible = "fsl,mpc8379-sata"; 199 compatible = "fsl,mpc8379-sata";
200 reg = <0x19000 0x1000>; 200 reg = <0x19000 0x1000>;
201 interrupts = <0x2d 0x8>; 201 interrupts = <45 0x8>;
202 interrupt-parent = < &ipic >; 202 interrupt-parent = <&ipic>;
203 }; 203 };
204 204
205 sata@1a000 { 205 sata@1a000 {
206 compatible = "fsl,mpc8379-sata"; 206 compatible = "fsl,mpc8379-sata";
207 reg = <0x1a000 0x1000>; 207 reg = <0x1a000 0x1000>;
208 interrupts = <0x2e 0x8>; 208 interrupts = <46 0x8>;
209 interrupt-parent = < &ipic >; 209 interrupt-parent = <&ipic>;
210 }; 210 };
211 211
212 sata@1b000 { 212 sata@1b000 {
213 compatible = "fsl,mpc8379-sata"; 213 compatible = "fsl,mpc8379-sata";
214 reg = <0x1b000 0x1000>; 214 reg = <0x1b000 0x1000>;
215 interrupts = <0x2f 0x8>; 215 interrupts = <47 0x8>;
216 interrupt-parent = < &ipic >; 216 interrupt-parent = <&ipic>;
217 }; 217 };
218 218
219 /* IPIC 219 /* IPIC
@@ -237,49 +237,49 @@
237 interrupt-map = < 237 interrupt-map = <
238 238
239 /* IDSEL 0x11 */ 239 /* IDSEL 0x11 */
240 0x8800 0x0 0x0 0x1 &ipic 0x14 0x8 240 0x8800 0x0 0x0 0x1 &ipic 20 0x8
241 0x8800 0x0 0x0 0x2 &ipic 0x15 0x8 241 0x8800 0x0 0x0 0x2 &ipic 21 0x8
242 0x8800 0x0 0x0 0x3 &ipic 0x16 0x8 242 0x8800 0x0 0x0 0x3 &ipic 22 0x8
243 0x8800 0x0 0x0 0x4 &ipic 0x17 0x8 243 0x8800 0x0 0x0 0x4 &ipic 23 0x8
244 244
245 /* IDSEL 0x12 */ 245 /* IDSEL 0x12 */
246 0x9000 0x0 0x0 0x1 &ipic 0x16 0x8 246 0x9000 0x0 0x0 0x1 &ipic 22 0x8
247 0x9000 0x0 0x0 0x2 &ipic 0x17 0x8 247 0x9000 0x0 0x0 0x2 &ipic 23 0x8
248 0x9000 0x0 0x0 0x3 &ipic 0x14 0x8 248 0x9000 0x0 0x0 0x3 &ipic 20 0x8
249 0x9000 0x0 0x0 0x4 &ipic 0x15 0x8 249 0x9000 0x0 0x0 0x4 &ipic 21 0x8
250 250
251 /* IDSEL 0x13 */ 251 /* IDSEL 0x13 */
252 0x9800 0x0 0x0 0x1 &ipic 0x17 0x8 252 0x9800 0x0 0x0 0x1 &ipic 23 0x8
253 0x9800 0x0 0x0 0x2 &ipic 0x14 0x8 253 0x9800 0x0 0x0 0x2 &ipic 20 0x8
254 0x9800 0x0 0x0 0x3 &ipic 0x15 0x8 254 0x9800 0x0 0x0 0x3 &ipic 21 0x8
255 0x9800 0x0 0x0 0x4 &ipic 0x16 0x8 255 0x9800 0x0 0x0 0x4 &ipic 22 0x8
256 256
257 /* IDSEL 0x15 */ 257 /* IDSEL 0x15 */
258 0xa800 0x0 0x0 0x1 &ipic 0x14 0x8 258 0xa800 0x0 0x0 0x1 &ipic 20 0x8
259 0xa800 0x0 0x0 0x2 &ipic 0x15 0x8 259 0xa800 0x0 0x0 0x2 &ipic 21 0x8
260 0xa800 0x0 0x0 0x3 &ipic 0x16 0x8 260 0xa800 0x0 0x0 0x3 &ipic 22 0x8
261 0xa800 0x0 0x0 0x4 &ipic 0x17 0x8 261 0xa800 0x0 0x0 0x4 &ipic 23 0x8
262 262
263 /* IDSEL 0x16 */ 263 /* IDSEL 0x16 */
264 0xb000 0x0 0x0 0x1 &ipic 0x17 0x8 264 0xb000 0x0 0x0 0x1 &ipic 23 0x8
265 0xb000 0x0 0x0 0x2 &ipic 0x14 0x8 265 0xb000 0x0 0x0 0x2 &ipic 20 0x8
266 0xb000 0x0 0x0 0x3 &ipic 0x15 0x8 266 0xb000 0x0 0x0 0x3 &ipic 21 0x8
267 0xb000 0x0 0x0 0x4 &ipic 0x16 0x8 267 0xb000 0x0 0x0 0x4 &ipic 22 0x8
268 268
269 /* IDSEL 0x17 */ 269 /* IDSEL 0x17 */
270 0xb800 0x0 0x0 0x1 &ipic 0x16 0x8 270 0xb800 0x0 0x0 0x1 &ipic 22 0x8
271 0xb800 0x0 0x0 0x2 &ipic 0x17 0x8 271 0xb800 0x0 0x0 0x2 &ipic 23 0x8
272 0xb800 0x0 0x0 0x3 &ipic 0x14 0x8 272 0xb800 0x0 0x0 0x3 &ipic 20 0x8
273 0xb800 0x0 0x0 0x4 &ipic 0x15 0x8 273 0xb800 0x0 0x0 0x4 &ipic 21 0x8
274 274
275 /* IDSEL 0x18 */ 275 /* IDSEL 0x18 */
276 0xc000 0x0 0x0 0x1 &ipic 0x15 0x8 276 0xc000 0x0 0x0 0x1 &ipic 21 0x8
277 0xc000 0x0 0x0 0x2 &ipic 0x16 0x8 277 0xc000 0x0 0x0 0x2 &ipic 22 0x8
278 0xc000 0x0 0x0 0x3 &ipic 0x17 0x8 278 0xc000 0x0 0x0 0x3 &ipic 23 0x8
279 0xc000 0x0 0x0 0x4 &ipic 0x14 0x8>; 279 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
280 interrupt-parent = < &ipic >; 280 interrupt-parent = <&ipic>;
281 interrupts = <0x42 0x8>; 281 interrupts = <66 0x8>;
282 bus-range = <0 0>; 282 bus-range = <0x0 0x0>;
283 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 283 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
284 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 284 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
285 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; 285 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 255d2e4fab50..0dda2fc558f8 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -30,7 +30,7 @@
30 30
31 PowerPC,8379@0 { 31 PowerPC,8379@0 {
32 device_type = "cpu"; 32 device_type = "cpu";
33 reg = <0>; 33 reg = <0x0>;
34 d-cache-line-size = <32>; 34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>; 35 i-cache-line-size = <32>;
36 d-cache-size = <32768>; 36 d-cache-size = <32768>;
@@ -51,22 +51,22 @@
51 #size-cells = <1>; 51 #size-cells = <1>;
52 compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus"; 52 compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
53 reg = <0xe0005000 0x1000>; 53 reg = <0xe0005000 0x1000>;
54 interrupts = <77 8>; 54 interrupts = <77 0x8>;
55 interrupt-parent = <&ipic>; 55 interrupt-parent = <&ipic>;
56 56
57 // CS0 and CS1 are swapped when 57 // CS0 and CS1 are swapped when
58 // booting from nand, but the 58 // booting from nand, but the
59 // addresses are the same. 59 // addresses are the same.
60 ranges = <0 0 0xfe000000 0x00800000 60 ranges = <0x0 0x0 0xfe000000 0x00800000
61 1 0 0xe0600000 0x00008000 61 0x1 0x0 0xe0600000 0x00008000
62 2 0 0xf0000000 0x00020000 62 0x2 0x0 0xf0000000 0x00020000
63 3 0 0xfa000000 0x00008000>; 63 0x3 0x0 0xfa000000 0x00008000>;
64 64
65 flash@0,0 { 65 flash@0,0 {
66 #address-cells = <1>; 66 #address-cells = <1>;
67 #size-cells = <1>; 67 #size-cells = <1>;
68 compatible = "cfi-flash"; 68 compatible = "cfi-flash";
69 reg = <0 0 0x800000>; 69 reg = <0x0 0x0 0x800000>;
70 bank-width = <2>; 70 bank-width = <2>;
71 device-width = <1>; 71 device-width = <1>;
72 }; 72 };
@@ -76,7 +76,7 @@
76 #size-cells = <1>; 76 #size-cells = <1>;
77 compatible = "fsl,mpc8379-fcm-nand", 77 compatible = "fsl,mpc8379-fcm-nand",
78 "fsl,elbc-fcm-nand"; 78 "fsl,elbc-fcm-nand";
79 reg = <1 0 0x8000>; 79 reg = <0x1 0x0 0x8000>;
80 80
81 u-boot@0 { 81 u-boot@0 {
82 reg = <0x0 0x100000>; 82 reg = <0x0 0x100000>;
@@ -97,7 +97,7 @@
97 #size-cells = <1>; 97 #size-cells = <1>;
98 device_type = "soc"; 98 device_type = "soc";
99 compatible = "simple-bus"; 99 compatible = "simple-bus";
100 ranges = <0 0xe0000000 0x00100000>; 100 ranges = <0x0 0xe0000000 0x00100000>;
101 reg = <0xe0000000 0x00000200>; 101 reg = <0xe0000000 0x00000200>;
102 bus-frequency = <0>; 102 bus-frequency = <0>;
103 103
@@ -113,8 +113,8 @@
113 cell-index = <0>; 113 cell-index = <0>;
114 compatible = "fsl-i2c"; 114 compatible = "fsl-i2c";
115 reg = <0x3000 0x100>; 115 reg = <0x3000 0x100>;
116 interrupts = <14 8>; 116 interrupts = <14 0x8>;
117 interrupt-parent = < &ipic >; 117 interrupt-parent = <&ipic>;
118 dfsrr; 118 dfsrr;
119 rtc@68 { 119 rtc@68 {
120 device_type = "rtc"; 120 device_type = "rtc";
@@ -129,8 +129,8 @@
129 cell-index = <1>; 129 cell-index = <1>;
130 compatible = "fsl-i2c"; 130 compatible = "fsl-i2c";
131 reg = <0x3100 0x100>; 131 reg = <0x3100 0x100>;
132 interrupts = <15 8>; 132 interrupts = <15 0x8>;
133 interrupt-parent = < &ipic >; 133 interrupt-parent = <&ipic>;
134 dfsrr; 134 dfsrr;
135 }; 135 };
136 136
@@ -138,8 +138,8 @@
138 cell-index = <0>; 138 cell-index = <0>;
139 compatible = "fsl,spi"; 139 compatible = "fsl,spi";
140 reg = <0x7000 0x1000>; 140 reg = <0x7000 0x1000>;
141 interrupts = <16 8>; 141 interrupts = <16 0x8>;
142 interrupt-parent = < &ipic >; 142 interrupt-parent = <&ipic>;
143 mode = "cpu"; 143 mode = "cpu";
144 }; 144 };
145 145
@@ -149,8 +149,8 @@
149 reg = <0x23000 0x1000>; 149 reg = <0x23000 0x1000>;
150 #address-cells = <1>; 150 #address-cells = <1>;
151 #size-cells = <0>; 151 #size-cells = <0>;
152 interrupt-parent = < &ipic >; 152 interrupt-parent = <&ipic>;
153 interrupts = <38 8>; 153 interrupts = <38 0x8>;
154 phy_type = "utmi"; 154 phy_type = "utmi";
155 }; 155 };
156 156
@@ -160,15 +160,15 @@
160 compatible = "fsl,gianfar-mdio"; 160 compatible = "fsl,gianfar-mdio";
161 reg = <0x24520 0x20>; 161 reg = <0x24520 0x20>;
162 phy2: ethernet-phy@2 { 162 phy2: ethernet-phy@2 {
163 interrupt-parent = < &ipic >; 163 interrupt-parent = <&ipic>;
164 interrupts = <17 8>; 164 interrupts = <17 0x8>;
165 reg = <2>; 165 reg = <0x2>;
166 device_type = "ethernet-phy"; 166 device_type = "ethernet-phy";
167 }; 167 };
168 phy3: ethernet-phy@3 { 168 phy3: ethernet-phy@3 {
169 interrupt-parent = < &ipic >; 169 interrupt-parent = <&ipic>;
170 interrupts = <18 8>; 170 interrupts = <18 0x8>;
171 reg = <3>; 171 reg = <0x3>;
172 device_type = "ethernet-phy"; 172 device_type = "ethernet-phy";
173 }; 173 };
174 }; 174 };
@@ -180,10 +180,10 @@
180 compatible = "gianfar"; 180 compatible = "gianfar";
181 reg = <0x24000 0x1000>; 181 reg = <0x24000 0x1000>;
182 local-mac-address = [ 00 00 00 00 00 00 ]; 182 local-mac-address = [ 00 00 00 00 00 00 ];
183 interrupts = <32 8 33 8 34 8>; 183 interrupts = <32 0x8 33 0x8 34 0x8>;
184 phy-connection-type = "mii"; 184 phy-connection-type = "mii";
185 interrupt-parent = < &ipic >; 185 interrupt-parent = <&ipic>;
186 phy-handle = < &phy2 >; 186 phy-handle = <&phy2>;
187 }; 187 };
188 188
189 enet1: ethernet@25000 { 189 enet1: ethernet@25000 {
@@ -193,10 +193,10 @@
193 compatible = "gianfar"; 193 compatible = "gianfar";
194 reg = <0x25000 0x1000>; 194 reg = <0x25000 0x1000>;
195 local-mac-address = [ 00 00 00 00 00 00 ]; 195 local-mac-address = [ 00 00 00 00 00 00 ];
196 interrupts = <35 8 36 8 37 8>; 196 interrupts = <35 0x8 36 0x8 37 0x8>;
197 phy-connection-type = "mii"; 197 phy-connection-type = "mii";
198 interrupt-parent = < &ipic >; 198 interrupt-parent = <&ipic>;
199 phy-handle = < &phy3 >; 199 phy-handle = <&phy3>;
200 }; 200 };
201 201
202 serial0: serial@4500 { 202 serial0: serial@4500 {
@@ -205,8 +205,8 @@
205 compatible = "ns16550"; 205 compatible = "ns16550";
206 reg = <0x4500 0x100>; 206 reg = <0x4500 0x100>;
207 clock-frequency = <0>; 207 clock-frequency = <0>;
208 interrupts = <9 8>; 208 interrupts = <9 0x8>;
209 interrupt-parent = < &ipic >; 209 interrupt-parent = <&ipic>;
210 }; 210 };
211 211
212 serial1: serial@4600 { 212 serial1: serial@4600 {
@@ -215,8 +215,8 @@
215 compatible = "ns16550"; 215 compatible = "ns16550";
216 reg = <0x4600 0x100>; 216 reg = <0x4600 0x100>;
217 clock-frequency = <0>; 217 clock-frequency = <0>;
218 interrupts = <10 8>; 218 interrupts = <10 0x8>;
219 interrupt-parent = < &ipic >; 219 interrupt-parent = <&ipic>;
220 }; 220 };
221 221
222 crypto@30000 { 222 crypto@30000 {
@@ -224,8 +224,8 @@
224 device_type = "crypto"; 224 device_type = "crypto";
225 compatible = "talitos"; 225 compatible = "talitos";
226 reg = <0x30000 0x10000>; 226 reg = <0x30000 0x10000>;
227 interrupts = <11 8>; 227 interrupts = <11 0x8>;
228 interrupt-parent = < &ipic >; 228 interrupt-parent = <&ipic>;
229 /* Rev. 3.0 geometry */ 229 /* Rev. 3.0 geometry */
230 num-channels = <4>; 230 num-channels = <4>;
231 channel-fifo-len = <24>; 231 channel-fifo-len = <24>;
@@ -236,29 +236,29 @@
236 sata@18000 { 236 sata@18000 {
237 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 237 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
238 reg = <0x18000 0x1000>; 238 reg = <0x18000 0x1000>;
239 interrupts = <44 8>; 239 interrupts = <44 0x8>;
240 interrupt-parent = < &ipic >; 240 interrupt-parent = <&ipic>;
241 }; 241 };
242 242
243 sata@19000 { 243 sata@19000 {
244 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 244 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
245 reg = <0x19000 0x1000>; 245 reg = <0x19000 0x1000>;
246 interrupts = <45 8>; 246 interrupts = <45 0x8>;
247 interrupt-parent = < &ipic >; 247 interrupt-parent = <&ipic>;
248 }; 248 };
249 249
250 sata@1a000 { 250 sata@1a000 {
251 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 251 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
252 reg = <0x1a000 0x1000>; 252 reg = <0x1a000 0x1000>;
253 interrupts = <46 8>; 253 interrupts = <46 0x8>;
254 interrupt-parent = < &ipic >; 254 interrupt-parent = <&ipic>;
255 }; 255 };
256 256
257 sata@1b000 { 257 sata@1b000 {
258 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 258 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
259 reg = <0x1b000 0x1000>; 259 reg = <0x1b000 0x1000>;
260 interrupts = <47 8>; 260 interrupts = <47 0x8>;
261 interrupt-parent = < &ipic >; 261 interrupt-parent = <&ipic>;
262 }; 262 };
263 263
264 /* IPIC 264 /* IPIC
@@ -282,23 +282,23 @@
282 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ 282 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
283 283
284 /* IDSEL AD14 IRQ6 inta */ 284 /* IDSEL AD14 IRQ6 inta */
285 0x7000 0 0 1 &ipic 22 8 285 0x7000 0x0 0x0 0x1 &ipic 22 0x8
286 286
287 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */ 287 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
288 0x7800 0 0 1 &ipic 21 8 288 0x7800 0x0 0x0 0x1 &ipic 21 0x8
289 0x7800 0 0 2 &ipic 22 8 289 0x7800 0x0 0x0 0x2 &ipic 22 0x8
290 0x7800 0 0 4 &ipic 23 8 290 0x7800 0x0 0x0 0x4 &ipic 23 0x8
291 291
292 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/ 292 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
293 0xE000 0 0 1 &ipic 23 8 293 0xE000 0x0 0x0 0x1 &ipic 23 0x8
294 0xE000 0 0 2 &ipic 21 8 294 0xE000 0x0 0x0 0x2 &ipic 21 0x8
295 0xE000 0 0 3 &ipic 22 8>; 295 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
296 interrupt-parent = < &ipic >; 296 interrupt-parent = <&ipic>;
297 interrupts = <66 8>; 297 interrupts = <66 0x8>;
298 bus-range = <0 0>; 298 bus-range = <0x0 0x0>;
299 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 299 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
300 0x42000000 0 0x80000000 0x80000000 0 0x10000000 300 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
301 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>; 301 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
302 clock-frequency = <66666666>; 302 clock-frequency = <66666666>;
303 #interrupt-cells = <1>; 303 #interrupt-cells = <1>;
304 #size-cells = <2>; 304 #size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index 0934f54b2b43..3839d4b7d6a7 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -35,11 +35,11 @@
35 35
36 PowerPC,8349@0 { 36 PowerPC,8349@0 {
37 device_type = "cpu"; 37 device_type = "cpu";
38 reg = <0>; 38 reg = <0x0>;
39 d-cache-line-size = <0x20>; // 32 bytes 39 d-cache-line-size = <32>;
40 i-cache-line-size = <0x20>; // 32 bytes 40 i-cache-line-size = <32>;
41 d-cache-size = <0x8000>; // L1, 32K 41 d-cache-size = <32768>;
42 i-cache-size = <0x8000>; // L1, 32K 42 i-cache-size = <32768>;
43 timebase-frequency = <0>; // from bootloader 43 timebase-frequency = <0>; // from bootloader
44 bus-frequency = <0>; // from bootloader 44 bus-frequency = <0>; // from bootloader
45 clock-frequency = <0>; // from bootloader 45 clock-frequency = <0>; // from bootloader
@@ -70,7 +70,7 @@
70 cell-index = <0>; 70 cell-index = <0>;
71 compatible = "fsl-i2c"; 71 compatible = "fsl-i2c";
72 reg = <0x3000 0x100>; 72 reg = <0x3000 0x100>;
73 interrupts = <0xe 0x8>; 73 interrupts = <14 0x8>;
74 interrupt-parent = <&ipic>; 74 interrupt-parent = <&ipic>;
75 dfsrr; 75 dfsrr;
76 }; 76 };
@@ -81,7 +81,7 @@
81 cell-index = <1>; 81 cell-index = <1>;
82 compatible = "fsl-i2c"; 82 compatible = "fsl-i2c";
83 reg = <0x3100 0x100>; 83 reg = <0x3100 0x100>;
84 interrupts = <0xf 0x8>; 84 interrupts = <15 0x8>;
85 interrupt-parent = <&ipic>; 85 interrupt-parent = <&ipic>;
86 dfsrr; 86 dfsrr;
87 }; 87 };
@@ -90,7 +90,7 @@
90 cell-index = <0>; 90 cell-index = <0>;
91 compatible = "fsl,spi"; 91 compatible = "fsl,spi";
92 reg = <0x7000 0x1000>; 92 reg = <0x7000 0x1000>;
93 interrupts = <0x10 0x8>; 93 interrupts = <16 0x8>;
94 interrupt-parent = <&ipic>; 94 interrupt-parent = <&ipic>;
95 mode = "cpu"; 95 mode = "cpu";
96 }; 96 };
@@ -103,7 +103,7 @@
103 #address-cells = <1>; 103 #address-cells = <1>;
104 #size-cells = <0>; 104 #size-cells = <0>;
105 interrupt-parent = <&ipic>; 105 interrupt-parent = <&ipic>;
106 interrupts = <0x27 0x8>; 106 interrupts = <39 0x8>;
107 phy_type = "ulpi"; 107 phy_type = "ulpi";
108 port1; 108 port1;
109 }; 109 };
@@ -115,7 +115,7 @@
115 #address-cells = <1>; 115 #address-cells = <1>;
116 #size-cells = <0>; 116 #size-cells = <0>;
117 interrupt-parent = <&ipic>; 117 interrupt-parent = <&ipic>;
118 interrupts = <0x26 0x8>; 118 interrupts = <38 0x8>;
119 dr_mode = "otg"; 119 dr_mode = "otg";
120 phy_type = "ulpi"; 120 phy_type = "ulpi";
121 }; 121 };
@@ -128,13 +128,13 @@
128 128
129 phy0: ethernet-phy@19 { 129 phy0: ethernet-phy@19 {
130 interrupt-parent = <&ipic>; 130 interrupt-parent = <&ipic>;
131 interrupts = <0x14 0x8>; 131 interrupts = <20 0x8>;
132 reg = <0x19>; 132 reg = <0x19>;
133 device_type = "ethernet-phy"; 133 device_type = "ethernet-phy";
134 }; 134 };
135 phy1: ethernet-phy@1a { 135 phy1: ethernet-phy@1a {
136 interrupt-parent = <&ipic>; 136 interrupt-parent = <&ipic>;
137 interrupts = <0x15 0x8>; 137 interrupts = <21 0x8>;
138 reg = <0x1a>; 138 reg = <0x1a>;
139 device_type = "ethernet-phy"; 139 device_type = "ethernet-phy";
140 }; 140 };
@@ -147,7 +147,7 @@
147 compatible = "gianfar"; 147 compatible = "gianfar";
148 reg = <0x24000 0x1000>; 148 reg = <0x24000 0x1000>;
149 local-mac-address = [ 00 00 00 00 00 00 ]; 149 local-mac-address = [ 00 00 00 00 00 00 ];
150 interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>; 150 interrupts = <32 0x8 33 0x8 34 0x8>;
151 interrupt-parent = <&ipic>; 151 interrupt-parent = <&ipic>;
152 phy-handle = <&phy0>; 152 phy-handle = <&phy0>;
153 linux,network-index = <0>; 153 linux,network-index = <0>;
@@ -160,7 +160,7 @@
160 compatible = "gianfar"; 160 compatible = "gianfar";
161 reg = <0x25000 0x1000>; 161 reg = <0x25000 0x1000>;
162 local-mac-address = [ 00 00 00 00 00 00 ]; 162 local-mac-address = [ 00 00 00 00 00 00 ];
163 interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>; 163 interrupts = <35 0x8 36 0x8 37 0x8>;
164 interrupt-parent = <&ipic>; 164 interrupt-parent = <&ipic>;
165 phy-handle = <&phy1>; 165 phy-handle = <&phy1>;
166 linux,network-index = <1>; 166 linux,network-index = <1>;
@@ -172,7 +172,7 @@
172 compatible = "ns16550"; 172 compatible = "ns16550";
173 reg = <0x4500 0x100>; 173 reg = <0x4500 0x100>;
174 clock-frequency = <0>; 174 clock-frequency = <0>;
175 interrupts = <0x9 0x8>; 175 interrupts = <9 0x8>;
176 interrupt-parent = <&ipic>; 176 interrupt-parent = <&ipic>;
177 }; 177 };
178 178
@@ -182,7 +182,7 @@
182 compatible = "ns16550"; 182 compatible = "ns16550";
183 reg = <0x4600 0x100>; 183 reg = <0x4600 0x100>;
184 clock-frequency = <0>; 184 clock-frequency = <0>;
185 interrupts = <0xa 0x8>; 185 interrupts = <10 0x8>;
186 interrupt-parent = <&ipic>; 186 interrupt-parent = <&ipic>;
187 }; 187 };
188 188
@@ -191,10 +191,10 @@
191 model = "SEC2"; 191 model = "SEC2";
192 compatible = "talitos"; 192 compatible = "talitos";
193 reg = <0x30000 0x10000>; 193 reg = <0x30000 0x10000>;
194 interrupts = <0xb 0x8>; 194 interrupts = <11 0x8>;
195 interrupt-parent = <&ipic>; 195 interrupt-parent = <&ipic>;
196 num-channels = <4>; 196 num-channels = <4>;
197 channel-fifo-len = <0x18>; 197 channel-fifo-len = <24>;
198 exec-units-mask = <0x0000007e>; 198 exec-units-mask = <0x0000007e>;
199 /* desc mask is for rev2.0, 199 /* desc mask is for rev2.0,
200 * we need runtime fixup for >2.0 */ 200 * we need runtime fixup for >2.0 */
@@ -222,10 +222,10 @@
222 interrupt-map = < 222 interrupt-map = <
223 223
224 /* IDSEL 0x11 */ 224 /* IDSEL 0x11 */
225 0x8800 0x0 0x0 0x1 &ipic 0x14 0x8 225 0x8800 0x0 0x0 0x1 &ipic 20 0x8
226 0x8800 0x0 0x0 0x2 &ipic 0x15 0x8 226 0x8800 0x0 0x0 0x2 &ipic 21 0x8
227 0x8800 0x0 0x0 0x3 &ipic 0x16 0x8 227 0x8800 0x0 0x0 0x3 &ipic 22 0x8
228 0x8800 0x0 0x0 0x4 &ipic 0x17 0x8>; 228 0x8800 0x0 0x0 0x4 &ipic 23 0x8>;
229 229
230 interrupt-parent = <&ipic>; 230 interrupt-parent = <&ipic>;
231 interrupts = <0x42 0x8>; 231 interrupts = <0x42 0x8>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-28 03:24:05 -0400