sh: pci: Support secondary FPGA-driven PCIe clocks on SDK7786.

The SDK7786 FPGA has secondary control over the PCIe clocks, specifically
relating to the slots and oscillator. This ties the FPGA clocks in to the
clock framework and balances the refcounting similar to how the primary
on-chip clocks are managed. While the on-chip clocks are per-port, the
FPGA clock enable/disable is global for the entire block.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

4 files changed, 75 insertions, 5 deletions

diff --git a/arch/sh/boards/mach-sdk7786/setup.c b/arch/sh/boards/mach-sdk7786/setup.c
index 2ec1ea5cf8ef..7e0c4e3878e0 100644
--- a/arch/sh/boards/mach-sdk7786/setup.c
+++ b/arch/sh/boards/mach-sdk7786/setup.c
@@ -20,6 +20,8 @@
 #include <asm/machvec.h>
 #include <asm/heartbeat.h>
 #include <asm/sizes.h>
+#include <asm/clock.h>
+#include <asm/clkdev.h>
 #include <asm/reboot.h>
 #include <asm/smp-ops.h>
 
@@ -140,6 +142,45 @@ static int sdk7786_mode_pins(void)
         return fpga_read_reg(MODSWR);
 }
 
+/*
+ * FPGA-driven PCIe clocks
+ *
+ * Historically these include the oscillator, clock B (slots 2/3/4) and
+ * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove
+ * everything under a single PCIe clocks enable bit that happens to map
+ * to the same bit position as the oscillator bit for earlier FPGA
+ * versions.
+ *
+ * Given that the legacy clocks have the side-effect of shutting the CPU
+ * off through the FPGA along with the PCI slots, we simply leave them in
+ * their initial state and don't bother registering them with the clock
+ * framework.
+ */
+static int sdk7786_pcie_clk_enable(struct clk *clk)
+{
+        fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR);
+        return 0;
+}
+
+static void sdk7786_pcie_clk_disable(struct clk *clk)
+{
+        fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
+}
+
+static struct clk_ops sdk7786_pcie_clk_ops = {
+        .enable         = sdk7786_pcie_clk_enable,
+        .disable        = sdk7786_pcie_clk_disable,
+};
+
+static struct clk sdk7786_pcie_clk = {
+        .ops            = &sdk7786_pcie_clk_ops,
+};
+
+static struct clk_lookup sdk7786_pcie_cl = {
+        .con_id         = "pcie_plat_clk",
+        .clk            = &sdk7786_pcie_clk,
+};
+
 static int sdk7786_clk_init(void)
 {
         struct clk *clk;
@@ -158,7 +199,18 @@ static int sdk7786_clk_init(void)
         ret = clk_set_rate(clk, 33333333);
         clk_put(clk);
 
-        return ret;
+        /*
+         * Setup the FPGA clocks.
+         */
+        ret = clk_register(&sdk7786_pcie_clk);
+        if (unlikely(ret)) {
+                pr_err("FPGA clock registration failed\n");
+                return ret;
+        }
+
+        clkdev_add(&sdk7786_pcie_cl);
+
+        return 0;
 }
 
 static void sdk7786_restart(char *cmd)
diff --git a/arch/sh/drivers/pci/fixups-sdk7786.c b/arch/sh/drivers/pci/fixups-sdk7786.c
index 058a65a1aa20..0e18ee332553 100644
--- a/arch/sh/drivers/pci/fixups-sdk7786.c
+++ b/arch/sh/drivers/pci/fixups-sdk7786.c
@@ -10,7 +10,6 @@
 #define pr_fmt(fmt) "PCI: " fmt
 
 #include <linux/init.h>
-#include <linux/clk.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <mach/fpga.h>
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index 8ec4af197388..ae0b2c9b70a0 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -17,7 +17,6 @@
 #include <linux/sh_clk.h>
 #include "pcie-sh7786.h"
 #include <asm/sizes.h>
-#include <asm/clock.h>
 
 struct sh7786_pcie_port {
         struct pci_channel      *hose;
@@ -510,6 +509,7 @@ static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
 
 static int __init sh7786_pcie_init(void)
 {
+        struct clk *platclk;
         int ret = 0, i;
 
         printk(KERN_NOTICE "PCI: Starting initialization.\n");
@@ -527,6 +527,22 @@ static int __init sh7786_pcie_init(void)
         if (unlikely(!sh7786_pcie_ports))
                 return -ENOMEM;
 
+        /*
+         * Fetch any optional platform clock associated with this block.
+         *
+         * This is a rather nasty hack for boards with spec-mocking FPGAs
+         * that have a secondary set of clocks outside of the on-chip
+         * ones that need to be accounted for before there is any chance
+         * of touching the existing MSTP bits or CPG clocks.
+         */
+        platclk = clk_get(NULL, "pcie_plat_clk");
+        if (IS_ERR(platclk)) {
+                /* Sane hardware should probably get a WARN_ON.. */
+                platclk = NULL;
+        }
+
+        clk_enable(platclk);
+
         printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
 
         for (i = 0; i < nr_ports; i++) {
@@ -539,8 +555,11 @@ static int __init sh7786_pcie_init(void)
                 ret |= sh7786_pcie_hwops->port_init_hw(port);
         }
 
-        if (unlikely(ret))
+        if (unlikely(ret)) {
+                clk_disable(platclk);
+                clk_put(platclk);
                 return ret;
+        }
 
         return 0;
 }
diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h
index 8cc784147b96..b7d93699b679 100644
--- a/arch/sh/include/mach-sdk7786/mach/fpga.h
+++ b/arch/sh/include/mach-sdk7786/mach/fpga.h
@@ -39,7 +39,7 @@
 #define  PCIECR_PRST3           BIT(11) /* slot 3 card present */
 #define  PCIECR_PRST2           BIT(10) /* slot 2 card present */
 #define  PCIECR_PRST1           BIT(9)  /* slot 1 card present */
-#define  PCIECR_CLKEN           BIT(4)
+#define  PCIECR_CLKEN           BIT(4)  /* oscillator enable */
 
 #define FAER            0x150
 #define USRGPIR         0x160