diff options
author | Chuanxiao Dong <chuanxiao.dong@intel.com> | 2010-07-26 23:32:21 -0400 |
---|---|---|
committer | David Woodhouse <David.Woodhouse@intel.com> | 2010-08-05 11:31:55 -0400 |
commit | a99d17966cfa65cd1767cbddb209166c18fedc74 (patch) | |
tree | 504272d1449308d26b78063d77e3297d3348cc7b | |
parent | bdca6daee20daf9c14f272fe1ab07990e881e518 (diff) |
mtd: denali.c: fix reserved all check-patch errors
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
-rw-r--r-- | drivers/mtd/nand/denali.c | 102 |
1 files changed, 53 insertions, 49 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 3ce11cc69721..52278d839d08 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c | |||
@@ -119,7 +119,7 @@ static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP, | |||
119 | INTR_STATUS3__RST_COMP}; | 119 | INTR_STATUS3__RST_COMP}; |
120 | 120 | ||
121 | /* specifies the debug level of the driver */ | 121 | /* specifies the debug level of the driver */ |
122 | static int nand_debug_level = 0; | 122 | static int nand_debug_level; |
123 | 123 | ||
124 | /* forward declarations */ | 124 | /* forward declarations */ |
125 | static void clear_interrupts(struct denali_nand_info *denali); | 125 | static void clear_interrupts(struct denali_nand_info *denali); |
@@ -991,7 +991,7 @@ static void denali_irq_enable(struct denali_nand_info *denali, | |||
991 | */ | 991 | */ |
992 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) | 992 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) |
993 | { | 993 | { |
994 | return (read_interrupt_status(denali) & DENALI_IRQ_ALL); | 994 | return read_interrupt_status(denali) & DENALI_IRQ_ALL; |
995 | } | 995 | } |
996 | 996 | ||
997 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ | 997 | /* Interrupts are cleared by writing a 1 to the appropriate status bit */ |
@@ -1172,9 +1172,12 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | |||
1172 | uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, | 1172 | uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, |
1173 | irq_mask = 0; | 1173 | irq_mask = 0; |
1174 | 1174 | ||
1175 | if (op == DENALI_READ) irq_mask = INTR_STATUS0__LOAD_COMP; | 1175 | if (op == DENALI_READ) |
1176 | else if (op == DENALI_WRITE) irq_mask = 0; | 1176 | irq_mask = INTR_STATUS0__LOAD_COMP; |
1177 | else BUG(); | 1177 | else if (op == DENALI_WRITE) |
1178 | irq_mask = 0; | ||
1179 | else | ||
1180 | BUG(); | ||
1178 | 1181 | ||
1179 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | 1182 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); |
1180 | 1183 | ||
@@ -1448,7 +1451,8 @@ static void denali_enable_dma(struct denali_nand_info *denali, bool en) | |||
1448 | { | 1451 | { |
1449 | uint32_t reg_val = 0x0; | 1452 | uint32_t reg_val = 0x0; |
1450 | 1453 | ||
1451 | if (en) reg_val = DMA_ENABLE__FLAG; | 1454 | if (en) |
1455 | reg_val = DMA_ENABLE__FLAG; | ||
1452 | 1456 | ||
1453 | denali_write32(reg_val, denali->flash_reg + DMA_ENABLE); | 1457 | denali_write32(reg_val, denali->flash_reg + DMA_ENABLE); |
1454 | ioread32(denali->flash_reg + DMA_ENABLE); | 1458 | ioread32(denali->flash_reg + DMA_ENABLE); |
@@ -1721,47 +1725,47 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, | |||
1721 | printk(KERN_INFO "cmdfunc: 0x%x %d %d\n", cmd, col, page); | 1725 | printk(KERN_INFO "cmdfunc: 0x%x %d %d\n", cmd, col, page); |
1722 | #endif | 1726 | #endif |
1723 | switch (cmd) { | 1727 | switch (cmd) { |
1724 | case NAND_CMD_PAGEPROG: | 1728 | case NAND_CMD_PAGEPROG: |
1725 | break; | 1729 | break; |
1726 | case NAND_CMD_STATUS: | 1730 | case NAND_CMD_STATUS: |
1727 | read_status(denali); | 1731 | read_status(denali); |
1728 | break; | 1732 | break; |
1729 | case NAND_CMD_READID: | 1733 | case NAND_CMD_READID: |
1730 | reset_buf(denali); | 1734 | reset_buf(denali); |
1731 | if (denali->flash_bank < denali->total_used_banks) { | 1735 | if (denali->flash_bank < denali->total_used_banks) { |
1732 | /* write manufacturer information into nand | 1736 | /* write manufacturer information into nand |
1733 | buffer for NAND subsystem to fetch. | 1737 | buffer for NAND subsystem to fetch. |
1734 | */ | 1738 | */ |
1735 | write_byte_to_buf(denali, | 1739 | write_byte_to_buf(denali, |
1736 | denali->dev_info.wDeviceMaker); | 1740 | denali->dev_info.wDeviceMaker); |
1737 | write_byte_to_buf(denali, | 1741 | write_byte_to_buf(denali, |
1738 | denali->dev_info.wDeviceID); | 1742 | denali->dev_info.wDeviceID); |
1739 | write_byte_to_buf(denali, | 1743 | write_byte_to_buf(denali, |
1740 | denali->dev_info.bDeviceParam0); | 1744 | denali->dev_info.bDeviceParam0); |
1741 | write_byte_to_buf(denali, | 1745 | write_byte_to_buf(denali, |
1742 | denali->dev_info.bDeviceParam1); | 1746 | denali->dev_info.bDeviceParam1); |
1743 | write_byte_to_buf(denali, | 1747 | write_byte_to_buf(denali, |
1744 | denali->dev_info.bDeviceParam2); | 1748 | denali->dev_info.bDeviceParam2); |
1745 | } else { | 1749 | } else { |
1746 | int i; | 1750 | int i; |
1747 | for (i = 0; i < 5; i++) | 1751 | for (i = 0; i < 5; i++) |
1748 | write_byte_to_buf(denali, 0xff); | 1752 | write_byte_to_buf(denali, 0xff); |
1749 | } | 1753 | } |
1750 | break; | 1754 | break; |
1751 | case NAND_CMD_READ0: | 1755 | case NAND_CMD_READ0: |
1752 | case NAND_CMD_SEQIN: | 1756 | case NAND_CMD_SEQIN: |
1753 | denali->page = page; | 1757 | denali->page = page; |
1754 | break; | 1758 | break; |
1755 | case NAND_CMD_RESET: | 1759 | case NAND_CMD_RESET: |
1756 | reset_bank(denali); | 1760 | reset_bank(denali); |
1757 | break; | 1761 | break; |
1758 | case NAND_CMD_READOOB: | 1762 | case NAND_CMD_READOOB: |
1759 | /* TODO: Read OOB data */ | 1763 | /* TODO: Read OOB data */ |
1760 | break; | 1764 | break; |
1761 | default: | 1765 | default: |
1762 | printk(KERN_ERR ": unsupported command" | 1766 | printk(KERN_ERR ": unsupported command" |
1763 | " received 0x%x\n", cmd); | 1767 | " received 0x%x\n", cmd); |
1764 | break; | 1768 | break; |
1765 | } | 1769 | } |
1766 | } | 1770 | } |
1767 | 1771 | ||
@@ -1807,7 +1811,7 @@ static void denali_hw_init(struct denali_nand_info *denali) | |||
1807 | } | 1811 | } |
1808 | 1812 | ||
1809 | /* ECC layout for SLC devices. Denali spec indicates SLC fixed at 4 bytes */ | 1813 | /* ECC layout for SLC devices. Denali spec indicates SLC fixed at 4 bytes */ |
1810 | #define ECC_BYTES_SLC 4 * (2048 / ECC_SECTOR_SIZE) | 1814 | #define ECC_BYTES_SLC (4 * (2048 / ECC_SECTOR_SIZE)) |
1811 | static struct nand_ecclayout nand_oob_slc = { | 1815 | static struct nand_ecclayout nand_oob_slc = { |
1812 | .eccbytes = 4, | 1816 | .eccbytes = 4, |
1813 | .eccpos = { 0, 1, 2, 3 }, /* not used */ | 1817 | .eccpos = { 0, 1, 2, 3 }, /* not used */ |
@@ -1819,7 +1823,7 @@ static struct nand_ecclayout nand_oob_slc = { | |||
1819 | } | 1823 | } |
1820 | }; | 1824 | }; |
1821 | 1825 | ||
1822 | #define ECC_BYTES_MLC 14 * (2048 / ECC_SECTOR_SIZE) | 1826 | #define ECC_BYTES_MLC (14 * (2048 / ECC_SECTOR_SIZE)) |
1823 | static struct nand_ecclayout nand_oob_mlc_14bit = { | 1827 | static struct nand_ecclayout nand_oob_mlc_14bit = { |
1824 | .eccbytes = 14, | 1828 | .eccbytes = 14, |
1825 | .eccpos = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13 }, /* not used */ | 1829 | .eccpos = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13 }, /* not used */ |