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authorRajendra Nayak <rnayak@ti.com>2009-12-08 20:47:16 -0500
committerpaul <paul@twilight.(none)>2009-12-11 19:00:46 -0500
commita1391d276866845018920329bc2a3a82ab322af8 (patch)
treea16a46b6d0af3cb5e3dcd4f7de207f138d087011
parentd79b126724554122d9598834ef39fb0bb4fc132d (diff)
ARM: OMAP4: PM: Move DPLL control apis to dpll.c
This patch moves all the dpll control api's to a common file dpll.c. This is in preperation of omap4 support wherein most of these api's can be reused. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/Makefile3
-rw-r--r--arch/arm/mach-omap2/clock.h13
-rw-r--r--arch/arm/mach-omap2/clock34xx.c489
-rw-r--r--arch/arm/mach-omap2/clock34xx.h11
-rw-r--r--arch/arm/mach-omap2/clock44xx.h8
-rw-r--r--arch/arm/mach-omap2/dpll.c532
6 files changed, 547 insertions, 509 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 3078ff4d3c71..551df7272247 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -10,7 +10,8 @@ prcm-common = prcm.o powerdomain.o
10clock-common = clock.o clock_common_data.o clockdomain.o 10clock-common = clock.o clock_common_data.o clockdomain.o
11 11
12obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) 12obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)
13obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) 13obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
14 dpll.o
14obj-$(CONFIG_ARCH_OMAP4) += prcm.o clock.o 15obj-$(CONFIG_ARCH_OMAP4) += prcm.o clock.o
15 16
16obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o 17obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 87c08056b303..4df7aa43ef44 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -36,6 +36,11 @@
36#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 36#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
37#define OMAP3XXX_EN_DPLL_LOCKED 0x7 37#define OMAP3XXX_EN_DPLL_LOCKED 0x7
38 38
39/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
40#define DPLL_LOW_POWER_STOP 0x1
41#define DPLL_LOW_POWER_BYPASS 0x5
42#define DPLL_LOCKED 0x7
43
39int omap2_clk_init(void); 44int omap2_clk_init(void);
40int omap2_clk_enable(struct clk *clk); 45int omap2_clk_enable(struct clk *clk);
41void omap2_clk_disable(struct clk *clk); 46void omap2_clk_disable(struct clk *clk);
@@ -44,6 +49,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
44int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); 49int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
45int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); 50int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
46long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); 51long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
52unsigned long omap3_dpll_recalc(struct clk *clk);
53unsigned long omap3_clkoutx2_recalc(struct clk *clk);
54void omap3_dpll_allow_idle(struct clk *clk);
55void omap3_dpll_deny_idle(struct clk *clk);
56u32 omap3_dpll_autoidle_read(struct clk *clk);
57int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
58int omap3_noncore_dpll_enable(struct clk *clk);
59void omap3_noncore_dpll_disable(struct clk *clk);
47 60
48#ifdef CONFIG_OMAP_RESET_CLOCKS 61#ifdef CONFIG_OMAP_RESET_CLOCKS
49void omap2_clk_disable_unused(struct clk *clk); 62void omap2_clk_disable_unused(struct clk *clk);
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6dc46dc1ea3a..ded32364f32b 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -43,12 +43,6 @@
43#include "cm.h" 43#include "cm.h"
44#include "cm-regbits-34xx.h" 44#include "cm-regbits-34xx.h"
45 45
46/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
47#define DPLL_AUTOIDLE_DISABLE 0x0
48#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
49
50#define MAX_DPLL_WAIT_TRIES 1000000
51
52#define CYCLES_PER_MHZ 1000000 46#define CYCLES_PER_MHZ 1000000
53 47
54/* 48/*
@@ -149,376 +143,11 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = {
149 .find_companion = omap2_clk_dflt_find_companion, 143 .find_companion = omap2_clk_dflt_find_companion,
150}; 144};
151 145
152/**
153 * omap3_dpll_recalc - recalculate DPLL rate
154 * @clk: DPLL struct clk
155 *
156 * Recalculate and propagate the DPLL rate.
157 */
158unsigned long omap3_dpll_recalc(struct clk *clk)
159{
160 return omap2_get_dpll_rate(clk);
161}
162
163/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
164static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
165{
166 const struct dpll_data *dd;
167 u32 v;
168
169 dd = clk->dpll_data;
170
171 v = __raw_readl(dd->control_reg);
172 v &= ~dd->enable_mask;
173 v |= clken_bits << __ffs(dd->enable_mask);
174 __raw_writel(v, dd->control_reg);
175}
176
177/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
178static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
179{
180 const struct dpll_data *dd;
181 int i = 0;
182 int ret = -EINVAL;
183
184 dd = clk->dpll_data;
185
186 state <<= __ffs(dd->idlest_mask);
187
188 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
189 i < MAX_DPLL_WAIT_TRIES) {
190 i++;
191 udelay(1);
192 }
193
194 if (i == MAX_DPLL_WAIT_TRIES) {
195 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
196 clk->name, (state) ? "locked" : "bypassed");
197 } else {
198 pr_debug("clock: %s transition to '%s' in %d loops\n",
199 clk->name, (state) ? "locked" : "bypassed", i);
200
201 ret = 0;
202 }
203
204 return ret;
205}
206
207/* From 3430 TRM ES2 4.7.6.2 */
208static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
209{
210 unsigned long fint;
211 u16 f = 0;
212
213 fint = clk->dpll_data->clk_ref->rate / n;
214
215 pr_debug("clock: fint is %lu\n", fint);
216
217 if (fint >= 750000 && fint <= 1000000)
218 f = 0x3;
219 else if (fint > 1000000 && fint <= 1250000)
220 f = 0x4;
221 else if (fint > 1250000 && fint <= 1500000)
222 f = 0x5;
223 else if (fint > 1500000 && fint <= 1750000)
224 f = 0x6;
225 else if (fint > 1750000 && fint <= 2100000)
226 f = 0x7;
227 else if (fint > 7500000 && fint <= 10000000)
228 f = 0xB;
229 else if (fint > 10000000 && fint <= 12500000)
230 f = 0xC;
231 else if (fint > 12500000 && fint <= 15000000)
232 f = 0xD;
233 else if (fint > 15000000 && fint <= 17500000)
234 f = 0xE;
235 else if (fint > 17500000 && fint <= 21000000)
236 f = 0xF;
237 else
238 pr_debug("clock: unknown freqsel setting for %d\n", n);
239
240 return f;
241}
242
243/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
244
245/*
246 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
247 * @clk: pointer to a DPLL struct clk
248 *
249 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
250 * readiness before returning. Will save and restore the DPLL's
251 * autoidle state across the enable, per the CDP code. If the DPLL
252 * locked successfully, return 0; if the DPLL did not lock in the time
253 * allotted, or DPLL3 was passed in, return -EINVAL.
254 */
255static int _omap3_noncore_dpll_lock(struct clk *clk)
256{
257 u8 ai;
258 int r;
259
260 pr_debug("clock: locking DPLL %s\n", clk->name);
261
262 ai = omap3_dpll_autoidle_read(clk);
263
264 omap3_dpll_deny_idle(clk);
265
266 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
267
268 r = _omap3_wait_dpll_status(clk, 1);
269
270 if (ai)
271 omap3_dpll_allow_idle(clk);
272
273 return r;
274}
275
276/*
277 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
278 * @clk: pointer to a DPLL struct clk
279 *
280 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
281 * bypass mode, the DPLL's rate is set equal to its parent clock's
282 * rate. Waits for the DPLL to report readiness before returning.
283 * Will save and restore the DPLL's autoidle state across the enable,
284 * per the CDP code. If the DPLL entered bypass mode successfully,
285 * return 0; if the DPLL did not enter bypass in the time allotted, or
286 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
287 * return -EINVAL.
288 */
289static int _omap3_noncore_dpll_bypass(struct clk *clk)
290{
291 int r;
292 u8 ai;
293
294 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
295 return -EINVAL;
296
297 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
298 clk->name);
299
300 ai = omap3_dpll_autoidle_read(clk);
301
302 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
303
304 r = _omap3_wait_dpll_status(clk, 0);
305
306 if (ai)
307 omap3_dpll_allow_idle(clk);
308 else
309 omap3_dpll_deny_idle(clk);
310
311 return r;
312}
313
314/*
315 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
316 * @clk: pointer to a DPLL struct clk
317 *
318 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
319 * restore the DPLL's autoidle state across the stop, per the CDP
320 * code. If DPLL3 was passed in, or the DPLL does not support
321 * low-power stop, return -EINVAL; otherwise, return 0.
322 */
323static int _omap3_noncore_dpll_stop(struct clk *clk)
324{
325 u8 ai;
326
327 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
328 return -EINVAL;
329
330 pr_debug("clock: stopping DPLL %s\n", clk->name);
331
332 ai = omap3_dpll_autoidle_read(clk);
333
334 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
335
336 if (ai)
337 omap3_dpll_allow_idle(clk);
338 else
339 omap3_dpll_deny_idle(clk);
340
341 return 0;
342}
343
344/**
345 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
346 * @clk: pointer to a DPLL struct clk
347 *
348 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
349 * The choice of modes depends on the DPLL's programmed rate: if it is
350 * the same as the DPLL's parent clock, it will enter bypass;
351 * otherwise, it will enter lock. This code will wait for the DPLL to
352 * indicate readiness before returning, unless the DPLL takes too long
353 * to enter the target state. Intended to be used as the struct clk's
354 * enable function. If DPLL3 was passed in, or the DPLL does not
355 * support low-power stop, or if the DPLL took too long to enter
356 * bypass or lock, return -EINVAL; otherwise, return 0.
357 */
358static int omap3_noncore_dpll_enable(struct clk *clk)
359{
360 int r;
361 struct dpll_data *dd;
362
363 dd = clk->dpll_data;
364 if (!dd)
365 return -EINVAL;
366
367 if (clk->rate == dd->clk_bypass->rate) {
368 WARN_ON(clk->parent != dd->clk_bypass);
369 r = _omap3_noncore_dpll_bypass(clk);
370 } else {
371 WARN_ON(clk->parent != dd->clk_ref);
372 r = _omap3_noncore_dpll_lock(clk);
373 }
374 /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
375 if (!r)
376 clk->rate = omap2_get_dpll_rate(clk);
377
378 return r;
379}
380
381/**
382 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
383 * @clk: pointer to a DPLL struct clk
384 *
385 * Instructs a non-CORE DPLL to enter low-power stop. This function is
386 * intended for use in struct clkops. No return value.
387 */
388static void omap3_noncore_dpll_disable(struct clk *clk)
389{
390 _omap3_noncore_dpll_stop(clk);
391}
392
393const struct clkops clkops_noncore_dpll_ops = { 146const struct clkops clkops_noncore_dpll_ops = {
394 .enable = omap3_noncore_dpll_enable, 147 .enable = omap3_noncore_dpll_enable,
395 .disable = omap3_noncore_dpll_disable, 148 .disable = omap3_noncore_dpll_disable,
396}; 149};
397 150
398/* Non-CORE DPLL rate set code */
399
400/*
401 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
402 * @clk: struct clk * of DPLL to set
403 * @m: DPLL multiplier to set
404 * @n: DPLL divider to set
405 * @freqsel: FREQSEL value to set
406 *
407 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
408 * lock.. Returns -EINVAL upon error, or 0 upon success.
409 */
410static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
411{
412 struct dpll_data *dd = clk->dpll_data;
413 u32 v;
414
415 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
416 _omap3_noncore_dpll_bypass(clk);
417
418 /* Set jitter correction */
419 v = __raw_readl(dd->control_reg);
420 v &= ~dd->freqsel_mask;
421 v |= freqsel << __ffs(dd->freqsel_mask);
422 __raw_writel(v, dd->control_reg);
423
424 /* Set DPLL multiplier, divider */
425 v = __raw_readl(dd->mult_div1_reg);
426 v &= ~(dd->mult_mask | dd->div1_mask);
427 v |= m << __ffs(dd->mult_mask);
428 v |= (n - 1) << __ffs(dd->div1_mask);
429 __raw_writel(v, dd->mult_div1_reg);
430
431 /* We let the clock framework set the other output dividers later */
432
433 /* REVISIT: Set ramp-up delay? */
434
435 _omap3_noncore_dpll_lock(clk);
436
437 return 0;
438}
439
440/**
441 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
442 * @clk: struct clk * of DPLL to set
443 * @rate: rounded target rate
444 *
445 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
446 * low-power bypass, and the target rate is the bypass source clock
447 * rate, then configure the DPLL for bypass. Otherwise, round the
448 * target rate if it hasn't been done already, then program and lock
449 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
450 */
451int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
452{
453 struct clk *new_parent = NULL;
454 u16 freqsel;
455 struct dpll_data *dd;
456 int ret;
457
458 if (!clk || !rate)
459 return -EINVAL;
460
461 dd = clk->dpll_data;
462 if (!dd)
463 return -EINVAL;
464
465 if (rate == omap2_get_dpll_rate(clk))
466 return 0;
467
468 /*
469 * Ensure both the bypass and ref clocks are enabled prior to
470 * doing anything; we need the bypass clock running to reprogram
471 * the DPLL.
472 */
473 omap2_clk_enable(dd->clk_bypass);
474 omap2_clk_enable(dd->clk_ref);
475
476 if (dd->clk_bypass->rate == rate &&
477 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
478 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
479
480 ret = _omap3_noncore_dpll_bypass(clk);
481 if (!ret)
482 new_parent = dd->clk_bypass;
483 } else {
484 if (dd->last_rounded_rate != rate)
485 omap2_dpll_round_rate(clk, rate);
486
487 if (dd->last_rounded_rate == 0)
488 return -EINVAL;
489
490 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
491 if (!freqsel)
492 WARN_ON(1);
493
494 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
495 clk->name, rate);
496
497 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
498 dd->last_rounded_n, freqsel);
499 if (!ret)
500 new_parent = dd->clk_ref;
501 }
502 if (!ret) {
503 /*
504 * Switch the parent clock in the heirarchy, and make sure
505 * that the new parent's usecount is correct. Note: we
506 * enable the new parent before disabling the old to avoid
507 * any unnecessary hardware disable->enable transitions.
508 */
509 if (clk->usecount) {
510 omap2_clk_enable(new_parent);
511 omap2_clk_disable(clk->parent);
512 }
513 clk_reparent(clk, new_parent);
514 clk->rate = rate;
515 }
516 omap2_clk_disable(dd->clk_ref);
517 omap2_clk_disable(dd->clk_bypass);
518
519 return 0;
520}
521
522int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) 151int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
523{ 152{
524 /* 153 /*
@@ -622,124 +251,6 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
622 return 0; 251 return 0;
623} 252}
624 253
625
626/* DPLL autoidle read/set code */
627
628
629/**
630 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
631 * @clk: struct clk * of the DPLL to read
632 *
633 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
634 * -EINVAL if passed a null pointer or if the struct clk does not
635 * appear to refer to a DPLL.
636 */
637u32 omap3_dpll_autoidle_read(struct clk *clk)
638{
639 const struct dpll_data *dd;
640 u32 v;
641
642 if (!clk || !clk->dpll_data)
643 return -EINVAL;
644
645 dd = clk->dpll_data;
646
647 v = __raw_readl(dd->autoidle_reg);
648 v &= dd->autoidle_mask;
649 v >>= __ffs(dd->autoidle_mask);
650
651 return v;
652}
653
654/**
655 * omap3_dpll_allow_idle - enable DPLL autoidle bits
656 * @clk: struct clk * of the DPLL to operate on
657 *
658 * Enable DPLL automatic idle control. This automatic idle mode
659 * switching takes effect only when the DPLL is locked, at least on
660 * OMAP3430. The DPLL will enter low-power stop when its downstream
661 * clocks are gated. No return value.
662 */
663void omap3_dpll_allow_idle(struct clk *clk)
664{
665 const struct dpll_data *dd;
666 u32 v;
667
668 if (!clk || !clk->dpll_data)
669 return;
670
671 dd = clk->dpll_data;
672
673 /*
674 * REVISIT: CORE DPLL can optionally enter low-power bypass
675 * by writing 0x5 instead of 0x1. Add some mechanism to
676 * optionally enter this mode.
677 */
678 v = __raw_readl(dd->autoidle_reg);
679 v &= ~dd->autoidle_mask;
680 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
681 __raw_writel(v, dd->autoidle_reg);
682}
683
684/**
685 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
686 * @clk: struct clk * of the DPLL to operate on
687 *
688 * Disable DPLL automatic idle control. No return value.
689 */
690void omap3_dpll_deny_idle(struct clk *clk)
691{
692 const struct dpll_data *dd;
693 u32 v;
694
695 if (!clk || !clk->dpll_data)
696 return;
697
698 dd = clk->dpll_data;
699
700 v = __raw_readl(dd->autoidle_reg);
701 v &= ~dd->autoidle_mask;
702 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
703 __raw_writel(v, dd->autoidle_reg);
704}
705
706/* Clock control for DPLL outputs */
707
708/**
709 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
710 * @clk: DPLL output struct clk
711 *
712 * Using parent clock DPLL data, look up DPLL state. If locked, set our
713 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
714 */
715unsigned long omap3_clkoutx2_recalc(struct clk *clk)
716{
717 const struct dpll_data *dd;
718 unsigned long rate;
719 u32 v;
720 struct clk *pclk;
721
722 /* Walk up the parents of clk, looking for a DPLL */
723 pclk = clk->parent;
724 while (pclk && !pclk->dpll_data)
725 pclk = pclk->parent;
726
727 /* clk does not have a DPLL as a parent? */
728 WARN_ON(!pclk);
729
730 dd = pclk->dpll_data;
731
732 WARN_ON(!dd->enable_mask);
733
734 v = __raw_readl(dd->control_reg) & dd->enable_mask;
735 v >>= __ffs(dd->enable_mask);
736 if (v != OMAP3XXX_EN_DPLL_LOCKED)
737 rate = clk->parent->rate;
738 else
739 rate = clk->parent->rate * 2;
740 return rate;
741}
742
743/* Common clock code */ 254/* Common clock code */
744 255
745/* 256/*
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index b08809efb0c8..9a2c07eac9ad 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -8,21 +8,10 @@
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H 8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H 9#define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
10 10
11unsigned long omap3_dpll_recalc(struct clk *clk);
12unsigned long omap3_clkoutx2_recalc(struct clk *clk);
13void omap3_dpll_allow_idle(struct clk *clk);
14void omap3_dpll_deny_idle(struct clk *clk);
15u32 omap3_dpll_autoidle_read(struct clk *clk);
16int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
17int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); 11int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
18int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); 12int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
19void omap3_clk_lock_dpll5(void); 13void omap3_clk_lock_dpll5(void);
20 14
21/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
22#define DPLL_LOW_POWER_STOP 0x1
23#define DPLL_LOW_POWER_BYPASS 0x5
24#define DPLL_LOCKED 0x7
25
26extern struct clk *sdrc_ick_p; 15extern struct clk *sdrc_ick_p;
27extern struct clk *arm_fck_p; 16extern struct clk *arm_fck_p;
28 17
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h
index c1bc4b6eb6b3..59b9ced4daa1 100644
--- a/arch/arm/mach-omap2/clock44xx.h
+++ b/arch/arm/mach-omap2/clock44xx.h
@@ -7,14 +7,6 @@
7#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H 7#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
8#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H 8#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
9 9
10unsigned long omap3_dpll_recalc(struct clk *clk);
11unsigned long omap3_clkoutx2_recalc(struct clk *clk);
12int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
13
14/* DPLL modes */
15#define DPLL_LOW_POWER_STOP 0x1
16#define DPLL_LOW_POWER_BYPASS 0x5
17#define DPLL_LOCKED 0x7
18#define OMAP4430_MAX_DPLL_MULT 2048 10#define OMAP4430_MAX_DPLL_MULT 2048
19#define OMAP4430_MAX_DPLL_DIV 128 11#define OMAP4430_MAX_DPLL_DIV 128
20 12
diff --git a/arch/arm/mach-omap2/dpll.c b/arch/arm/mach-omap2/dpll.c
new file mode 100644
index 000000000000..a39fe9d8c278
--- /dev/null
+++ b/arch/arm/mach-omap2/dpll.c
@@ -0,0 +1,532 @@
1/*
2 * OMAP3/4 - specific DPLL control functions
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/device.h>
21#include <linux/list.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26#include <linux/limits.h>
27#include <linux/bitops.h>
28
29#include <mach/cpu.h>
30#include <mach/clock.h>
31#include <mach/sram.h>
32#include <asm/div64.h>
33#include <asm/clkdev.h>
34
35#include "clock.h"
36#include "prm.h"
37#include "prm-regbits-34xx.h"
38#include "cm.h"
39#include "cm-regbits-34xx.h"
40
41/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
42#define DPLL_AUTOIDLE_DISABLE 0x0
43#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
44
45#define MAX_DPLL_WAIT_TRIES 1000000
46
47
48/**
49 * omap3_dpll_recalc - recalculate DPLL rate
50 * @clk: DPLL struct clk
51 *
52 * Recalculate and propagate the DPLL rate.
53 */
54unsigned long omap3_dpll_recalc(struct clk *clk)
55{
56 return omap2_get_dpll_rate(clk);
57}
58
59/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
61{
62 const struct dpll_data *dd;
63 u32 v;
64
65 dd = clk->dpll_data;
66
67 v = __raw_readl(dd->control_reg);
68 v &= ~dd->enable_mask;
69 v |= clken_bits << __ffs(dd->enable_mask);
70 __raw_writel(v, dd->control_reg);
71}
72
73/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
74static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
75{
76 const struct dpll_data *dd;
77 int i = 0;
78 int ret = -EINVAL;
79
80 dd = clk->dpll_data;
81
82 state <<= __ffs(dd->idlest_mask);
83
84 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
85 i < MAX_DPLL_WAIT_TRIES) {
86 i++;
87 udelay(1);
88 }
89
90 if (i == MAX_DPLL_WAIT_TRIES) {
91 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
92 clk->name, (state) ? "locked" : "bypassed");
93 } else {
94 pr_debug("clock: %s transition to '%s' in %d loops\n",
95 clk->name, (state) ? "locked" : "bypassed", i);
96
97 ret = 0;
98 }
99
100 return ret;
101}
102
103/* From 3430 TRM ES2 4.7.6.2 */
104static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
105{
106 unsigned long fint;
107 u16 f = 0;
108
109 fint = clk->dpll_data->clk_ref->rate / n;
110
111 pr_debug("clock: fint is %lu\n", fint);
112
113 if (fint >= 750000 && fint <= 1000000)
114 f = 0x3;
115 else if (fint > 1000000 && fint <= 1250000)
116 f = 0x4;
117 else if (fint > 1250000 && fint <= 1500000)
118 f = 0x5;
119 else if (fint > 1500000 && fint <= 1750000)
120 f = 0x6;
121 else if (fint > 1750000 && fint <= 2100000)
122 f = 0x7;
123 else if (fint > 7500000 && fint <= 10000000)
124 f = 0xB;
125 else if (fint > 10000000 && fint <= 12500000)
126 f = 0xC;
127 else if (fint > 12500000 && fint <= 15000000)
128 f = 0xD;
129 else if (fint > 15000000 && fint <= 17500000)
130 f = 0xE;
131 else if (fint > 17500000 && fint <= 21000000)
132 f = 0xF;
133 else
134 pr_debug("clock: unknown freqsel setting for %d\n", n);
135
136 return f;
137}
138
139/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
140
141/*
142 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
143 * @clk: pointer to a DPLL struct clk
144 *
145 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
146 * readiness before returning. Will save and restore the DPLL's
147 * autoidle state across the enable, per the CDP code. If the DPLL
148 * locked successfully, return 0; if the DPLL did not lock in the time
149 * allotted, or DPLL3 was passed in, return -EINVAL.
150 */
151static int _omap3_noncore_dpll_lock(struct clk *clk)
152{
153 u8 ai;
154 int r;
155
156 pr_debug("clock: locking DPLL %s\n", clk->name);
157
158 ai = omap3_dpll_autoidle_read(clk);
159
160 omap3_dpll_deny_idle(clk);
161
162 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
163
164 r = _omap3_wait_dpll_status(clk, 1);
165
166 if (ai)
167 omap3_dpll_allow_idle(clk);
168
169 return r;
170}
171
172/*
173 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
174 * @clk: pointer to a DPLL struct clk
175 *
176 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
177 * bypass mode, the DPLL's rate is set equal to its parent clock's
178 * rate. Waits for the DPLL to report readiness before returning.
179 * Will save and restore the DPLL's autoidle state across the enable,
180 * per the CDP code. If the DPLL entered bypass mode successfully,
181 * return 0; if the DPLL did not enter bypass in the time allotted, or
182 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
183 * return -EINVAL.
184 */
185static int _omap3_noncore_dpll_bypass(struct clk *clk)
186{
187 int r;
188 u8 ai;
189
190 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
191 return -EINVAL;
192
193 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
194 clk->name);
195
196 ai = omap3_dpll_autoidle_read(clk);
197
198 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
199
200 r = _omap3_wait_dpll_status(clk, 0);
201
202 if (ai)
203 omap3_dpll_allow_idle(clk);
204 else
205 omap3_dpll_deny_idle(clk);
206
207 return r;
208}
209
210/*
211 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
212 * @clk: pointer to a DPLL struct clk
213 *
214 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
215 * restore the DPLL's autoidle state across the stop, per the CDP
216 * code. If DPLL3 was passed in, or the DPLL does not support
217 * low-power stop, return -EINVAL; otherwise, return 0.
218 */
219static int _omap3_noncore_dpll_stop(struct clk *clk)
220{
221 u8 ai;
222
223 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
224 return -EINVAL;
225
226 pr_debug("clock: stopping DPLL %s\n", clk->name);
227
228 ai = omap3_dpll_autoidle_read(clk);
229
230 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
231
232 if (ai)
233 omap3_dpll_allow_idle(clk);
234 else
235 omap3_dpll_deny_idle(clk);
236
237 return 0;
238}
239
240/**
241 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
242 * @clk: pointer to a DPLL struct clk
243 *
244 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
245 * The choice of modes depends on the DPLL's programmed rate: if it is
246 * the same as the DPLL's parent clock, it will enter bypass;
247 * otherwise, it will enter lock. This code will wait for the DPLL to
248 * indicate readiness before returning, unless the DPLL takes too long
249 * to enter the target state. Intended to be used as the struct clk's
250 * enable function. If DPLL3 was passed in, or the DPLL does not
251 * support low-power stop, or if the DPLL took too long to enter
252 * bypass or lock, return -EINVAL; otherwise, return 0.
253 */
254int omap3_noncore_dpll_enable(struct clk *clk)
255{
256 int r;
257 struct dpll_data *dd;
258
259 dd = clk->dpll_data;
260 if (!dd)
261 return -EINVAL;
262
263 if (clk->rate == dd->clk_bypass->rate) {
264 WARN_ON(clk->parent != dd->clk_bypass);
265 r = _omap3_noncore_dpll_bypass(clk);
266 } else {
267 WARN_ON(clk->parent != dd->clk_ref);
268 r = _omap3_noncore_dpll_lock(clk);
269 }
270 /*
271 *FIXME: this is dubious - if clk->rate has changed, what about
272 * propagating?
273 */
274 if (!r)
275 clk->rate = omap2_get_dpll_rate(clk);
276
277 return r;
278}
279
280/**
281 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
282 * @clk: pointer to a DPLL struct clk
283 *
284 * Instructs a non-CORE DPLL to enter low-power stop. This function is
285 * intended for use in struct clkops. No return value.
286 */
287void omap3_noncore_dpll_disable(struct clk *clk)
288{
289 _omap3_noncore_dpll_stop(clk);
290}
291
292
293/* Non-CORE DPLL rate set code */
294
295/*
296 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
297 * @clk: struct clk * of DPLL to set
298 * @m: DPLL multiplier to set
299 * @n: DPLL divider to set
300 * @freqsel: FREQSEL value to set
301 *
302 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
303 * lock.. Returns -EINVAL upon error, or 0 upon success.
304 */
305int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
306{
307 struct dpll_data *dd = clk->dpll_data;
308 u32 v;
309
310 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
311 _omap3_noncore_dpll_bypass(clk);
312
313 /* Set jitter correction */
314 v = __raw_readl(dd->control_reg);
315 v &= ~dd->freqsel_mask;
316 v |= freqsel << __ffs(dd->freqsel_mask);
317 __raw_writel(v, dd->control_reg);
318
319 /* Set DPLL multiplier, divider */
320 v = __raw_readl(dd->mult_div1_reg);
321 v &= ~(dd->mult_mask | dd->div1_mask);
322 v |= m << __ffs(dd->mult_mask);
323 v |= (n - 1) << __ffs(dd->div1_mask);
324 __raw_writel(v, dd->mult_div1_reg);
325
326 /* We let the clock framework set the other output dividers later */
327
328 /* REVISIT: Set ramp-up delay? */
329
330 _omap3_noncore_dpll_lock(clk);
331
332 return 0;
333}
334
335/**
336 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
337 * @clk: struct clk * of DPLL to set
338 * @rate: rounded target rate
339 *
340 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
341 * low-power bypass, and the target rate is the bypass source clock
342 * rate, then configure the DPLL for bypass. Otherwise, round the
343 * target rate if it hasn't been done already, then program and lock
344 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
345 */
346int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
347{
348 struct clk *new_parent = NULL;
349 u16 freqsel;
350 struct dpll_data *dd;
351 int ret;
352
353 if (!clk || !rate)
354 return -EINVAL;
355
356 dd = clk->dpll_data;
357 if (!dd)
358 return -EINVAL;
359
360 if (rate == omap2_get_dpll_rate(clk))
361 return 0;
362
363 /*
364 * Ensure both the bypass and ref clocks are enabled prior to
365 * doing anything; we need the bypass clock running to reprogram
366 * the DPLL.
367 */
368 omap2_clk_enable(dd->clk_bypass);
369 omap2_clk_enable(dd->clk_ref);
370
371 if (dd->clk_bypass->rate == rate &&
372 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
373 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
374
375 ret = _omap3_noncore_dpll_bypass(clk);
376 if (!ret)
377 new_parent = dd->clk_bypass;
378 } else {
379 if (dd->last_rounded_rate != rate)
380 omap2_dpll_round_rate(clk, rate);
381
382 if (dd->last_rounded_rate == 0)
383 return -EINVAL;
384
385 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
386 if (!freqsel)
387 WARN_ON(1);
388
389 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
390 clk->name, rate);
391
392 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
393 dd->last_rounded_n, freqsel);
394 if (!ret)
395 new_parent = dd->clk_ref;
396 }
397 if (!ret) {
398 /*
399 * Switch the parent clock in the heirarchy, and make sure
400 * that the new parent's usecount is correct. Note: we
401 * enable the new parent before disabling the old to avoid
402 * any unnecessary hardware disable->enable transitions.
403 */
404 if (clk->usecount) {
405 omap2_clk_enable(new_parent);
406 omap2_clk_disable(clk->parent);
407 }
408 clk_reparent(clk, new_parent);
409 clk->rate = rate;
410 }
411 omap2_clk_disable(dd->clk_ref);
412 omap2_clk_disable(dd->clk_bypass);
413
414 return 0;
415}
416
417/* DPLL autoidle read/set code */
418
419/**
420 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
421 * @clk: struct clk * of the DPLL to read
422 *
423 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
424 * -EINVAL if passed a null pointer or if the struct clk does not
425 * appear to refer to a DPLL.
426 */
427u32 omap3_dpll_autoidle_read(struct clk *clk)
428{
429 const struct dpll_data *dd;
430 u32 v;
431
432 if (!clk || !clk->dpll_data)
433 return -EINVAL;
434
435 dd = clk->dpll_data;
436
437 v = __raw_readl(dd->autoidle_reg);
438 v &= dd->autoidle_mask;
439 v >>= __ffs(dd->autoidle_mask);
440
441 return v;
442}
443
444/**
445 * omap3_dpll_allow_idle - enable DPLL autoidle bits
446 * @clk: struct clk * of the DPLL to operate on
447 *
448 * Enable DPLL automatic idle control. This automatic idle mode
449 * switching takes effect only when the DPLL is locked, at least on
450 * OMAP3430. The DPLL will enter low-power stop when its downstream
451 * clocks are gated. No return value.
452 */
453void omap3_dpll_allow_idle(struct clk *clk)
454{
455 const struct dpll_data *dd;
456 u32 v;
457
458 if (!clk || !clk->dpll_data)
459 return;
460
461 dd = clk->dpll_data;
462
463 /*
464 * REVISIT: CORE DPLL can optionally enter low-power bypass
465 * by writing 0x5 instead of 0x1. Add some mechanism to
466 * optionally enter this mode.
467 */
468 v = __raw_readl(dd->autoidle_reg);
469 v &= ~dd->autoidle_mask;
470 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
471 __raw_writel(v, dd->autoidle_reg);
472}
473
474/**
475 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
476 * @clk: struct clk * of the DPLL to operate on
477 *
478 * Disable DPLL automatic idle control. No return value.
479 */
480void omap3_dpll_deny_idle(struct clk *clk)
481{
482 const struct dpll_data *dd;
483 u32 v;
484
485 if (!clk || !clk->dpll_data)
486 return;
487
488 dd = clk->dpll_data;
489
490 v = __raw_readl(dd->autoidle_reg);
491 v &= ~dd->autoidle_mask;
492 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
493 __raw_writel(v, dd->autoidle_reg);
494
495}
496
497/* Clock control for DPLL outputs */
498
499/**
500 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
501 * @clk: DPLL output struct clk
502 *
503 * Using parent clock DPLL data, look up DPLL state. If locked, set our
504 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
505 */
506unsigned long omap3_clkoutx2_recalc(struct clk *clk)
507{
508 const struct dpll_data *dd;
509 unsigned long rate;
510 u32 v;
511 struct clk *pclk;
512
513 /* Walk up the parents of clk, looking for a DPLL */
514 pclk = clk->parent;
515 while (pclk && !pclk->dpll_data)
516 pclk = pclk->parent;
517
518 /* clk does not have a DPLL as a parent? */
519 WARN_ON(!pclk);
520
521 dd = pclk->dpll_data;
522
523 WARN_ON(!dd->enable_mask);
524
525 v = __raw_readl(dd->control_reg) & dd->enable_mask;
526 v >>= __ffs(dd->enable_mask);
527 if (v != OMAP3XXX_EN_DPLL_LOCKED)
528 rate = clk->parent->rate;
529 else
530 rate = clk->parent->rate * 2;
531 return rate;
532}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 19:34:22 -0500