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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2007-10-17 11:57:07 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-17 13:28:49 -0400
commit9ee5389c58d7e74ae06887541fbb0ff6ecc6a499 (patch)
treeda9715fa4b6f8e43f84a2309501120bd9fa17e3b
parent9d360ab4a7568a8d177280f651a8a772ae52b9b9 (diff)
[MIPS] Sibyte: Fix typos in sibyte clockevent drivers
Fix some typo introduced on clockevent conversion. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/sibyte/bcm1480/time.c2
-rw-r--r--arch/mips/sibyte/sb1250/time.c8
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index 40d7126cd5bf..5b4bfbbb5a24 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -84,7 +84,7 @@ static void sibyte_set_mode(enum clock_event_mode mode,
84 void __iomem *timer_cfg, *timer_init; 84 void __iomem *timer_cfg, *timer_init;
85 85
86 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 86 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
87 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 87 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
88 88
89 switch (mode) { 89 switch (mode) {
90 case CLOCK_EVT_MODE_PERIODIC: 90 case CLOCK_EVT_MODE_PERIODIC:
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index 38199ad8fc54..fe11fed8e0d7 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -83,7 +83,7 @@ static void sibyte_set_mode(enum clock_event_mode mode,
83 void __iomem *timer_cfg, *timer_init; 83 void __iomem *timer_cfg, *timer_init;
84 84
85 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 85 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
86 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 86 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
87 87
88 switch(mode) { 88 switch(mode) {
89 case CLOCK_EVT_MODE_PERIODIC: 89 case CLOCK_EVT_MODE_PERIODIC:
@@ -111,7 +111,7 @@ sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
111 void __iomem *timer_cfg, *timer_init; 111 void __iomem *timer_cfg, *timer_init;
112 112
113 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 113 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
114 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 114 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
115 115
116 __raw_writeq(0, timer_cfg); 116 __raw_writeq(0, timer_cfg);
117 __raw_writeq(delta, timer_init); 117 __raw_writeq(delta, timer_init);
@@ -155,7 +155,7 @@ static void sibyte_set_mode(enum clock_event_mode mode,
155 void __iomem *timer_cfg, *timer_init; 155 void __iomem *timer_cfg, *timer_init;
156 156
157 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 157 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
158 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 158 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
159 159
160 switch (mode) { 160 switch (mode) {
161 case CLOCK_EVT_MODE_PERIODIC: 161 case CLOCK_EVT_MODE_PERIODIC:
@@ -183,7 +183,7 @@ sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
183 void __iomem *timer_cfg, *timer_init; 183 void __iomem *timer_cfg, *timer_init;
184 184
185 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 185 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
186 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 186 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
187 187
188 __raw_writeq(0, timer_cfg); 188 __raw_writeq(0, timer_cfg);
189 __raw_writeq(delta, timer_init); 189 __raw_writeq(delta, timer_init);