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authorAdrian Bunk <bunk@stusta.de>2007-07-21 11:10:46 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-21 21:37:10 -0400
commit9596017e79cddb4f4fd4b896425a30f86946ce85 (patch)
treef03f0c9af1ea2081755c2e203a59dcc5b8bfacc3
parentef3e28c5b956cbb3b17531c85b698a27e83d5cf2 (diff)
x86: remove support for the Rise CPU
The Rise CPUs were only very short-lived, and there are no reports of anyone both owning one and running Linux on it. Googling for the printk string "CPU: Rise iDragon" didn't find any dmesg available online. If it turns out that against all expectations there are actually users reverting this patch would be easy. This patch will make the kernel images smaller by a few bytes for all i386 users. Signed-off-by: Adrian Bunk <bunk@stusta.de> Acked-by: Dave Jones <davej@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-rw-r--r--arch/i386/kernel/cpu/Makefile1
-rw-r--r--arch/i386/kernel/cpu/common.c2
-rw-r--r--arch/i386/kernel/cpu/rise.c52
-rw-r--r--include/asm-i386/processor.h1
-rw-r--r--include/asm-x86_64/processor.h1
5 files changed, 0 insertions, 57 deletions
diff --git a/arch/i386/kernel/cpu/Makefile b/arch/i386/kernel/cpu/Makefile
index 0b6a8551e9e2..778396c78d65 100644
--- a/arch/i386/kernel/cpu/Makefile
+++ b/arch/i386/kernel/cpu/Makefile
@@ -9,7 +9,6 @@ obj-y += cyrix.o
9obj-y += centaur.o 9obj-y += centaur.o
10obj-y += transmeta.o 10obj-y += transmeta.o
11obj-y += intel.o intel_cacheinfo.o addon_cpuid_features.o 11obj-y += intel.o intel_cacheinfo.o addon_cpuid_features.o
12obj-y += rise.o
13obj-y += nexgen.o 12obj-y += nexgen.o
14obj-y += umc.o 13obj-y += umc.o
15 14
diff --git a/arch/i386/kernel/cpu/common.c b/arch/i386/kernel/cpu/common.c
index e5419a9dec88..d506201d397c 100644
--- a/arch/i386/kernel/cpu/common.c
+++ b/arch/i386/kernel/cpu/common.c
@@ -606,7 +606,6 @@ extern int nsc_init_cpu(void);
606extern int amd_init_cpu(void); 606extern int amd_init_cpu(void);
607extern int centaur_init_cpu(void); 607extern int centaur_init_cpu(void);
608extern int transmeta_init_cpu(void); 608extern int transmeta_init_cpu(void);
609extern int rise_init_cpu(void);
610extern int nexgen_init_cpu(void); 609extern int nexgen_init_cpu(void);
611extern int umc_init_cpu(void); 610extern int umc_init_cpu(void);
612 611
@@ -618,7 +617,6 @@ void __init early_cpu_init(void)
618 amd_init_cpu(); 617 amd_init_cpu();
619 centaur_init_cpu(); 618 centaur_init_cpu();
620 transmeta_init_cpu(); 619 transmeta_init_cpu();
621 rise_init_cpu();
622 nexgen_init_cpu(); 620 nexgen_init_cpu();
623 umc_init_cpu(); 621 umc_init_cpu();
624 early_cpu_detect(); 622 early_cpu_detect();
diff --git a/arch/i386/kernel/cpu/rise.c b/arch/i386/kernel/cpu/rise.c
deleted file mode 100644
index 50076f22e90f..000000000000
--- a/arch/i386/kernel/cpu/rise.c
+++ /dev/null
@@ -1,52 +0,0 @@
1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/bitops.h>
4#include <asm/processor.h>
5
6#include "cpu.h"
7
8static void __cpuinit init_rise(struct cpuinfo_x86 *c)
9{
10 printk("CPU: Rise iDragon");
11 if (c->x86_model > 2)
12 printk(" II");
13 printk("\n");
14
15 /* Unhide possibly hidden capability flags
16 The mp6 iDragon family don't have MSRs.
17 We switch on extra features with this cpuid weirdness: */
18 __asm__ (
19 "movl $0x6363452a, %%eax\n\t"
20 "movl $0x3231206c, %%ecx\n\t"
21 "movl $0x2a32313a, %%edx\n\t"
22 "cpuid\n\t"
23 "movl $0x63634523, %%eax\n\t"
24 "movl $0x32315f6c, %%ecx\n\t"
25 "movl $0x2333313a, %%edx\n\t"
26 "cpuid\n\t" : : : "eax", "ebx", "ecx", "edx"
27 );
28 set_bit(X86_FEATURE_CX8, c->x86_capability);
29}
30
31static struct cpu_dev rise_cpu_dev __cpuinitdata = {
32 .c_vendor = "Rise",
33 .c_ident = { "RiseRiseRise" },
34 .c_models = {
35 { .vendor = X86_VENDOR_RISE, .family = 5, .model_names =
36 {
37 [0] = "iDragon",
38 [2] = "iDragon",
39 [8] = "iDragon II",
40 [9] = "iDragon II"
41 }
42 },
43 },
44 .c_init = init_rise,
45};
46
47int __init rise_init_cpu(void)
48{
49 cpu_devs[X86_VENDOR_RISE] = &rise_cpu_dev;
50 return 0;
51}
52
diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h
index 422cffef00c9..48a7f69bb767 100644
--- a/include/asm-i386/processor.h
+++ b/include/asm-i386/processor.h
@@ -88,7 +88,6 @@ struct cpuinfo_x86 {
88#define X86_VENDOR_UMC 3 88#define X86_VENDOR_UMC 3
89#define X86_VENDOR_NEXGEN 4 89#define X86_VENDOR_NEXGEN 4
90#define X86_VENDOR_CENTAUR 5 90#define X86_VENDOR_CENTAUR 5
91#define X86_VENDOR_RISE 6
92#define X86_VENDOR_TRANSMETA 7 91#define X86_VENDOR_TRANSMETA 7
93#define X86_VENDOR_NSC 8 92#define X86_VENDOR_NSC 8
94#define X86_VENDOR_NUM 9 93#define X86_VENDOR_NUM 9
diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h
index efc87a5aff7f..a1645bbc03bd 100644
--- a/include/asm-x86_64/processor.h
+++ b/include/asm-x86_64/processor.h
@@ -83,7 +83,6 @@ struct cpuinfo_x86 {
83#define X86_VENDOR_UMC 3 83#define X86_VENDOR_UMC 3
84#define X86_VENDOR_NEXGEN 4 84#define X86_VENDOR_NEXGEN 4
85#define X86_VENDOR_CENTAUR 5 85#define X86_VENDOR_CENTAUR 5
86#define X86_VENDOR_RISE 6
87#define X86_VENDOR_TRANSMETA 7 86#define X86_VENDOR_TRANSMETA 7
88#define X86_VENDOR_NUM 8 87#define X86_VENDOR_NUM 8
89#define X86_VENDOR_UNKNOWN 0xff 88#define X86_VENDOR_UNKNOWN 0xff