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authorMark Brown <broonie@opensource.wolfsonmicro.com>2009-07-10 18:12:01 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2009-08-03 11:59:16 -0400
commit8d50e447d19fec64adebeef55f2b60d695435412 (patch)
treeaac4234db113cf40abc4c7779ddecb76d7e0946b
parentafa2f1066e7288a9e4f8e3fda277da245219dffc (diff)
ASoC: Factor out I/O for Wolfson 8 bit data 16 bit register CODECs
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat
-rw-r--r--sound/soc/codecs/wm8523.c98
-rw-r--r--sound/soc/codecs/wm8900.c319
-rw-r--r--sound/soc/codecs/wm8903.c244
-rw-r--r--sound/soc/codecs/wm8940.c143
-rw-r--r--sound/soc/codecs/wm8961.c231
-rw-r--r--sound/soc/codecs/wm8990.c194
-rw-r--r--sound/soc/codecs/wm9081.c229
7 files changed, 521 insertions, 937 deletions
diff --git a/sound/soc/codecs/wm8523.c b/sound/soc/codecs/wm8523.c
index 3b499ae7ce6c..25870a4652fb 100644
--- a/sound/soc/codecs/wm8523.c
+++ b/sound/soc/codecs/wm8523.c
@@ -62,7 +62,7 @@ static const u16 wm8523_reg[WM8523_REGISTER_COUNT] = {
62 0x0000, /* R8 - ZERO_DETECT */ 62 0x0000, /* R8 - ZERO_DETECT */
63}; 63};
64 64
65static int wm8523_volatile(unsigned int reg) 65static int wm8523_volatile_register(unsigned int reg)
66{ 66{
67 switch (reg) { 67 switch (reg) {
68 case WM8523_DEVICE_ID: 68 case WM8523_DEVICE_ID:
@@ -73,71 +73,9 @@ static int wm8523_volatile(unsigned int reg)
73 } 73 }
74} 74}
75 75
76static int wm8523_write(struct snd_soc_codec *codec, unsigned int reg,
77 unsigned int value)
78{
79 struct wm8523_priv *wm8523 = codec->private_data;
80 u8 data[3];
81
82 BUG_ON(reg > WM8523_MAX_REGISTER);
83
84 data[0] = reg;
85 data[1] = (value >> 8) & 0x00ff;
86 data[2] = value & 0x00ff;
87
88 if (!wm8523_volatile(reg))
89 wm8523->reg_cache[reg] = value;
90 if (codec->hw_write(codec->control_data, data, 3) == 3)
91 return 0;
92 else
93 return -EIO;
94}
95
96static int wm8523_reset(struct snd_soc_codec *codec) 76static int wm8523_reset(struct snd_soc_codec *codec)
97{ 77{
98 return wm8523_write(codec, WM8523_DEVICE_ID, 0); 78 return snd_soc_write(codec, WM8523_DEVICE_ID, 0);
99}
100
101static unsigned int wm8523_read_hw(struct snd_soc_codec *codec, u8 reg)
102{
103 struct i2c_msg xfer[2];
104 u16 data;
105 int ret;
106 struct i2c_client *i2c = codec->control_data;
107
108 /* Write register */
109 xfer[0].addr = i2c->addr;
110 xfer[0].flags = 0;
111 xfer[0].len = 1;
112 xfer[0].buf = &reg;
113
114 /* Read data */
115 xfer[1].addr = i2c->addr;
116 xfer[1].flags = I2C_M_RD;
117 xfer[1].len = 2;
118 xfer[1].buf = (u8 *)&data;
119
120 ret = i2c_transfer(i2c->adapter, xfer, 2);
121 if (ret != 2) {
122 dev_err(codec->dev, "Failed to read 0x%x: %d\n", reg, ret);
123 return 0;
124 }
125
126 return (data >> 8) | ((data & 0xff) << 8);
127}
128
129
130static unsigned int wm8523_read(struct snd_soc_codec *codec,
131 unsigned int reg)
132{
133 u16 *reg_cache = codec->reg_cache;
134
135 BUG_ON(reg > WM8523_MAX_REGISTER);
136
137 if (wm8523_volatile(reg))
138 return wm8523_read_hw(codec, reg);
139 else
140 return reg_cache[reg];
141} 79}
142 80
143static const DECLARE_TLV_DB_SCALE(dac_tlv, -10000, 25, 0); 81static const DECLARE_TLV_DB_SCALE(dac_tlv, -10000, 25, 0);
@@ -228,8 +166,8 @@ static int wm8523_hw_params(struct snd_pcm_substream *substream,
228 struct snd_soc_codec *codec = socdev->card->codec; 166 struct snd_soc_codec *codec = socdev->card->codec;
229 struct wm8523_priv *wm8523 = codec->private_data; 167 struct wm8523_priv *wm8523 = codec->private_data;
230 int i; 168 int i;
231 u16 aifctrl1 = wm8523_read(codec, WM8523_AIF_CTRL1); 169 u16 aifctrl1 = snd_soc_read(codec, WM8523_AIF_CTRL1);
232 u16 aifctrl2 = wm8523_read(codec, WM8523_AIF_CTRL2); 170 u16 aifctrl2 = snd_soc_read(codec, WM8523_AIF_CTRL2);
233 171
234 /* Find a supported LRCLK ratio */ 172 /* Find a supported LRCLK ratio */
235 for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) { 173 for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
@@ -263,8 +201,8 @@ static int wm8523_hw_params(struct snd_pcm_substream *substream,
263 break; 201 break;
264 } 202 }
265 203
266 wm8523_write(codec, WM8523_AIF_CTRL1, aifctrl1); 204 snd_soc_write(codec, WM8523_AIF_CTRL1, aifctrl1);
267 wm8523_write(codec, WM8523_AIF_CTRL2, aifctrl2); 205 snd_soc_write(codec, WM8523_AIF_CTRL2, aifctrl2);
268 206
269 return 0; 207 return 0;
270} 208}
@@ -322,7 +260,7 @@ static int wm8523_set_dai_fmt(struct snd_soc_dai *codec_dai,
322 unsigned int fmt) 260 unsigned int fmt)
323{ 261{
324 struct snd_soc_codec *codec = codec_dai->codec; 262 struct snd_soc_codec *codec = codec_dai->codec;
325 u16 aifctrl1 = wm8523_read(codec, WM8523_AIF_CTRL1); 263 u16 aifctrl1 = snd_soc_read(codec, WM8523_AIF_CTRL1);
326 264
327 aifctrl1 &= ~(WM8523_BCLK_INV_MASK | WM8523_LRCLK_INV_MASK | 265 aifctrl1 &= ~(WM8523_BCLK_INV_MASK | WM8523_LRCLK_INV_MASK |
328 WM8523_FMT_MASK | WM8523_AIF_MSTR_MASK); 266 WM8523_FMT_MASK | WM8523_AIF_MSTR_MASK);
@@ -372,7 +310,7 @@ static int wm8523_set_dai_fmt(struct snd_soc_dai *codec_dai,
372 return -EINVAL; 310 return -EINVAL;
373 } 311 }
374 312
375 wm8523_write(codec, WM8523_AIF_CTRL1, aifctrl1); 313 snd_soc_write(codec, WM8523_AIF_CTRL1, aifctrl1);
376 314
377 return 0; 315 return 0;
378} 316}
@@ -411,7 +349,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec,
411 /* Sync back default/cached values */ 349 /* Sync back default/cached values */
412 for (i = WM8523_AIF_CTRL1; 350 for (i = WM8523_AIF_CTRL1;
413 i < WM8523_MAX_REGISTER; i++) 351 i < WM8523_MAX_REGISTER; i++)
414 wm8523_write(codec, i, wm8523->reg_cache[i]); 352 snd_soc_write(codec, i, wm8523->reg_cache[i]);
415 353
416 354
417 msleep(100); 355 msleep(100);
@@ -543,7 +481,8 @@ struct snd_soc_codec_device soc_codec_dev_wm8523 = {
543}; 481};
544EXPORT_SYMBOL_GPL(soc_codec_dev_wm8523); 482EXPORT_SYMBOL_GPL(soc_codec_dev_wm8523);
545 483
546static int wm8523_register(struct wm8523_priv *wm8523) 484static int wm8523_register(struct wm8523_priv *wm8523,
485 enum snd_soc_control_type control)
547{ 486{
548 int ret; 487 int ret;
549 struct snd_soc_codec *codec = &wm8523->codec; 488 struct snd_soc_codec *codec = &wm8523->codec;
@@ -561,14 +500,13 @@ static int wm8523_register(struct wm8523_priv *wm8523)
561 codec->private_data = wm8523; 500 codec->private_data = wm8523;
562 codec->name = "WM8523"; 501 codec->name = "WM8523";
563 codec->owner = THIS_MODULE; 502 codec->owner = THIS_MODULE;
564 codec->read = wm8523_read;
565 codec->write = wm8523_write;
566 codec->bias_level = SND_SOC_BIAS_OFF; 503 codec->bias_level = SND_SOC_BIAS_OFF;
567 codec->set_bias_level = wm8523_set_bias_level; 504 codec->set_bias_level = wm8523_set_bias_level;
568 codec->dai = &wm8523_dai; 505 codec->dai = &wm8523_dai;
569 codec->num_dai = 1; 506 codec->num_dai = 1;
570 codec->reg_cache_size = WM8523_REGISTER_COUNT; 507 codec->reg_cache_size = WM8523_REGISTER_COUNT;
571 codec->reg_cache = &wm8523->reg_cache; 508 codec->reg_cache = &wm8523->reg_cache;
509 codec->volatile_register = wm8523_volatile_register;
572 510
573 wm8523->rate_constraint.list = &wm8523->rate_constraint_list[0]; 511 wm8523->rate_constraint.list = &wm8523->rate_constraint_list[0];
574 wm8523->rate_constraint.count = 512 wm8523->rate_constraint.count =
@@ -576,6 +514,12 @@ static int wm8523_register(struct wm8523_priv *wm8523)
576 514
577 memcpy(codec->reg_cache, wm8523_reg, sizeof(wm8523_reg)); 515 memcpy(codec->reg_cache, wm8523_reg, sizeof(wm8523_reg));
578 516
517 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
518 if (ret != 0) {
519 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
520 goto err;
521 }
522
579 for (i = 0; i < ARRAY_SIZE(wm8523->supplies); i++) 523 for (i = 0; i < ARRAY_SIZE(wm8523->supplies); i++)
580 wm8523->supplies[i].supply = wm8523_supply_names[i]; 524 wm8523->supplies[i].supply = wm8523_supply_names[i];
581 525
@@ -593,7 +537,7 @@ static int wm8523_register(struct wm8523_priv *wm8523)
593 goto err_get; 537 goto err_get;
594 } 538 }
595 539
596 ret = wm8523_read(codec, WM8523_DEVICE_ID); 540 ret = snd_soc_read(codec, WM8523_DEVICE_ID);
597 if (ret < 0) { 541 if (ret < 0) {
598 dev_err(codec->dev, "Failed to read ID register\n"); 542 dev_err(codec->dev, "Failed to read ID register\n");
599 goto err_enable; 543 goto err_enable;
@@ -604,7 +548,7 @@ static int wm8523_register(struct wm8523_priv *wm8523)
604 goto err_enable; 548 goto err_enable;
605 } 549 }
606 550
607 ret = wm8523_read(codec, WM8523_REVISION); 551 ret = snd_soc_read(codec, WM8523_REVISION);
608 if (ret < 0) { 552 if (ret < 0) {
609 dev_err(codec->dev, "Failed to read revision register\n"); 553 dev_err(codec->dev, "Failed to read revision register\n");
610 goto err_enable; 554 goto err_enable;
@@ -684,7 +628,7 @@ static __devinit int wm8523_i2c_probe(struct i2c_client *i2c,
684 628
685 codec->dev = &i2c->dev; 629 codec->dev = &i2c->dev;
686 630
687 return wm8523_register(wm8523); 631 return wm8523_register(wm8523, SND_SOC_I2C);
688} 632}
689 633
690static __devexit int wm8523_i2c_remove(struct i2c_client *client) 634static __devexit int wm8523_i2c_remove(struct i2c_client *client)
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c
index ac308993ac5a..5e9c855c0036 100644
--- a/sound/soc/codecs/wm8900.c
+++ b/sound/soc/codecs/wm8900.c
@@ -183,111 +183,20 @@ static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
183 /* Remaining registers all zero */ 183 /* Remaining registers all zero */
184}; 184};
185 185
186/* 186static int wm8900_volatile_register(unsigned int reg)
187 * read wm8900 register cache
188 */
189static inline unsigned int wm8900_read_reg_cache(struct snd_soc_codec *codec,
190 unsigned int reg)
191{
192 u16 *cache = codec->reg_cache;
193
194 BUG_ON(reg >= WM8900_MAXREG);
195
196 if (reg == WM8900_REG_ID)
197 return 0;
198
199 return cache[reg];
200}
201
202/*
203 * write wm8900 register cache
204 */
205static inline void wm8900_write_reg_cache(struct snd_soc_codec *codec,
206 u16 reg, unsigned int value)
207{
208 u16 *cache = codec->reg_cache;
209
210 BUG_ON(reg >= WM8900_MAXREG);
211
212 cache[reg] = value;
213}
214
215/*
216 * write to the WM8900 register space
217 */
218static int wm8900_write(struct snd_soc_codec *codec, unsigned int reg,
219 unsigned int value)
220{
221 u8 data[3];
222
223 if (value == wm8900_read_reg_cache(codec, reg))
224 return 0;
225
226 /* data is
227 * D15..D9 WM8900 register offset
228 * D8...D0 register data
229 */
230 data[0] = reg;
231 data[1] = value >> 8;
232 data[2] = value & 0x00ff;
233
234 wm8900_write_reg_cache(codec, reg, value);
235 if (codec->hw_write(codec->control_data, data, 3) == 3)
236 return 0;
237 else
238 return -EIO;
239}
240
241/*
242 * Read from the wm8900.
243 */
244static unsigned int wm8900_chip_read(struct snd_soc_codec *codec, u8 reg)
245{
246 struct i2c_msg xfer[2];
247 u16 data;
248 int ret;
249 struct i2c_client *client = codec->control_data;
250
251 BUG_ON(reg != WM8900_REG_ID && reg != WM8900_REG_POWER1);
252
253 /* Write register */
254 xfer[0].addr = client->addr;
255 xfer[0].flags = 0;
256 xfer[0].len = 1;
257 xfer[0].buf = &reg;
258
259 /* Read data */
260 xfer[1].addr = client->addr;
261 xfer[1].flags = I2C_M_RD;
262 xfer[1].len = 2;
263 xfer[1].buf = (u8 *)&data;
264
265 ret = i2c_transfer(client->adapter, xfer, 2);
266 if (ret != 2) {
267 printk(KERN_CRIT "i2c_transfer returned %d\n", ret);
268 return 0;
269 }
270
271 return (data >> 8) | ((data & 0xff) << 8);
272}
273
274/*
275 * Read from the WM8900 register space. Most registers can't be read
276 * and are therefore supplied from cache.
277 */
278static unsigned int wm8900_read(struct snd_soc_codec *codec, unsigned int reg)
279{ 187{
280 switch (reg) { 188 switch (reg) {
281 case WM8900_REG_ID: 189 case WM8900_REG_ID:
282 return wm8900_chip_read(codec, reg); 190 case WM8900_REG_POWER1:
191 return 1;
283 default: 192 default:
284 return wm8900_read_reg_cache(codec, reg); 193 return 0;
285 } 194 }
286} 195}
287 196
288static void wm8900_reset(struct snd_soc_codec *codec) 197static void wm8900_reset(struct snd_soc_codec *codec)
289{ 198{
290 wm8900_write(codec, WM8900_REG_RESET, 0); 199 snd_soc_write(codec, WM8900_REG_RESET, 0);
291 200
292 memcpy(codec->reg_cache, wm8900_reg_defaults, 201 memcpy(codec->reg_cache, wm8900_reg_defaults,
293 sizeof(codec->reg_cache)); 202 sizeof(codec->reg_cache));
@@ -297,14 +206,14 @@ static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
297 struct snd_kcontrol *kcontrol, int event) 206 struct snd_kcontrol *kcontrol, int event)
298{ 207{
299 struct snd_soc_codec *codec = w->codec; 208 struct snd_soc_codec *codec = w->codec;
300 u16 hpctl1 = wm8900_read(codec, WM8900_REG_HPCTL1); 209 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
301 210
302 switch (event) { 211 switch (event) {
303 case SND_SOC_DAPM_PRE_PMU: 212 case SND_SOC_DAPM_PRE_PMU:
304 /* Clamp headphone outputs */ 213 /* Clamp headphone outputs */
305 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP | 214 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
306 WM8900_REG_HPCTL1_HP_CLAMP_OP; 215 WM8900_REG_HPCTL1_HP_CLAMP_OP;
307 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 216 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
308 break; 217 break;
309 218
310 case SND_SOC_DAPM_POST_PMU: 219 case SND_SOC_DAPM_POST_PMU:
@@ -313,41 +222,41 @@ static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
313 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT | 222 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
314 WM8900_REG_HPCTL1_HP_SHORT2 | 223 WM8900_REG_HPCTL1_HP_SHORT2 |
315 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; 224 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
316 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 225 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
317 226
318 msleep(400); 227 msleep(400);
319 228
320 /* Enable the output stage */ 229 /* Enable the output stage */
321 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP; 230 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
322 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; 231 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
323 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 232 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
324 233
325 /* Remove the shorts */ 234 /* Remove the shorts */
326 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2; 235 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
327 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 236 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
328 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT; 237 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
329 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 238 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
330 break; 239 break;
331 240
332 case SND_SOC_DAPM_PRE_PMD: 241 case SND_SOC_DAPM_PRE_PMD:
333 /* Short the output */ 242 /* Short the output */
334 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT; 243 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
335 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 244 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
336 245
337 /* Disable the output stage */ 246 /* Disable the output stage */
338 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; 247 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
339 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 248 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
340 249
341 /* Clamp the outputs and power down input */ 250 /* Clamp the outputs and power down input */
342 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP | 251 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
343 WM8900_REG_HPCTL1_HP_CLAMP_OP; 252 WM8900_REG_HPCTL1_HP_CLAMP_OP;
344 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; 253 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
345 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 254 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
346 break; 255 break;
347 256
348 case SND_SOC_DAPM_POST_PMD: 257 case SND_SOC_DAPM_POST_PMD:
349 /* Disable everything */ 258 /* Disable everything */
350 wm8900_write(codec, WM8900_REG_HPCTL1, 0); 259 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
351 break; 260 break;
352 261
353 default: 262 default:
@@ -723,7 +632,7 @@ static int wm8900_hw_params(struct snd_pcm_substream *substream,
723 struct snd_soc_codec *codec = socdev->card->codec; 632 struct snd_soc_codec *codec = socdev->card->codec;
724 u16 reg; 633 u16 reg;
725 634
726 reg = wm8900_read(codec, WM8900_REG_AUDIO1) & ~0x60; 635 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
727 636
728 switch (params_format(params)) { 637 switch (params_format(params)) {
729 case SNDRV_PCM_FORMAT_S16_LE: 638 case SNDRV_PCM_FORMAT_S16_LE:
@@ -741,17 +650,17 @@ static int wm8900_hw_params(struct snd_pcm_substream *substream,
741 return -EINVAL; 650 return -EINVAL;
742 } 651 }
743 652
744 wm8900_write(codec, WM8900_REG_AUDIO1, reg); 653 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
745 654
746 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
747 reg = wm8900_read(codec, WM8900_REG_DACCTRL); 656 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
748 657
749 if (params_rate(params) <= 24000) 658 if (params_rate(params) <= 24000)
750 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT; 659 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
751 else 660 else
752 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT; 661 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
753 662
754 wm8900_write(codec, WM8900_REG_DACCTRL, reg); 663 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
755 } 664 }
756 665
757 return 0; 666 return 0;
@@ -845,18 +754,18 @@ static int wm8900_set_fll(struct snd_soc_codec *codec,
845 return 0; 754 return 0;
846 755
847 /* The digital side should be disabled during any change. */ 756 /* The digital side should be disabled during any change. */
848 reg = wm8900_read(codec, WM8900_REG_POWER1); 757 reg = snd_soc_read(codec, WM8900_REG_POWER1);
849 wm8900_write(codec, WM8900_REG_POWER1, 758 snd_soc_write(codec, WM8900_REG_POWER1,
850 reg & (~WM8900_REG_POWER1_FLL_ENA)); 759 reg & (~WM8900_REG_POWER1_FLL_ENA));
851 760
852 /* Disable the FLL? */ 761 /* Disable the FLL? */
853 if (!freq_in || !freq_out) { 762 if (!freq_in || !freq_out) {
854 reg = wm8900_read(codec, WM8900_REG_CLOCKING1); 763 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
855 wm8900_write(codec, WM8900_REG_CLOCKING1, 764 snd_soc_write(codec, WM8900_REG_CLOCKING1,
856 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC)); 765 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
857 766
858 reg = wm8900_read(codec, WM8900_REG_FLLCTL1); 767 reg = snd_soc_read(codec, WM8900_REG_FLLCTL1);
859 wm8900_write(codec, WM8900_REG_FLLCTL1, 768 snd_soc_write(codec, WM8900_REG_FLLCTL1,
860 reg & (~WM8900_REG_FLLCTL1_OSC_ENA)); 769 reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
861 770
862 wm8900->fll_in = freq_in; 771 wm8900->fll_in = freq_in;
@@ -873,33 +782,33 @@ static int wm8900_set_fll(struct snd_soc_codec *codec,
873 782
874 /* The osclilator *MUST* be enabled before we enable the 783 /* The osclilator *MUST* be enabled before we enable the
875 * digital circuit. */ 784 * digital circuit. */
876 wm8900_write(codec, WM8900_REG_FLLCTL1, 785 snd_soc_write(codec, WM8900_REG_FLLCTL1,
877 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA); 786 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
878 787
879 wm8900_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5); 788 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
880 wm8900_write(codec, WM8900_REG_FLLCTL5, 789 snd_soc_write(codec, WM8900_REG_FLLCTL5,
881 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f)); 790 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
882 791
883 if (fll_div.k) { 792 if (fll_div.k) {
884 wm8900_write(codec, WM8900_REG_FLLCTL2, 793 snd_soc_write(codec, WM8900_REG_FLLCTL2,
885 (fll_div.k >> 8) | 0x100); 794 (fll_div.k >> 8) | 0x100);
886 wm8900_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff); 795 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
887 } else 796 } else
888 wm8900_write(codec, WM8900_REG_FLLCTL2, 0); 797 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
889 798
890 if (fll_div.fll_slow_lock_ref) 799 if (fll_div.fll_slow_lock_ref)
891 wm8900_write(codec, WM8900_REG_FLLCTL6, 800 snd_soc_write(codec, WM8900_REG_FLLCTL6,
892 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF); 801 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
893 else 802 else
894 wm8900_write(codec, WM8900_REG_FLLCTL6, 0); 803 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
895 804
896 reg = wm8900_read(codec, WM8900_REG_POWER1); 805 reg = snd_soc_read(codec, WM8900_REG_POWER1);
897 wm8900_write(codec, WM8900_REG_POWER1, 806 snd_soc_write(codec, WM8900_REG_POWER1,
898 reg | WM8900_REG_POWER1_FLL_ENA); 807 reg | WM8900_REG_POWER1_FLL_ENA);
899 808
900reenable: 809reenable:
901 reg = wm8900_read(codec, WM8900_REG_CLOCKING1); 810 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
902 wm8900_write(codec, WM8900_REG_CLOCKING1, 811 snd_soc_write(codec, WM8900_REG_CLOCKING1,
903 reg | WM8900_REG_CLOCKING1_MCLK_SRC); 812 reg | WM8900_REG_CLOCKING1_MCLK_SRC);
904 813
905 return 0; 814 return 0;
@@ -919,38 +828,38 @@ static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
919 828
920 switch (div_id) { 829 switch (div_id) {
921 case WM8900_BCLK_DIV: 830 case WM8900_BCLK_DIV:
922 reg = wm8900_read(codec, WM8900_REG_CLOCKING1); 831 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
923 wm8900_write(codec, WM8900_REG_CLOCKING1, 832 snd_soc_write(codec, WM8900_REG_CLOCKING1,
924 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK)); 833 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
925 break; 834 break;
926 case WM8900_OPCLK_DIV: 835 case WM8900_OPCLK_DIV:
927 reg = wm8900_read(codec, WM8900_REG_CLOCKING1); 836 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
928 wm8900_write(codec, WM8900_REG_CLOCKING1, 837 snd_soc_write(codec, WM8900_REG_CLOCKING1,
929 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK)); 838 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
930 break; 839 break;
931 case WM8900_DAC_LRCLK: 840 case WM8900_DAC_LRCLK:
932 reg = wm8900_read(codec, WM8900_REG_AUDIO4); 841 reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
933 wm8900_write(codec, WM8900_REG_AUDIO4, 842 snd_soc_write(codec, WM8900_REG_AUDIO4,
934 div | (reg & WM8900_LRC_MASK)); 843 div | (reg & WM8900_LRC_MASK));
935 break; 844 break;
936 case WM8900_ADC_LRCLK: 845 case WM8900_ADC_LRCLK:
937 reg = wm8900_read(codec, WM8900_REG_AUDIO3); 846 reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
938 wm8900_write(codec, WM8900_REG_AUDIO3, 847 snd_soc_write(codec, WM8900_REG_AUDIO3,
939 div | (reg & WM8900_LRC_MASK)); 848 div | (reg & WM8900_LRC_MASK));
940 break; 849 break;
941 case WM8900_DAC_CLKDIV: 850 case WM8900_DAC_CLKDIV:
942 reg = wm8900_read(codec, WM8900_REG_CLOCKING2); 851 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
943 wm8900_write(codec, WM8900_REG_CLOCKING2, 852 snd_soc_write(codec, WM8900_REG_CLOCKING2,
944 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV)); 853 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
945 break; 854 break;
946 case WM8900_ADC_CLKDIV: 855 case WM8900_ADC_CLKDIV:
947 reg = wm8900_read(codec, WM8900_REG_CLOCKING2); 856 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
948 wm8900_write(codec, WM8900_REG_CLOCKING2, 857 snd_soc_write(codec, WM8900_REG_CLOCKING2,
949 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV)); 858 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
950 break; 859 break;
951 case WM8900_LRCLK_MODE: 860 case WM8900_LRCLK_MODE:
952 reg = wm8900_read(codec, WM8900_REG_DACCTRL); 861 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
953 wm8900_write(codec, WM8900_REG_DACCTRL, 862 snd_soc_write(codec, WM8900_REG_DACCTRL,
954 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE)); 863 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
955 break; 864 break;
956 default: 865 default:
@@ -967,10 +876,10 @@ static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
967 struct snd_soc_codec *codec = codec_dai->codec; 876 struct snd_soc_codec *codec = codec_dai->codec;
968 unsigned int clocking1, aif1, aif3, aif4; 877 unsigned int clocking1, aif1, aif3, aif4;
969 878
970 clocking1 = wm8900_read(codec, WM8900_REG_CLOCKING1); 879 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
971 aif1 = wm8900_read(codec, WM8900_REG_AUDIO1); 880 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
972 aif3 = wm8900_read(codec, WM8900_REG_AUDIO3); 881 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
973 aif4 = wm8900_read(codec, WM8900_REG_AUDIO4); 882 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
974 883
975 /* set master/slave audio interface */ 884 /* set master/slave audio interface */
976 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 885 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -1066,10 +975,10 @@ static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
1066 return -EINVAL; 975 return -EINVAL;
1067 } 976 }
1068 977
1069 wm8900_write(codec, WM8900_REG_CLOCKING1, clocking1); 978 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
1070 wm8900_write(codec, WM8900_REG_AUDIO1, aif1); 979 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
1071 wm8900_write(codec, WM8900_REG_AUDIO3, aif3); 980 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
1072 wm8900_write(codec, WM8900_REG_AUDIO4, aif4); 981 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
1073 982
1074 return 0; 983 return 0;
1075} 984}
@@ -1079,14 +988,14 @@ static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1079 struct snd_soc_codec *codec = codec_dai->codec; 988 struct snd_soc_codec *codec = codec_dai->codec;
1080 u16 reg; 989 u16 reg;
1081 990
1082 reg = wm8900_read(codec, WM8900_REG_DACCTRL); 991 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
1083 992
1084 if (mute) 993 if (mute)
1085 reg |= WM8900_REG_DACCTRL_MUTE; 994 reg |= WM8900_REG_DACCTRL_MUTE;
1086 else 995 else
1087 reg &= ~WM8900_REG_DACCTRL_MUTE; 996 reg &= ~WM8900_REG_DACCTRL_MUTE;
1088 997
1089 wm8900_write(codec, WM8900_REG_DACCTRL, reg); 998 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
1090 999
1091 return 0; 1000 return 0;
1092} 1001}
@@ -1135,11 +1044,11 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1135 switch (level) { 1044 switch (level) {
1136 case SND_SOC_BIAS_ON: 1045 case SND_SOC_BIAS_ON:
1137 /* Enable thermal shutdown */ 1046 /* Enable thermal shutdown */
1138 reg = wm8900_read(codec, WM8900_REG_GPIO); 1047 reg = snd_soc_read(codec, WM8900_REG_GPIO);
1139 wm8900_write(codec, WM8900_REG_GPIO, 1048 snd_soc_write(codec, WM8900_REG_GPIO,
1140 reg | WM8900_REG_GPIO_TEMP_ENA); 1049 reg | WM8900_REG_GPIO_TEMP_ENA);
1141 reg = wm8900_read(codec, WM8900_REG_ADDCTL); 1050 reg = snd_soc_read(codec, WM8900_REG_ADDCTL);
1142 wm8900_write(codec, WM8900_REG_ADDCTL, 1051 snd_soc_write(codec, WM8900_REG_ADDCTL,
1143 reg | WM8900_REG_ADDCTL_TEMP_SD); 1052 reg | WM8900_REG_ADDCTL_TEMP_SD);
1144 break; 1053 break;
1145 1054
@@ -1150,69 +1059,69 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1150 /* Charge capacitors if initial power up */ 1059 /* Charge capacitors if initial power up */
1151 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1060 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1152 /* STARTUP_BIAS_ENA on */ 1061 /* STARTUP_BIAS_ENA on */
1153 wm8900_write(codec, WM8900_REG_POWER1, 1062 snd_soc_write(codec, WM8900_REG_POWER1,
1154 WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1063 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1155 1064
1156 /* Startup bias mode */ 1065 /* Startup bias mode */
1157 wm8900_write(codec, WM8900_REG_ADDCTL, 1066 snd_soc_write(codec, WM8900_REG_ADDCTL,
1158 WM8900_REG_ADDCTL_BIAS_SRC | 1067 WM8900_REG_ADDCTL_BIAS_SRC |
1159 WM8900_REG_ADDCTL_VMID_SOFTST); 1068 WM8900_REG_ADDCTL_VMID_SOFTST);
1160 1069
1161 /* VMID 2x50k */ 1070 /* VMID 2x50k */
1162 wm8900_write(codec, WM8900_REG_POWER1, 1071 snd_soc_write(codec, WM8900_REG_POWER1,
1163 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1); 1072 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1164 1073
1165 /* Allow capacitors to charge */ 1074 /* Allow capacitors to charge */
1166 schedule_timeout_interruptible(msecs_to_jiffies(400)); 1075 schedule_timeout_interruptible(msecs_to_jiffies(400));
1167 1076
1168 /* Enable bias */ 1077 /* Enable bias */
1169 wm8900_write(codec, WM8900_REG_POWER1, 1078 snd_soc_write(codec, WM8900_REG_POWER1,
1170 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 1079 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1171 WM8900_REG_POWER1_BIAS_ENA | 0x1); 1080 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1172 1081
1173 wm8900_write(codec, WM8900_REG_ADDCTL, 0); 1082 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1174 1083
1175 wm8900_write(codec, WM8900_REG_POWER1, 1084 snd_soc_write(codec, WM8900_REG_POWER1,
1176 WM8900_REG_POWER1_BIAS_ENA | 0x1); 1085 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1177 } 1086 }
1178 1087
1179 reg = wm8900_read(codec, WM8900_REG_POWER1); 1088 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1180 wm8900_write(codec, WM8900_REG_POWER1, 1089 snd_soc_write(codec, WM8900_REG_POWER1,
1181 (reg & WM8900_REG_POWER1_FLL_ENA) | 1090 (reg & WM8900_REG_POWER1_FLL_ENA) |
1182 WM8900_REG_POWER1_BIAS_ENA | 0x1); 1091 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1183 wm8900_write(codec, WM8900_REG_POWER2, 1092 snd_soc_write(codec, WM8900_REG_POWER2,
1184 WM8900_REG_POWER2_SYSCLK_ENA); 1093 WM8900_REG_POWER2_SYSCLK_ENA);
1185 wm8900_write(codec, WM8900_REG_POWER3, 0); 1094 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1186 break; 1095 break;
1187 1096
1188 case SND_SOC_BIAS_OFF: 1097 case SND_SOC_BIAS_OFF:
1189 /* Startup bias enable */ 1098 /* Startup bias enable */
1190 reg = wm8900_read(codec, WM8900_REG_POWER1); 1099 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1191 wm8900_write(codec, WM8900_REG_POWER1, 1100 snd_soc_write(codec, WM8900_REG_POWER1,
1192 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1101 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1193 wm8900_write(codec, WM8900_REG_ADDCTL, 1102 snd_soc_write(codec, WM8900_REG_ADDCTL,
1194 WM8900_REG_ADDCTL_BIAS_SRC | 1103 WM8900_REG_ADDCTL_BIAS_SRC |
1195 WM8900_REG_ADDCTL_VMID_SOFTST); 1104 WM8900_REG_ADDCTL_VMID_SOFTST);
1196 1105
1197 /* Discharge caps */ 1106 /* Discharge caps */
1198 wm8900_write(codec, WM8900_REG_POWER1, 1107 snd_soc_write(codec, WM8900_REG_POWER1,
1199 WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1108 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1200 schedule_timeout_interruptible(msecs_to_jiffies(500)); 1109 schedule_timeout_interruptible(msecs_to_jiffies(500));
1201 1110
1202 /* Remove clamp */ 1111 /* Remove clamp */
1203 wm8900_write(codec, WM8900_REG_HPCTL1, 0); 1112 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
1204 1113
1205 /* Power down */ 1114 /* Power down */
1206 wm8900_write(codec, WM8900_REG_ADDCTL, 0); 1115 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1207 wm8900_write(codec, WM8900_REG_POWER1, 0); 1116 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1208 wm8900_write(codec, WM8900_REG_POWER2, 0); 1117 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1209 wm8900_write(codec, WM8900_REG_POWER3, 0); 1118 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1210 1119
1211 /* Need to let things settle before stopping the clock 1120 /* Need to let things settle before stopping the clock
1212 * to ensure that restart works, see "Stopping the 1121 * to ensure that restart works, see "Stopping the
1213 * master clock" in the datasheet. */ 1122 * master clock" in the datasheet. */
1214 schedule_timeout_interruptible(msecs_to_jiffies(1)); 1123 schedule_timeout_interruptible(msecs_to_jiffies(1));
1215 wm8900_write(codec, WM8900_REG_POWER2, 1124 snd_soc_write(codec, WM8900_REG_POWER2,
1216 WM8900_REG_POWER2_SYSCLK_ENA); 1125 WM8900_REG_POWER2_SYSCLK_ENA);
1217 break; 1126 break;
1218 } 1127 }
@@ -1275,7 +1184,7 @@ static int wm8900_resume(struct platform_device *pdev)
1275 1184
1276 if (cache) { 1185 if (cache) {
1277 for (i = 0; i < WM8900_MAXREG; i++) 1186 for (i = 0; i < WM8900_MAXREG; i++)
1278 wm8900_write(codec, i, cache[i]); 1187 snd_soc_write(codec, i, cache[i]);
1279 kfree(cache); 1188 kfree(cache);
1280 } else 1189 } else
1281 dev_err(&pdev->dev, "Unable to allocate register cache\n"); 1190 dev_err(&pdev->dev, "Unable to allocate register cache\n");
@@ -1308,16 +1217,20 @@ static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1308 1217
1309 codec->name = "WM8900"; 1218 codec->name = "WM8900";
1310 codec->owner = THIS_MODULE; 1219 codec->owner = THIS_MODULE;
1311 codec->read = wm8900_read;
1312 codec->write = wm8900_write;
1313 codec->dai = &wm8900_dai; 1220 codec->dai = &wm8900_dai;
1314 codec->num_dai = 1; 1221 codec->num_dai = 1;
1315 codec->hw_write = (hw_write_t)i2c_master_send;
1316 codec->control_data = i2c; 1222 codec->control_data = i2c;
1317 codec->set_bias_level = wm8900_set_bias_level; 1223 codec->set_bias_level = wm8900_set_bias_level;
1224 codec->volatile_register = wm8900_volatile_register;
1318 codec->dev = &i2c->dev; 1225 codec->dev = &i2c->dev;
1319 1226
1320 reg = wm8900_read(codec, WM8900_REG_ID); 1227 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1228 if (ret != 0) {
1229 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
1230 goto err;
1231 }
1232
1233 reg = snd_soc_read(codec, WM8900_REG_ID);
1321 if (reg != 0x8900) { 1234 if (reg != 0x8900) {
1322 dev_err(&i2c->dev, "Device is not a WM8900 - ID %x\n", reg); 1235 dev_err(&i2c->dev, "Device is not a WM8900 - ID %x\n", reg);
1323 ret = -ENODEV; 1236 ret = -ENODEV;
@@ -1325,7 +1238,7 @@ static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1325 } 1238 }
1326 1239
1327 /* Read back from the chip */ 1240 /* Read back from the chip */
1328 reg = wm8900_chip_read(codec, WM8900_REG_POWER1); 1241 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1329 reg = (reg >> 12) & 0xf; 1242 reg = (reg >> 12) & 0xf;
1330 dev_info(&i2c->dev, "WM8900 revision %d\n", reg); 1243 dev_info(&i2c->dev, "WM8900 revision %d\n", reg);
1331 1244
@@ -1335,29 +1248,29 @@ static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1335 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1248 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1336 1249
1337 /* Latch the volume update bits */ 1250 /* Latch the volume update bits */
1338 wm8900_write(codec, WM8900_REG_LINVOL, 1251 snd_soc_write(codec, WM8900_REG_LINVOL,
1339 wm8900_read(codec, WM8900_REG_LINVOL) | 0x100); 1252 snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100);
1340 wm8900_write(codec, WM8900_REG_RINVOL, 1253 snd_soc_write(codec, WM8900_REG_RINVOL,
1341 wm8900_read(codec, WM8900_REG_RINVOL) | 0x100); 1254 snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100);
1342 wm8900_write(codec, WM8900_REG_LOUT1CTL, 1255 snd_soc_write(codec, WM8900_REG_LOUT1CTL,
1343 wm8900_read(codec, WM8900_REG_LOUT1CTL) | 0x100); 1256 snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1344 wm8900_write(codec, WM8900_REG_ROUT1CTL, 1257 snd_soc_write(codec, WM8900_REG_ROUT1CTL,
1345 wm8900_read(codec, WM8900_REG_ROUT1CTL) | 0x100); 1258 snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1346 wm8900_write(codec, WM8900_REG_LOUT2CTL, 1259 snd_soc_write(codec, WM8900_REG_LOUT2CTL,
1347 wm8900_read(codec, WM8900_REG_LOUT2CTL) | 0x100); 1260 snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1348 wm8900_write(codec, WM8900_REG_ROUT2CTL, 1261 snd_soc_write(codec, WM8900_REG_ROUT2CTL,
1349 wm8900_read(codec, WM8900_REG_ROUT2CTL) | 0x100); 1262 snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1350 wm8900_write(codec, WM8900_REG_LDAC_DV, 1263 snd_soc_write(codec, WM8900_REG_LDAC_DV,
1351 wm8900_read(codec, WM8900_REG_LDAC_DV) | 0x100); 1264 snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1352 wm8900_write(codec, WM8900_REG_RDAC_DV, 1265 snd_soc_write(codec, WM8900_REG_RDAC_DV,
1353 wm8900_read(codec, WM8900_REG_RDAC_DV) | 0x100); 1266 snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1354 wm8900_write(codec, WM8900_REG_LADC_DV, 1267 snd_soc_write(codec, WM8900_REG_LADC_DV,
1355 wm8900_read(codec, WM8900_REG_LADC_DV) | 0x100); 1268 snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100);
1356 wm8900_write(codec, WM8900_REG_RADC_DV, 1269 snd_soc_write(codec, WM8900_REG_RADC_DV,
1357 wm8900_read(codec, WM8900_REG_RADC_DV) | 0x100); 1270 snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100);
1358 1271
1359 /* Set the DAC and mixer output bias */ 1272 /* Set the DAC and mixer output bias */
1360 wm8900_write(codec, WM8900_REG_OUTBIASCTL, 0x81); 1273 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1361 1274
1362 wm8900_dai.dev = &i2c->dev; 1275 wm8900_dai.dev = &i2c->dev;
1363 1276
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index c9baeae3e275..fe1307b500cf 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -225,94 +225,18 @@ struct wm8903_priv {
225 struct snd_pcm_substream *slave_substream; 225 struct snd_pcm_substream *slave_substream;
226}; 226};
227 227
228 228static int wm8903_volatile_register(unsigned int reg)
229static unsigned int wm8903_read_reg_cache(struct snd_soc_codec *codec,
230 unsigned int reg)
231{
232 u16 *cache = codec->reg_cache;
233
234 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
235
236 return cache[reg];
237}
238
239static unsigned int wm8903_hw_read(struct snd_soc_codec *codec, u8 reg)
240{
241 struct i2c_msg xfer[2];
242 u16 data;
243 int ret;
244 struct i2c_client *client = codec->control_data;
245
246 /* Write register */
247 xfer[0].addr = client->addr;
248 xfer[0].flags = 0;
249 xfer[0].len = 1;
250 xfer[0].buf = &reg;
251
252 /* Read data */
253 xfer[1].addr = client->addr;
254 xfer[1].flags = I2C_M_RD;
255 xfer[1].len = 2;
256 xfer[1].buf = (u8 *)&data;
257
258 ret = i2c_transfer(client->adapter, xfer, 2);
259 if (ret != 2) {
260 pr_err("i2c_transfer returned %d\n", ret);
261 return 0;
262 }
263
264 return (data >> 8) | ((data & 0xff) << 8);
265}
266
267static unsigned int wm8903_read(struct snd_soc_codec *codec,
268 unsigned int reg)
269{ 229{
270 switch (reg) { 230 switch (reg) {
271 case WM8903_SW_RESET_AND_ID: 231 case WM8903_SW_RESET_AND_ID:
272 case WM8903_REVISION_NUMBER: 232 case WM8903_REVISION_NUMBER:
273 case WM8903_INTERRUPT_STATUS_1: 233 case WM8903_INTERRUPT_STATUS_1:
274 case WM8903_WRITE_SEQUENCER_4: 234 case WM8903_WRITE_SEQUENCER_4:
275 return wm8903_hw_read(codec, reg); 235 return 1;
276 236
277 default: 237 default:
278 return wm8903_read_reg_cache(codec, reg);
279 }
280}
281
282static void wm8903_write_reg_cache(struct snd_soc_codec *codec,
283 u16 reg, unsigned int value)
284{
285 u16 *cache = codec->reg_cache;
286
287 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
288
289 switch (reg) {
290 case WM8903_SW_RESET_AND_ID:
291 case WM8903_REVISION_NUMBER:
292 break;
293
294 default:
295 cache[reg] = value;
296 break;
297 }
298}
299
300static int wm8903_write(struct snd_soc_codec *codec, unsigned int reg,
301 unsigned int value)
302{
303 u8 data[3];
304
305 wm8903_write_reg_cache(codec, reg, value);
306
307 /* Data format is 1 byte of address followed by 2 bytes of data */
308 data[0] = reg;
309 data[1] = (value >> 8) & 0xff;
310 data[2] = value & 0xff;
311
312 if (codec->hw_write(codec->control_data, data, 3) == 2)
313 return 0; 238 return 0;
314 else 239 }
315 return -EIO;
316} 240}
317 241
318static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start) 242static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
@@ -323,13 +247,13 @@ static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
323 BUG_ON(start > 48); 247 BUG_ON(start > 48);
324 248
325 /* Enable the sequencer */ 249 /* Enable the sequencer */
326 reg[0] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_0); 250 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
327 reg[0] |= WM8903_WSEQ_ENA; 251 reg[0] |= WM8903_WSEQ_ENA;
328 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]); 252 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
329 253
330 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start); 254 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
331 255
332 wm8903_write(codec, WM8903_WRITE_SEQUENCER_3, 256 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
333 start | WM8903_WSEQ_START); 257 start | WM8903_WSEQ_START);
334 258
335 /* Wait for it to complete. If we have the interrupt wired up then 259 /* Wait for it to complete. If we have the interrupt wired up then
@@ -339,13 +263,13 @@ static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
339 do { 263 do {
340 msleep(10); 264 msleep(10);
341 265
342 reg[4] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_4); 266 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
343 } while (reg[4] & WM8903_WSEQ_BUSY); 267 } while (reg[4] & WM8903_WSEQ_BUSY);
344 268
345 dev_dbg(&i2c->dev, "Sequence complete\n"); 269 dev_dbg(&i2c->dev, "Sequence complete\n");
346 270
347 /* Disable the sequencer again */ 271 /* Disable the sequencer again */
348 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, 272 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
349 reg[0] & ~WM8903_WSEQ_ENA); 273 reg[0] & ~WM8903_WSEQ_ENA);
350 274
351 return 0; 275 return 0;
@@ -357,12 +281,12 @@ static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
357 281
358 /* There really ought to be something better we can do here :/ */ 282 /* There really ought to be something better we can do here :/ */
359 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++) 283 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
360 cache[i] = wm8903_hw_read(codec, i); 284 cache[i] = codec->hw_read(codec, i);
361} 285}
362 286
363static void wm8903_reset(struct snd_soc_codec *codec) 287static void wm8903_reset(struct snd_soc_codec *codec)
364{ 288{
365 wm8903_write(codec, WM8903_SW_RESET_AND_ID, 0); 289 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
366 memcpy(codec->reg_cache, wm8903_reg_defaults, 290 memcpy(codec->reg_cache, wm8903_reg_defaults,
367 sizeof(wm8903_reg_defaults)); 291 sizeof(wm8903_reg_defaults));
368} 292}
@@ -423,52 +347,52 @@ static int wm8903_output_event(struct snd_soc_dapm_widget *w,
423 } 347 }
424 348
425 if (event & SND_SOC_DAPM_PRE_PMU) { 349 if (event & SND_SOC_DAPM_PRE_PMU) {
426 val = wm8903_read(codec, reg); 350 val = snd_soc_read(codec, reg);
427 351
428 /* Short the output */ 352 /* Short the output */
429 val &= ~(WM8903_OUTPUT_SHORT << shift); 353 val &= ~(WM8903_OUTPUT_SHORT << shift);
430 wm8903_write(codec, reg, val); 354 snd_soc_write(codec, reg, val);
431 } 355 }
432 356
433 if (event & SND_SOC_DAPM_POST_PMU) { 357 if (event & SND_SOC_DAPM_POST_PMU) {
434 val = wm8903_read(codec, reg); 358 val = snd_soc_read(codec, reg);
435 359
436 val |= (WM8903_OUTPUT_IN << shift); 360 val |= (WM8903_OUTPUT_IN << shift);
437 wm8903_write(codec, reg, val); 361 snd_soc_write(codec, reg, val);
438 362
439 val |= (WM8903_OUTPUT_INT << shift); 363 val |= (WM8903_OUTPUT_INT << shift);
440 wm8903_write(codec, reg, val); 364 snd_soc_write(codec, reg, val);
441 365
442 /* Turn on the output ENA_OUTP */ 366 /* Turn on the output ENA_OUTP */
443 val |= (WM8903_OUTPUT_OUT << shift); 367 val |= (WM8903_OUTPUT_OUT << shift);
444 wm8903_write(codec, reg, val); 368 snd_soc_write(codec, reg, val);
445 369
446 /* Enable the DC servo */ 370 /* Enable the DC servo */
447 dcs_reg = wm8903_read(codec, WM8903_DC_SERVO_0); 371 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
448 dcs_reg |= dcs_bit; 372 dcs_reg |= dcs_bit;
449 wm8903_write(codec, WM8903_DC_SERVO_0, dcs_reg); 373 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
450 374
451 /* Remove the short */ 375 /* Remove the short */
452 val |= (WM8903_OUTPUT_SHORT << shift); 376 val |= (WM8903_OUTPUT_SHORT << shift);
453 wm8903_write(codec, reg, val); 377 snd_soc_write(codec, reg, val);
454 } 378 }
455 379
456 if (event & SND_SOC_DAPM_PRE_PMD) { 380 if (event & SND_SOC_DAPM_PRE_PMD) {
457 val = wm8903_read(codec, reg); 381 val = snd_soc_read(codec, reg);
458 382
459 /* Short the output */ 383 /* Short the output */
460 val &= ~(WM8903_OUTPUT_SHORT << shift); 384 val &= ~(WM8903_OUTPUT_SHORT << shift);
461 wm8903_write(codec, reg, val); 385 snd_soc_write(codec, reg, val);
462 386
463 /* Disable the DC servo */ 387 /* Disable the DC servo */
464 dcs_reg = wm8903_read(codec, WM8903_DC_SERVO_0); 388 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
465 dcs_reg &= ~dcs_bit; 389 dcs_reg &= ~dcs_bit;
466 wm8903_write(codec, WM8903_DC_SERVO_0, dcs_reg); 390 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
467 391
468 /* Then disable the intermediate and output stages */ 392 /* Then disable the intermediate and output stages */
469 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT | 393 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
470 WM8903_OUTPUT_IN) << shift); 394 WM8903_OUTPUT_IN) << shift);
471 wm8903_write(codec, reg, val); 395 snd_soc_write(codec, reg, val);
472 } 396 }
473 397
474 return 0; 398 return 0;
@@ -492,13 +416,13 @@ static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
492 u16 reg; 416 u16 reg;
493 int ret; 417 int ret;
494 418
495 reg = wm8903_read(codec, WM8903_CLASS_W_0); 419 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
496 420
497 /* Turn it off if we're about to enable bypass */ 421 /* Turn it off if we're about to enable bypass */
498 if (ucontrol->value.integer.value[0]) { 422 if (ucontrol->value.integer.value[0]) {
499 if (wm8903->class_w_users == 0) { 423 if (wm8903->class_w_users == 0) {
500 dev_dbg(&i2c->dev, "Disabling Class W\n"); 424 dev_dbg(&i2c->dev, "Disabling Class W\n");
501 wm8903_write(codec, WM8903_CLASS_W_0, reg & 425 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
502 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); 426 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
503 } 427 }
504 wm8903->class_w_users++; 428 wm8903->class_w_users++;
@@ -511,7 +435,7 @@ static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
511 if (!ucontrol->value.integer.value[0]) { 435 if (!ucontrol->value.integer.value[0]) {
512 if (wm8903->class_w_users == 1) { 436 if (wm8903->class_w_users == 1) {
513 dev_dbg(&i2c->dev, "Enabling Class W\n"); 437 dev_dbg(&i2c->dev, "Enabling Class W\n");
514 wm8903_write(codec, WM8903_CLASS_W_0, reg | 438 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
515 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 439 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
516 } 440 }
517 wm8903->class_w_users--; 441 wm8903->class_w_users--;
@@ -1009,55 +933,55 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1009 switch (level) { 933 switch (level) {
1010 case SND_SOC_BIAS_ON: 934 case SND_SOC_BIAS_ON:
1011 case SND_SOC_BIAS_PREPARE: 935 case SND_SOC_BIAS_PREPARE:
1012 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0); 936 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
1013 reg &= ~(WM8903_VMID_RES_MASK); 937 reg &= ~(WM8903_VMID_RES_MASK);
1014 reg |= WM8903_VMID_RES_50K; 938 reg |= WM8903_VMID_RES_50K;
1015 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg); 939 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
1016 break; 940 break;
1017 941
1018 case SND_SOC_BIAS_STANDBY: 942 case SND_SOC_BIAS_STANDBY:
1019 if (codec->bias_level == SND_SOC_BIAS_OFF) { 943 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1020 wm8903_write(codec, WM8903_CLOCK_RATES_2, 944 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
1021 WM8903_CLK_SYS_ENA); 945 WM8903_CLK_SYS_ENA);
1022 946
1023 /* Change DC servo dither level in startup sequence */ 947 /* Change DC servo dither level in startup sequence */
1024 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11); 948 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1025 wm8903_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257); 949 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1026 wm8903_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2); 950 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
1027 951
1028 wm8903_run_sequence(codec, 0); 952 wm8903_run_sequence(codec, 0);
1029 wm8903_sync_reg_cache(codec, codec->reg_cache); 953 wm8903_sync_reg_cache(codec, codec->reg_cache);
1030 954
1031 /* Enable low impedence charge pump output */ 955 /* Enable low impedence charge pump output */
1032 reg = wm8903_read(codec, 956 reg = snd_soc_read(codec,
1033 WM8903_CONTROL_INTERFACE_TEST_1); 957 WM8903_CONTROL_INTERFACE_TEST_1);
1034 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, 958 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1035 reg | WM8903_TEST_KEY); 959 reg | WM8903_TEST_KEY);
1036 reg2 = wm8903_read(codec, WM8903_CHARGE_PUMP_TEST_1); 960 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
1037 wm8903_write(codec, WM8903_CHARGE_PUMP_TEST_1, 961 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
1038 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK); 962 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
1039 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, 963 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1040 reg); 964 reg);
1041 965
1042 /* By default no bypass paths are enabled so 966 /* By default no bypass paths are enabled so
1043 * enable Class W support. 967 * enable Class W support.
1044 */ 968 */
1045 dev_dbg(&i2c->dev, "Enabling Class W\n"); 969 dev_dbg(&i2c->dev, "Enabling Class W\n");
1046 wm8903_write(codec, WM8903_CLASS_W_0, reg | 970 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
1047 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 971 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
1048 } 972 }
1049 973
1050 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0); 974 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
1051 reg &= ~(WM8903_VMID_RES_MASK); 975 reg &= ~(WM8903_VMID_RES_MASK);
1052 reg |= WM8903_VMID_RES_250K; 976 reg |= WM8903_VMID_RES_250K;
1053 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg); 977 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
1054 break; 978 break;
1055 979
1056 case SND_SOC_BIAS_OFF: 980 case SND_SOC_BIAS_OFF:
1057 wm8903_run_sequence(codec, 32); 981 wm8903_run_sequence(codec, 32);
1058 reg = wm8903_read(codec, WM8903_CLOCK_RATES_2); 982 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
1059 reg &= ~WM8903_CLK_SYS_ENA; 983 reg &= ~WM8903_CLK_SYS_ENA;
1060 wm8903_write(codec, WM8903_CLOCK_RATES_2, reg); 984 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
1061 break; 985 break;
1062 } 986 }
1063 987
@@ -1081,7 +1005,7 @@ static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1081 unsigned int fmt) 1005 unsigned int fmt)
1082{ 1006{
1083 struct snd_soc_codec *codec = codec_dai->codec; 1007 struct snd_soc_codec *codec = codec_dai->codec;
1084 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1); 1008 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1085 1009
1086 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | 1010 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1087 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); 1011 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
@@ -1159,7 +1083,7 @@ static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1159 return -EINVAL; 1083 return -EINVAL;
1160 } 1084 }
1161 1085
1162 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1086 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1163 1087
1164 return 0; 1088 return 0;
1165} 1089}
@@ -1169,14 +1093,14 @@ static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1169 struct snd_soc_codec *codec = codec_dai->codec; 1093 struct snd_soc_codec *codec = codec_dai->codec;
1170 u16 reg; 1094 u16 reg;
1171 1095
1172 reg = wm8903_read(codec, WM8903_DAC_DIGITAL_1); 1096 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1173 1097
1174 if (mute) 1098 if (mute)
1175 reg |= WM8903_DAC_MUTE; 1099 reg |= WM8903_DAC_MUTE;
1176 else 1100 else
1177 reg &= ~WM8903_DAC_MUTE; 1101 reg &= ~WM8903_DAC_MUTE;
1178 1102
1179 wm8903_write(codec, WM8903_DAC_DIGITAL_1, reg); 1103 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
1180 1104
1181 return 0; 1105 return 0;
1182} 1106}
@@ -1366,12 +1290,12 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
1366 int cur_val; 1290 int cur_val;
1367 int clk_sys; 1291 int clk_sys;
1368 1292
1369 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1); 1293 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1370 u16 aif2 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_2); 1294 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1371 u16 aif3 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_3); 1295 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1372 u16 clock0 = wm8903_read(codec, WM8903_CLOCK_RATES_0); 1296 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1373 u16 clock1 = wm8903_read(codec, WM8903_CLOCK_RATES_1); 1297 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1374 u16 dac_digital1 = wm8903_read(codec, WM8903_DAC_DIGITAL_1); 1298 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1375 1299
1376 if (substream == wm8903->slave_substream) { 1300 if (substream == wm8903->slave_substream) {
1377 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n"); 1301 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
@@ -1503,12 +1427,12 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
1503 aif2 |= bclk_divs[bclk_div].div; 1427 aif2 |= bclk_divs[bclk_div].div;
1504 aif3 |= bclk / fs; 1428 aif3 |= bclk / fs;
1505 1429
1506 wm8903_write(codec, WM8903_CLOCK_RATES_0, clock0); 1430 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1507 wm8903_write(codec, WM8903_CLOCK_RATES_1, clock1); 1431 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1508 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1432 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1509 wm8903_write(codec, WM8903_AUDIO_INTERFACE_2, aif2); 1433 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1510 wm8903_write(codec, WM8903_AUDIO_INTERFACE_3, aif3); 1434 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1511 wm8903_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1); 1435 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
1512 1436
1513 return 0; 1437 return 0;
1514} 1438}
@@ -1593,7 +1517,7 @@ static int wm8903_resume(struct platform_device *pdev)
1593 if (tmp_cache) { 1517 if (tmp_cache) {
1594 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++) 1518 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1595 if (tmp_cache[i] != reg_cache[i]) 1519 if (tmp_cache[i] != reg_cache[i])
1596 wm8903_write(codec, i, tmp_cache[i]); 1520 snd_soc_write(codec, i, tmp_cache[i]);
1597 } else { 1521 } else {
1598 dev_err(&i2c->dev, "Failed to allocate temporary cache\n"); 1522 dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1599 } 1523 }
@@ -1624,9 +1548,6 @@ static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1624 codec->dev = &i2c->dev; 1548 codec->dev = &i2c->dev;
1625 codec->name = "WM8903"; 1549 codec->name = "WM8903";
1626 codec->owner = THIS_MODULE; 1550 codec->owner = THIS_MODULE;
1627 codec->read = wm8903_read;
1628 codec->write = wm8903_write;
1629 codec->hw_write = (hw_write_t)i2c_master_send;
1630 codec->bias_level = SND_SOC_BIAS_OFF; 1551 codec->bias_level = SND_SOC_BIAS_OFF;
1631 codec->set_bias_level = wm8903_set_bias_level; 1552 codec->set_bias_level = wm8903_set_bias_level;
1632 codec->dai = &wm8903_dai; 1553 codec->dai = &wm8903_dai;
@@ -1634,18 +1555,25 @@ static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1634 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache); 1555 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
1635 codec->reg_cache = &wm8903->reg_cache[0]; 1556 codec->reg_cache = &wm8903->reg_cache[0];
1636 codec->private_data = wm8903; 1557 codec->private_data = wm8903;
1558 codec->volatile_register = wm8903_volatile_register;
1637 1559
1638 i2c_set_clientdata(i2c, codec); 1560 i2c_set_clientdata(i2c, codec);
1639 codec->control_data = i2c; 1561 codec->control_data = i2c;
1640 1562
1641 val = wm8903_hw_read(codec, WM8903_SW_RESET_AND_ID); 1563 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1564 if (ret != 0) {
1565 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
1566 goto err;
1567 }
1568
1569 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
1642 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) { 1570 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1643 dev_err(&i2c->dev, 1571 dev_err(&i2c->dev,
1644 "Device with ID register %x is not a WM8903\n", val); 1572 "Device with ID register %x is not a WM8903\n", val);
1645 return -ENODEV; 1573 return -ENODEV;
1646 } 1574 }
1647 1575
1648 val = wm8903_read(codec, WM8903_REVISION_NUMBER); 1576 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1649 dev_info(&i2c->dev, "WM8903 revision %d\n", 1577 dev_info(&i2c->dev, "WM8903 revision %d\n",
1650 val & WM8903_CHIP_REV_MASK); 1578 val & WM8903_CHIP_REV_MASK);
1651 1579
@@ -1655,35 +1583,35 @@ static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1655 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1583 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1656 1584
1657 /* Latch volume update bits */ 1585 /* Latch volume update bits */
1658 val = wm8903_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT); 1586 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1659 val |= WM8903_ADCVU; 1587 val |= WM8903_ADCVU;
1660 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val); 1588 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1661 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val); 1589 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1662 1590
1663 val = wm8903_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT); 1591 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1664 val |= WM8903_DACVU; 1592 val |= WM8903_DACVU;
1665 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val); 1593 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1666 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val); 1594 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1667 1595
1668 val = wm8903_read(codec, WM8903_ANALOGUE_OUT1_LEFT); 1596 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1669 val |= WM8903_HPOUTVU; 1597 val |= WM8903_HPOUTVU;
1670 wm8903_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val); 1598 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1671 wm8903_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val); 1599 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1672 1600
1673 val = wm8903_read(codec, WM8903_ANALOGUE_OUT2_LEFT); 1601 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1674 val |= WM8903_LINEOUTVU; 1602 val |= WM8903_LINEOUTVU;
1675 wm8903_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val); 1603 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1676 wm8903_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val); 1604 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1677 1605
1678 val = wm8903_read(codec, WM8903_ANALOGUE_OUT3_LEFT); 1606 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1679 val |= WM8903_SPKVU; 1607 val |= WM8903_SPKVU;
1680 wm8903_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val); 1608 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1681 wm8903_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val); 1609 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1682 1610
1683 /* Enable DAC soft mute by default */ 1611 /* Enable DAC soft mute by default */
1684 val = wm8903_read(codec, WM8903_DAC_DIGITAL_1); 1612 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1685 val |= WM8903_DAC_MUTEMODE; 1613 val |= WM8903_DAC_MUTEMODE;
1686 wm8903_write(codec, WM8903_DAC_DIGITAL_1, val); 1614 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
1687 1615
1688 wm8903_dai.dev = &i2c->dev; 1616 wm8903_dai.dev = &i2c->dev;
1689 wm8903_codec = codec; 1617 wm8903_codec = codec;
diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
index b69210a77423..da97aae475a2 100644
--- a/sound/soc/codecs/wm8940.c
+++ b/sound/soc/codecs/wm8940.c
@@ -106,50 +106,6 @@ static u16 wm8940_reg_defaults[] = {
106 0x0000, /* Mono Mixer Control */ 106 0x0000, /* Mono Mixer Control */
107}; 107};
108 108
109static inline unsigned int wm8940_read_reg_cache(struct snd_soc_codec *codec,
110 unsigned int reg)
111{
112 u16 *cache = codec->reg_cache;
113
114 if (reg >= ARRAY_SIZE(wm8940_reg_defaults))
115 return -1;
116
117 return cache[reg];
118}
119
120static inline int wm8940_write_reg_cache(struct snd_soc_codec *codec,
121 u16 reg, unsigned int value)
122{
123 u16 *cache = codec->reg_cache;
124
125 if (reg >= ARRAY_SIZE(wm8940_reg_defaults))
126 return -1;
127
128 cache[reg] = value;
129
130 return 0;
131}
132
133static int wm8940_write(struct snd_soc_codec *codec, unsigned int reg,
134 unsigned int value)
135{
136 int ret;
137 u8 data[3] = { reg,
138 (value & 0xff00) >> 8,
139 (value & 0x00ff)
140 };
141
142 wm8940_write_reg_cache(codec, reg, value);
143
144 ret = codec->hw_write(codec->control_data, data, 3);
145
146 if (ret < 0)
147 return ret;
148 else if (ret != 3)
149 return -EIO;
150 return 0;
151}
152
153static const char *wm8940_companding[] = { "Off", "NC", "u-law", "A-law" }; 109static const char *wm8940_companding[] = { "Off", "NC", "u-law", "A-law" };
154static const struct soc_enum wm8940_adc_companding_enum 110static const struct soc_enum wm8940_adc_companding_enum
155= SOC_ENUM_SINGLE(WM8940_COMPANDINGCTL, 1, 4, wm8940_companding); 111= SOC_ENUM_SINGLE(WM8940_COMPANDINGCTL, 1, 4, wm8940_companding);
@@ -348,14 +304,14 @@ error_ret:
348 return ret; 304 return ret;
349} 305}
350 306
351#define wm8940_reset(c) wm8940_write(c, WM8940_SOFTRESET, 0); 307#define wm8940_reset(c) snd_soc_write(c, WM8940_SOFTRESET, 0);
352 308
353static int wm8940_set_dai_fmt(struct snd_soc_dai *codec_dai, 309static int wm8940_set_dai_fmt(struct snd_soc_dai *codec_dai,
354 unsigned int fmt) 310 unsigned int fmt)
355{ 311{
356 struct snd_soc_codec *codec = codec_dai->codec; 312 struct snd_soc_codec *codec = codec_dai->codec;
357 u16 iface = wm8940_read_reg_cache(codec, WM8940_IFACE) & 0xFE67; 313 u16 iface = snd_soc_read(codec, WM8940_IFACE) & 0xFE67;
358 u16 clk = wm8940_read_reg_cache(codec, WM8940_CLOCK) & 0x1fe; 314 u16 clk = snd_soc_read(codec, WM8940_CLOCK) & 0x1fe;
359 315
360 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 316 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
361 case SND_SOC_DAIFMT_CBM_CFM: 317 case SND_SOC_DAIFMT_CBM_CFM:
@@ -366,7 +322,7 @@ static int wm8940_set_dai_fmt(struct snd_soc_dai *codec_dai,
366 default: 322 default:
367 return -EINVAL; 323 return -EINVAL;
368 } 324 }
369 wm8940_write(codec, WM8940_CLOCK, clk); 325 snd_soc_write(codec, WM8940_CLOCK, clk);
370 326
371 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 327 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
372 case SND_SOC_DAIFMT_I2S: 328 case SND_SOC_DAIFMT_I2S:
@@ -399,7 +355,7 @@ static int wm8940_set_dai_fmt(struct snd_soc_dai *codec_dai,
399 break; 355 break;
400 } 356 }
401 357
402 wm8940_write(codec, WM8940_IFACE, iface); 358 snd_soc_write(codec, WM8940_IFACE, iface);
403 359
404 return 0; 360 return 0;
405} 361}
@@ -411,9 +367,9 @@ static int wm8940_i2s_hw_params(struct snd_pcm_substream *substream,
411 struct snd_soc_pcm_runtime *rtd = substream->private_data; 367 struct snd_soc_pcm_runtime *rtd = substream->private_data;
412 struct snd_soc_device *socdev = rtd->socdev; 368 struct snd_soc_device *socdev = rtd->socdev;
413 struct snd_soc_codec *codec = socdev->card->codec; 369 struct snd_soc_codec *codec = socdev->card->codec;
414 u16 iface = wm8940_read_reg_cache(codec, WM8940_IFACE) & 0xFD9F; 370 u16 iface = snd_soc_read(codec, WM8940_IFACE) & 0xFD9F;
415 u16 addcntrl = wm8940_read_reg_cache(codec, WM8940_ADDCNTRL) & 0xFFF1; 371 u16 addcntrl = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFF1;
416 u16 companding = wm8940_read_reg_cache(codec, 372 u16 companding = snd_soc_read(codec,
417 WM8940_COMPANDINGCTL) & 0xFFDF; 373 WM8940_COMPANDINGCTL) & 0xFFDF;
418 int ret; 374 int ret;
419 375
@@ -442,7 +398,7 @@ static int wm8940_i2s_hw_params(struct snd_pcm_substream *substream,
442 case SNDRV_PCM_RATE_48000: 398 case SNDRV_PCM_RATE_48000:
443 break; 399 break;
444 } 400 }
445 ret = wm8940_write(codec, WM8940_ADDCNTRL, addcntrl); 401 ret = snd_soc_write(codec, WM8940_ADDCNTRL, addcntrl);
446 if (ret) 402 if (ret)
447 goto error_ret; 403 goto error_ret;
448 404
@@ -462,10 +418,10 @@ static int wm8940_i2s_hw_params(struct snd_pcm_substream *substream,
462 iface |= (3 << 5); 418 iface |= (3 << 5);
463 break; 419 break;
464 } 420 }
465 ret = wm8940_write(codec, WM8940_COMPANDINGCTL, companding); 421 ret = snd_soc_write(codec, WM8940_COMPANDINGCTL, companding);
466 if (ret) 422 if (ret)
467 goto error_ret; 423 goto error_ret;
468 ret = wm8940_write(codec, WM8940_IFACE, iface); 424 ret = snd_soc_write(codec, WM8940_IFACE, iface);
469 425
470error_ret: 426error_ret:
471 return ret; 427 return ret;
@@ -474,19 +430,19 @@ error_ret:
474static int wm8940_mute(struct snd_soc_dai *dai, int mute) 430static int wm8940_mute(struct snd_soc_dai *dai, int mute)
475{ 431{
476 struct snd_soc_codec *codec = dai->codec; 432 struct snd_soc_codec *codec = dai->codec;
477 u16 mute_reg = wm8940_read_reg_cache(codec, WM8940_DAC) & 0xffbf; 433 u16 mute_reg = snd_soc_read(codec, WM8940_DAC) & 0xffbf;
478 434
479 if (mute) 435 if (mute)
480 mute_reg |= 0x40; 436 mute_reg |= 0x40;
481 437
482 return wm8940_write(codec, WM8940_DAC, mute_reg); 438 return snd_soc_write(codec, WM8940_DAC, mute_reg);
483} 439}
484 440
485static int wm8940_set_bias_level(struct snd_soc_codec *codec, 441static int wm8940_set_bias_level(struct snd_soc_codec *codec,
486 enum snd_soc_bias_level level) 442 enum snd_soc_bias_level level)
487{ 443{
488 u16 val; 444 u16 val;
489 u16 pwr_reg = wm8940_read_reg_cache(codec, WM8940_POWER1) & 0x1F0; 445 u16 pwr_reg = snd_soc_read(codec, WM8940_POWER1) & 0x1F0;
490 int ret = 0; 446 int ret = 0;
491 447
492 switch (level) { 448 switch (level) {
@@ -494,26 +450,26 @@ static int wm8940_set_bias_level(struct snd_soc_codec *codec,
494 /* ensure bufioen and biasen */ 450 /* ensure bufioen and biasen */
495 pwr_reg |= (1 << 2) | (1 << 3); 451 pwr_reg |= (1 << 2) | (1 << 3);
496 /* Enable thermal shutdown */ 452 /* Enable thermal shutdown */
497 val = wm8940_read_reg_cache(codec, WM8940_OUTPUTCTL); 453 val = snd_soc_read(codec, WM8940_OUTPUTCTL);
498 ret = wm8940_write(codec, WM8940_OUTPUTCTL, val | 0x2); 454 ret = snd_soc_write(codec, WM8940_OUTPUTCTL, val | 0x2);
499 if (ret) 455 if (ret)
500 break; 456 break;
501 /* set vmid to 75k */ 457 /* set vmid to 75k */
502 ret = wm8940_write(codec, WM8940_POWER1, pwr_reg | 0x1); 458 ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x1);
503 break; 459 break;
504 case SND_SOC_BIAS_PREPARE: 460 case SND_SOC_BIAS_PREPARE:
505 /* ensure bufioen and biasen */ 461 /* ensure bufioen and biasen */
506 pwr_reg |= (1 << 2) | (1 << 3); 462 pwr_reg |= (1 << 2) | (1 << 3);
507 ret = wm8940_write(codec, WM8940_POWER1, pwr_reg | 0x1); 463 ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x1);
508 break; 464 break;
509 case SND_SOC_BIAS_STANDBY: 465 case SND_SOC_BIAS_STANDBY:
510 /* ensure bufioen and biasen */ 466 /* ensure bufioen and biasen */
511 pwr_reg |= (1 << 2) | (1 << 3); 467 pwr_reg |= (1 << 2) | (1 << 3);
512 /* set vmid to 300k for standby */ 468 /* set vmid to 300k for standby */
513 ret = wm8940_write(codec, WM8940_POWER1, pwr_reg | 0x2); 469 ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x2);
514 break; 470 break;
515 case SND_SOC_BIAS_OFF: 471 case SND_SOC_BIAS_OFF:
516 ret = wm8940_write(codec, WM8940_POWER1, pwr_reg); 472 ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg);
517 break; 473 break;
518 } 474 }
519 475
@@ -587,36 +543,36 @@ static int wm8940_set_dai_pll(struct snd_soc_dai *codec_dai,
587 u16 reg; 543 u16 reg;
588 544
589 /* Turn off PLL */ 545 /* Turn off PLL */
590 reg = wm8940_read_reg_cache(codec, WM8940_POWER1); 546 reg = snd_soc_read(codec, WM8940_POWER1);
591 wm8940_write(codec, WM8940_POWER1, reg & 0x1df); 547 snd_soc_write(codec, WM8940_POWER1, reg & 0x1df);
592 548
593 if (freq_in == 0 || freq_out == 0) { 549 if (freq_in == 0 || freq_out == 0) {
594 /* Clock CODEC directly from MCLK */ 550 /* Clock CODEC directly from MCLK */
595 reg = wm8940_read_reg_cache(codec, WM8940_CLOCK); 551 reg = snd_soc_read(codec, WM8940_CLOCK);
596 wm8940_write(codec, WM8940_CLOCK, reg & 0x0ff); 552 snd_soc_write(codec, WM8940_CLOCK, reg & 0x0ff);
597 /* Pll power down */ 553 /* Pll power down */
598 wm8940_write(codec, WM8940_PLLN, (1 << 7)); 554 snd_soc_write(codec, WM8940_PLLN, (1 << 7));
599 return 0; 555 return 0;
600 } 556 }
601 557
602 /* Pll is followed by a frequency divide by 4 */ 558 /* Pll is followed by a frequency divide by 4 */
603 pll_factors(freq_out*4, freq_in); 559 pll_factors(freq_out*4, freq_in);
604 if (pll_div.k) 560 if (pll_div.k)
605 wm8940_write(codec, WM8940_PLLN, 561 snd_soc_write(codec, WM8940_PLLN,
606 (pll_div.pre_scale << 4) | pll_div.n | (1 << 6)); 562 (pll_div.pre_scale << 4) | pll_div.n | (1 << 6));
607 else /* No factional component */ 563 else /* No factional component */
608 wm8940_write(codec, WM8940_PLLN, 564 snd_soc_write(codec, WM8940_PLLN,
609 (pll_div.pre_scale << 4) | pll_div.n); 565 (pll_div.pre_scale << 4) | pll_div.n);
610 wm8940_write(codec, WM8940_PLLK1, pll_div.k >> 18); 566 snd_soc_write(codec, WM8940_PLLK1, pll_div.k >> 18);
611 wm8940_write(codec, WM8940_PLLK2, (pll_div.k >> 9) & 0x1ff); 567 snd_soc_write(codec, WM8940_PLLK2, (pll_div.k >> 9) & 0x1ff);
612 wm8940_write(codec, WM8940_PLLK3, pll_div.k & 0x1ff); 568 snd_soc_write(codec, WM8940_PLLK3, pll_div.k & 0x1ff);
613 /* Enable the PLL */ 569 /* Enable the PLL */
614 reg = wm8940_read_reg_cache(codec, WM8940_POWER1); 570 reg = snd_soc_read(codec, WM8940_POWER1);
615 wm8940_write(codec, WM8940_POWER1, reg | 0x020); 571 snd_soc_write(codec, WM8940_POWER1, reg | 0x020);
616 572
617 /* Run CODEC from PLL instead of MCLK */ 573 /* Run CODEC from PLL instead of MCLK */
618 reg = wm8940_read_reg_cache(codec, WM8940_CLOCK); 574 reg = snd_soc_read(codec, WM8940_CLOCK);
619 wm8940_write(codec, WM8940_CLOCK, reg | 0x100); 575 snd_soc_write(codec, WM8940_CLOCK, reg | 0x100);
620 576
621 return 0; 577 return 0;
622} 578}
@@ -648,16 +604,16 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
648 604
649 switch (div_id) { 605 switch (div_id) {
650 case WM8940_BCLKDIV: 606 case WM8940_BCLKDIV:
651 reg = wm8940_read_reg_cache(codec, WM8940_CLOCK) & 0xFFEF3; 607 reg = snd_soc_read(codec, WM8940_CLOCK) & 0xFFEF3;
652 ret = wm8940_write(codec, WM8940_CLOCK, reg | (div << 2)); 608 ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 2));
653 break; 609 break;
654 case WM8940_MCLKDIV: 610 case WM8940_MCLKDIV:
655 reg = wm8940_read_reg_cache(codec, WM8940_CLOCK) & 0xFF1F; 611 reg = snd_soc_read(codec, WM8940_CLOCK) & 0xFF1F;
656 ret = wm8940_write(codec, WM8940_CLOCK, reg | (div << 5)); 612 ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 5));
657 break; 613 break;
658 case WM8940_OPCLKDIV: 614 case WM8940_OPCLKDIV:
659 reg = wm8940_read_reg_cache(codec, WM8940_ADDCNTRL) & 0xFFCF; 615 reg = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFCF;
660 ret = wm8940_write(codec, WM8940_ADDCNTRL, reg | (div << 4)); 616 ret = snd_soc_write(codec, WM8940_ADDCNTRL, reg | (div << 4));
661 break; 617 break;
662 } 618 }
663 return ret; 619 return ret;
@@ -808,7 +764,8 @@ struct snd_soc_codec_device soc_codec_dev_wm8940 = {
808}; 764};
809EXPORT_SYMBOL_GPL(soc_codec_dev_wm8940); 765EXPORT_SYMBOL_GPL(soc_codec_dev_wm8940);
810 766
811static int wm8940_register(struct wm8940_priv *wm8940) 767static int wm8940_register(struct wm8940_priv *wm8940,
768 enum snd_soc_control_type control)
812{ 769{
813 struct wm8940_setup_data *pdata = wm8940->codec.dev->platform_data; 770 struct wm8940_setup_data *pdata = wm8940->codec.dev->platform_data;
814 struct snd_soc_codec *codec = &wm8940->codec; 771 struct snd_soc_codec *codec = &wm8940->codec;
@@ -825,8 +782,6 @@ static int wm8940_register(struct wm8940_priv *wm8940)
825 codec->private_data = wm8940; 782 codec->private_data = wm8940;
826 codec->name = "WM8940"; 783 codec->name = "WM8940";
827 codec->owner = THIS_MODULE; 784 codec->owner = THIS_MODULE;
828 codec->read = wm8940_read_reg_cache;
829 codec->write = wm8940_write;
830 codec->bias_level = SND_SOC_BIAS_OFF; 785 codec->bias_level = SND_SOC_BIAS_OFF;
831 codec->set_bias_level = wm8940_set_bias_level; 786 codec->set_bias_level = wm8940_set_bias_level;
832 codec->dai = &wm8940_dai; 787 codec->dai = &wm8940_dai;
@@ -834,6 +789,12 @@ static int wm8940_register(struct wm8940_priv *wm8940)
834 codec->reg_cache_size = ARRAY_SIZE(wm8940_reg_defaults); 789 codec->reg_cache_size = ARRAY_SIZE(wm8940_reg_defaults);
835 codec->reg_cache = &wm8940->reg_cache; 790 codec->reg_cache = &wm8940->reg_cache;
836 791
792 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
793 if (ret == 0) {
794 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
795 return ret;
796 }
797
837 memcpy(codec->reg_cache, wm8940_reg_defaults, 798 memcpy(codec->reg_cache, wm8940_reg_defaults,
838 sizeof(wm8940_reg_defaults)); 799 sizeof(wm8940_reg_defaults));
839 800
@@ -847,15 +808,15 @@ static int wm8940_register(struct wm8940_priv *wm8940)
847 808
848 wm8940_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 809 wm8940_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
849 810
850 ret = wm8940_write(codec, WM8940_POWER1, 0x180); 811 ret = snd_soc_write(codec, WM8940_POWER1, 0x180);
851 if (ret < 0) 812 if (ret < 0)
852 return ret; 813 return ret;
853 814
854 if (!pdata) 815 if (!pdata)
855 dev_warn(codec->dev, "No platform data supplied\n"); 816 dev_warn(codec->dev, "No platform data supplied\n");
856 else { 817 else {
857 reg = wm8940_read_reg_cache(codec, WM8940_OUTPUTCTL); 818 reg = snd_soc_read(codec, WM8940_OUTPUTCTL);
858 ret = wm8940_write(codec, WM8940_OUTPUTCTL, reg | pdata->vroi); 819 ret = snd_soc_write(codec, WM8940_OUTPUTCTL, reg | pdata->vroi);
859 if (ret < 0) 820 if (ret < 0)
860 return ret; 821 return ret;
861 } 822 }
@@ -904,7 +865,7 @@ static int wm8940_i2c_probe(struct i2c_client *i2c,
904 codec->control_data = i2c; 865 codec->control_data = i2c;
905 codec->dev = &i2c->dev; 866 codec->dev = &i2c->dev;
906 867
907 return wm8940_register(wm8940); 868 return wm8940_register(wm8940, SND_SOC_I2C);
908} 869}
909 870
910static int __devexit wm8940_i2c_remove(struct i2c_client *client) 871static int __devexit wm8940_i2c_remove(struct i2c_client *client)
diff --git a/sound/soc/codecs/wm8961.c b/sound/soc/codecs/wm8961.c
index bd1af92a122f..503032085899 100644
--- a/sound/soc/codecs/wm8961.c
+++ b/sound/soc/codecs/wm8961.c
@@ -292,9 +292,10 @@ struct wm8961_priv {
292 u16 reg_cache[WM8961_MAX_REGISTER]; 292 u16 reg_cache[WM8961_MAX_REGISTER];
293}; 293};
294 294
295static int wm8961_reg_is_volatile(int reg) 295static int wm8961_volatile_register(unsigned int reg)
296{ 296{
297 switch (reg) { 297 switch (reg) {
298 case WM8961_SOFTWARE_RESET:
298 case WM8961_WRITE_SEQUENCER_7: 299 case WM8961_WRITE_SEQUENCER_7:
299 case WM8961_DC_SERVO_1: 300 case WM8961_DC_SERVO_1:
300 return 1; 301 return 1;
@@ -304,76 +305,9 @@ static int wm8961_reg_is_volatile(int reg)
304 } 305 }
305} 306}
306 307
307static unsigned int wm8961_read_reg_cache(struct snd_soc_codec *codec,
308 unsigned int reg)
309{
310 u16 *cache = codec->reg_cache;
311 BUG_ON(reg > WM8961_MAX_REGISTER);
312 return cache[reg];
313}
314
315static unsigned int wm8961_read_hw(struct snd_soc_codec *codec, u8 reg)
316{
317 struct i2c_msg xfer[2];
318 u16 data;
319 int ret;
320 struct i2c_client *client = codec->control_data;
321
322 BUG_ON(reg > WM8961_MAX_REGISTER);
323
324 /* Write register */
325 xfer[0].addr = client->addr;
326 xfer[0].flags = 0;
327 xfer[0].len = 1;
328 xfer[0].buf = &reg;
329
330 /* Read data */
331 xfer[1].addr = client->addr;
332 xfer[1].flags = I2C_M_RD;
333 xfer[1].len = 2;
334 xfer[1].buf = (u8 *)&data;
335
336 ret = i2c_transfer(client->adapter, xfer, 2);
337 if (ret != 2) {
338 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
339 return 0;
340 }
341
342 return (data >> 8) | ((data & 0xff) << 8);
343}
344
345static unsigned int wm8961_read(struct snd_soc_codec *codec, unsigned int reg)
346{
347 if (wm8961_reg_is_volatile(reg))
348 return wm8961_read_hw(codec, reg);
349 else
350 return wm8961_read_reg_cache(codec, reg);
351}
352
353static int wm8961_write(struct snd_soc_codec *codec, unsigned int reg,
354 unsigned int value)
355{
356 u16 *cache = codec->reg_cache;
357 u8 data[3];
358
359 BUG_ON(reg > WM8961_MAX_REGISTER);
360
361 if (!wm8961_reg_is_volatile(reg))
362 cache[reg] = value;
363
364 data[0] = reg;
365 data[1] = value >> 8;
366 data[2] = value & 0x00ff;
367
368 if (codec->hw_write(codec->control_data, data, 3) == 3)
369 return 0;
370 else
371 return -EIO;
372}
373
374static int wm8961_reset(struct snd_soc_codec *codec) 308static int wm8961_reset(struct snd_soc_codec *codec)
375{ 309{
376 return wm8961_write(codec, WM8961_SOFTWARE_RESET, 0); 310 return snd_soc_write(codec, WM8961_SOFTWARE_RESET, 0);
377} 311}
378 312
379/* 313/*
@@ -384,33 +318,33 @@ static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
384 struct snd_kcontrol *kcontrol, int event) 318 struct snd_kcontrol *kcontrol, int event)
385{ 319{
386 struct snd_soc_codec *codec = w->codec; 320 struct snd_soc_codec *codec = w->codec;
387 u16 hp_reg = wm8961_read(codec, WM8961_ANALOGUE_HP_0); 321 u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
388 u16 cp_reg = wm8961_read(codec, WM8961_CHARGE_PUMP_1); 322 u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
389 u16 pwr_reg = wm8961_read(codec, WM8961_PWR_MGMT_2); 323 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
390 u16 dcs_reg = wm8961_read(codec, WM8961_DC_SERVO_1); 324 u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
391 int timeout = 500; 325 int timeout = 500;
392 326
393 if (event & SND_SOC_DAPM_POST_PMU) { 327 if (event & SND_SOC_DAPM_POST_PMU) {
394 /* Make sure the output is shorted */ 328 /* Make sure the output is shorted */
395 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT); 329 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
396 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 330 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
397 331
398 /* Enable the charge pump */ 332 /* Enable the charge pump */
399 cp_reg |= WM8961_CP_ENA; 333 cp_reg |= WM8961_CP_ENA;
400 wm8961_write(codec, WM8961_CHARGE_PUMP_1, cp_reg); 334 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
401 mdelay(5); 335 mdelay(5);
402 336
403 /* Enable the PGA */ 337 /* Enable the PGA */
404 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA; 338 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
405 wm8961_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 339 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
406 340
407 /* Enable the amplifier */ 341 /* Enable the amplifier */
408 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA; 342 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
409 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 343 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
410 344
411 /* Second stage enable */ 345 /* Second stage enable */
412 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY; 346 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
413 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 347 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
414 348
415 /* Enable the DC servo & trigger startup */ 349 /* Enable the DC servo & trigger startup */
416 dcs_reg |= 350 dcs_reg |=
@@ -418,10 +352,10 @@ static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
418 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL; 352 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
419 dev_dbg(codec->dev, "Enabling DC servo\n"); 353 dev_dbg(codec->dev, "Enabling DC servo\n");
420 354
421 wm8961_write(codec, WM8961_DC_SERVO_1, dcs_reg); 355 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
422 do { 356 do {
423 msleep(1); 357 msleep(1);
424 dcs_reg = wm8961_read(codec, WM8961_DC_SERVO_1); 358 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
425 } while (--timeout && 359 } while (--timeout &&
426 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR | 360 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
427 WM8961_DCS_TRIG_STARTUP_HPL)); 361 WM8961_DCS_TRIG_STARTUP_HPL));
@@ -433,39 +367,39 @@ static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
433 367
434 /* Enable the output stage */ 368 /* Enable the output stage */
435 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP; 369 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
436 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 370 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
437 371
438 /* Remove the short on the output stage */ 372 /* Remove the short on the output stage */
439 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT; 373 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
440 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 374 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
441 } 375 }
442 376
443 if (event & SND_SOC_DAPM_PRE_PMD) { 377 if (event & SND_SOC_DAPM_PRE_PMD) {
444 /* Short the output */ 378 /* Short the output */
445 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT); 379 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
446 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 380 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
447 381
448 /* Disable the output stage */ 382 /* Disable the output stage */
449 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP); 383 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
450 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 384 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
451 385
452 /* Disable DC offset cancellation */ 386 /* Disable DC offset cancellation */
453 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR | 387 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
454 WM8961_DCS_ENA_CHAN_HPL); 388 WM8961_DCS_ENA_CHAN_HPL);
455 wm8961_write(codec, WM8961_DC_SERVO_1, dcs_reg); 389 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
456 390
457 /* Finish up */ 391 /* Finish up */
458 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA | 392 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
459 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA); 393 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
460 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 394 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
461 395
462 /* Disable the PGA */ 396 /* Disable the PGA */
463 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA); 397 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
464 wm8961_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 398 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
465 399
466 /* Disable the charge pump */ 400 /* Disable the charge pump */
467 dev_dbg(codec->dev, "Disabling charge pump\n"); 401 dev_dbg(codec->dev, "Disabling charge pump\n");
468 wm8961_write(codec, WM8961_CHARGE_PUMP_1, 402 snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
469 cp_reg & ~WM8961_CP_ENA); 403 cp_reg & ~WM8961_CP_ENA);
470 } 404 }
471 405
@@ -476,27 +410,27 @@ static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
476 struct snd_kcontrol *kcontrol, int event) 410 struct snd_kcontrol *kcontrol, int event)
477{ 411{
478 struct snd_soc_codec *codec = w->codec; 412 struct snd_soc_codec *codec = w->codec;
479 u16 pwr_reg = wm8961_read(codec, WM8961_PWR_MGMT_2); 413 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
480 u16 spk_reg = wm8961_read(codec, WM8961_CLASS_D_CONTROL_1); 414 u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
481 415
482 if (event & SND_SOC_DAPM_POST_PMU) { 416 if (event & SND_SOC_DAPM_POST_PMU) {
483 /* Enable the PGA */ 417 /* Enable the PGA */
484 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA; 418 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
485 wm8961_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 419 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
486 420
487 /* Enable the amplifier */ 421 /* Enable the amplifier */
488 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA; 422 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
489 wm8961_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg); 423 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
490 } 424 }
491 425
492 if (event & SND_SOC_DAPM_PRE_PMD) { 426 if (event & SND_SOC_DAPM_PRE_PMD) {
493 /* Enable the amplifier */ 427 /* Enable the amplifier */
494 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA); 428 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
495 wm8961_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg); 429 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
496 430
497 /* Enable the PGA */ 431 /* Enable the PGA */
498 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA); 432 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
499 wm8961_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 433 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
500 } 434 }
501 435
502 return 0; 436 return 0;
@@ -714,10 +648,10 @@ static int wm8961_hw_params(struct snd_pcm_substream *substream,
714 abs(wm8961_srate[best].rate - fs)) 648 abs(wm8961_srate[best].rate - fs))
715 best = i; 649 best = i;
716 } 650 }
717 reg = wm8961_read(codec, WM8961_ADDITIONAL_CONTROL_3); 651 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
718 reg &= ~WM8961_SAMPLE_RATE_MASK; 652 reg &= ~WM8961_SAMPLE_RATE_MASK;
719 reg |= wm8961_srate[best].val; 653 reg |= wm8961_srate[best].val;
720 wm8961_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg); 654 snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
721 dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n", 655 dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
722 wm8961_srate[best].rate, fs); 656 wm8961_srate[best].rate, fs);
723 657
@@ -747,12 +681,12 @@ static int wm8961_hw_params(struct snd_pcm_substream *substream,
747 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs, 681 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
748 wm8961->sysclk / fs); 682 wm8961->sysclk / fs);
749 683
750 reg = wm8961_read(codec, WM8961_CLOCKING_4); 684 reg = snd_soc_read(codec, WM8961_CLOCKING_4);
751 reg &= ~WM8961_CLK_SYS_RATE_MASK; 685 reg &= ~WM8961_CLK_SYS_RATE_MASK;
752 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT; 686 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
753 wm8961_write(codec, WM8961_CLOCKING_4, reg); 687 snd_soc_write(codec, WM8961_CLOCKING_4, reg);
754 688
755 reg = wm8961_read(codec, WM8961_AUDIO_INTERFACE_0); 689 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
756 reg &= ~WM8961_WL_MASK; 690 reg &= ~WM8961_WL_MASK;
757 switch (params_format(params)) { 691 switch (params_format(params)) {
758 case SNDRV_PCM_FORMAT_S16_LE: 692 case SNDRV_PCM_FORMAT_S16_LE:
@@ -769,15 +703,15 @@ static int wm8961_hw_params(struct snd_pcm_substream *substream,
769 default: 703 default:
770 return -EINVAL; 704 return -EINVAL;
771 } 705 }
772 wm8961_write(codec, WM8961_AUDIO_INTERFACE_0, reg); 706 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
773 707
774 /* Sloping stop-band filter is recommended for <= 24kHz */ 708 /* Sloping stop-band filter is recommended for <= 24kHz */
775 reg = wm8961_read(codec, WM8961_ADC_DAC_CONTROL_2); 709 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
776 if (fs <= 24000) 710 if (fs <= 24000)
777 reg |= WM8961_DACSLOPE; 711 reg |= WM8961_DACSLOPE;
778 else 712 else
779 reg &= WM8961_DACSLOPE; 713 reg &= WM8961_DACSLOPE;
780 wm8961_write(codec, WM8961_ADC_DAC_CONTROL_2, reg); 714 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
781 715
782 return 0; 716 return 0;
783} 717}
@@ -788,7 +722,7 @@ static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
788{ 722{
789 struct snd_soc_codec *codec = dai->codec; 723 struct snd_soc_codec *codec = dai->codec;
790 struct wm8961_priv *wm8961 = codec->private_data; 724 struct wm8961_priv *wm8961 = codec->private_data;
791 u16 reg = wm8961_read(codec, WM8961_CLOCKING1); 725 u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
792 726
793 if (freq > 33000000) { 727 if (freq > 33000000) {
794 dev_err(codec->dev, "MCLK must be <33MHz\n"); 728 dev_err(codec->dev, "MCLK must be <33MHz\n");
@@ -804,7 +738,7 @@ static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
804 reg &= WM8961_MCLKDIV; 738 reg &= WM8961_MCLKDIV;
805 } 739 }
806 740
807 wm8961_write(codec, WM8961_CLOCKING1, reg); 741 snd_soc_write(codec, WM8961_CLOCKING1, reg);
808 742
809 wm8961->sysclk = freq; 743 wm8961->sysclk = freq;
810 744
@@ -814,7 +748,7 @@ static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
814static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 748static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
815{ 749{
816 struct snd_soc_codec *codec = dai->codec; 750 struct snd_soc_codec *codec = dai->codec;
817 u16 aif = wm8961_read(codec, WM8961_AUDIO_INTERFACE_0); 751 u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
818 752
819 aif &= ~(WM8961_BCLKINV | WM8961_LRP | 753 aif &= ~(WM8961_BCLKINV | WM8961_LRP |
820 WM8961_MS | WM8961_FORMAT_MASK); 754 WM8961_MS | WM8961_FORMAT_MASK);
@@ -874,26 +808,26 @@ static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
874 return -EINVAL; 808 return -EINVAL;
875 } 809 }
876 810
877 return wm8961_write(codec, WM8961_AUDIO_INTERFACE_0, aif); 811 return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
878} 812}
879 813
880static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate) 814static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
881{ 815{
882 struct snd_soc_codec *codec = dai->codec; 816 struct snd_soc_codec *codec = dai->codec;
883 u16 reg = wm8961_read(codec, WM8961_ADDITIONAL_CONTROL_2); 817 u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
884 818
885 if (tristate) 819 if (tristate)
886 reg |= WM8961_TRIS; 820 reg |= WM8961_TRIS;
887 else 821 else
888 reg &= ~WM8961_TRIS; 822 reg &= ~WM8961_TRIS;
889 823
890 return wm8961_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg); 824 return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
891} 825}
892 826
893static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute) 827static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
894{ 828{
895 struct snd_soc_codec *codec = dai->codec; 829 struct snd_soc_codec *codec = dai->codec;
896 u16 reg = wm8961_read(codec, WM8961_ADC_DAC_CONTROL_1); 830 u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
897 831
898 if (mute) 832 if (mute)
899 reg |= WM8961_DACMU; 833 reg |= WM8961_DACMU;
@@ -902,7 +836,7 @@ static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
902 836
903 msleep(17); 837 msleep(17);
904 838
905 return wm8961_write(codec, WM8961_ADC_DAC_CONTROL_1, reg); 839 return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
906} 840}
907 841
908static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) 842static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
@@ -912,17 +846,17 @@ static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
912 846
913 switch (div_id) { 847 switch (div_id) {
914 case WM8961_BCLK: 848 case WM8961_BCLK:
915 reg = wm8961_read(codec, WM8961_CLOCKING2); 849 reg = snd_soc_read(codec, WM8961_CLOCKING2);
916 reg &= ~WM8961_BCLKDIV_MASK; 850 reg &= ~WM8961_BCLKDIV_MASK;
917 reg |= div; 851 reg |= div;
918 wm8961_write(codec, WM8961_CLOCKING2, reg); 852 snd_soc_write(codec, WM8961_CLOCKING2, reg);
919 break; 853 break;
920 854
921 case WM8961_LRCLK: 855 case WM8961_LRCLK:
922 reg = wm8961_read(codec, WM8961_AUDIO_INTERFACE_2); 856 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
923 reg &= ~WM8961_LRCLK_RATE_MASK; 857 reg &= ~WM8961_LRCLK_RATE_MASK;
924 reg |= div; 858 reg |= div;
925 wm8961_write(codec, WM8961_AUDIO_INTERFACE_2, reg); 859 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
926 break; 860 break;
927 861
928 default: 862 default:
@@ -949,34 +883,34 @@ static int wm8961_set_bias_level(struct snd_soc_codec *codec,
949 case SND_SOC_BIAS_PREPARE: 883 case SND_SOC_BIAS_PREPARE:
950 if (codec->bias_level == SND_SOC_BIAS_STANDBY) { 884 if (codec->bias_level == SND_SOC_BIAS_STANDBY) {
951 /* Enable bias generation */ 885 /* Enable bias generation */
952 reg = wm8961_read(codec, WM8961_ANTI_POP); 886 reg = snd_soc_read(codec, WM8961_ANTI_POP);
953 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN; 887 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
954 wm8961_write(codec, WM8961_ANTI_POP, reg); 888 snd_soc_write(codec, WM8961_ANTI_POP, reg);
955 889
956 /* VMID=2*50k, VREF */ 890 /* VMID=2*50k, VREF */
957 reg = wm8961_read(codec, WM8961_PWR_MGMT_1); 891 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
958 reg &= ~WM8961_VMIDSEL_MASK; 892 reg &= ~WM8961_VMIDSEL_MASK;
959 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF; 893 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
960 wm8961_write(codec, WM8961_PWR_MGMT_1, reg); 894 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
961 } 895 }
962 break; 896 break;
963 897
964 case SND_SOC_BIAS_STANDBY: 898 case SND_SOC_BIAS_STANDBY:
965 if (codec->bias_level == SND_SOC_BIAS_PREPARE) { 899 if (codec->bias_level == SND_SOC_BIAS_PREPARE) {
966 /* VREF off */ 900 /* VREF off */
967 reg = wm8961_read(codec, WM8961_PWR_MGMT_1); 901 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
968 reg &= ~WM8961_VREF; 902 reg &= ~WM8961_VREF;
969 wm8961_write(codec, WM8961_PWR_MGMT_1, reg); 903 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
970 904
971 /* Bias generation off */ 905 /* Bias generation off */
972 reg = wm8961_read(codec, WM8961_ANTI_POP); 906 reg = snd_soc_read(codec, WM8961_ANTI_POP);
973 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN); 907 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
974 wm8961_write(codec, WM8961_ANTI_POP, reg); 908 snd_soc_write(codec, WM8961_ANTI_POP, reg);
975 909
976 /* VMID off */ 910 /* VMID off */
977 reg = wm8961_read(codec, WM8961_PWR_MGMT_1); 911 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
978 reg &= ~WM8961_VMIDSEL_MASK; 912 reg &= ~WM8961_VMIDSEL_MASK;
979 wm8961_write(codec, WM8961_PWR_MGMT_1, reg); 913 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
980 } 914 }
981 break; 915 break;
982 916
@@ -1101,7 +1035,7 @@ static int wm8961_resume(struct platform_device *pdev)
1101 if (i == WM8961_SOFTWARE_RESET) 1035 if (i == WM8961_SOFTWARE_RESET)
1102 continue; 1036 continue;
1103 1037
1104 wm8961_write(codec, i, reg_cache[i]); 1038 snd_soc_write(codec, i, reg_cache[i]);
1105 } 1039 }
1106 1040
1107 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1041 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
@@ -1140,26 +1074,32 @@ static int wm8961_register(struct wm8961_priv *wm8961)
1140 codec->private_data = wm8961; 1074 codec->private_data = wm8961;
1141 codec->name = "WM8961"; 1075 codec->name = "WM8961";
1142 codec->owner = THIS_MODULE; 1076 codec->owner = THIS_MODULE;
1143 codec->read = wm8961_read;
1144 codec->write = wm8961_write;
1145 codec->dai = &wm8961_dai; 1077 codec->dai = &wm8961_dai;
1146 codec->num_dai = 1; 1078 codec->num_dai = 1;
1147 codec->reg_cache_size = ARRAY_SIZE(wm8961->reg_cache); 1079 codec->reg_cache_size = ARRAY_SIZE(wm8961->reg_cache);
1148 codec->reg_cache = &wm8961->reg_cache; 1080 codec->reg_cache = &wm8961->reg_cache;
1149 codec->bias_level = SND_SOC_BIAS_OFF; 1081 codec->bias_level = SND_SOC_BIAS_OFF;
1150 codec->set_bias_level = wm8961_set_bias_level; 1082 codec->set_bias_level = wm8961_set_bias_level;
1083 codec->volatile_register = wm8961_volatile_register;
1151 1084
1152 memcpy(codec->reg_cache, wm8961_reg_defaults, 1085 memcpy(codec->reg_cache, wm8961_reg_defaults,
1153 sizeof(wm8961_reg_defaults)); 1086 sizeof(wm8961_reg_defaults));
1154 1087
1155 reg = wm8961_read_hw(codec, WM8961_SOFTWARE_RESET); 1088 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1089 if (ret != 0) {
1090 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1091 goto err;
1092 }
1093
1094 reg = snd_soc_read(codec, WM8961_SOFTWARE_RESET);
1156 if (reg != 0x1801) { 1095 if (reg != 0x1801) {
1157 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg); 1096 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg);
1158 ret = -EINVAL; 1097 ret = -EINVAL;
1159 goto err; 1098 goto err;
1160 } 1099 }
1161 1100
1162 reg = wm8961_read_hw(codec, WM8961_RIGHT_INPUT_VOLUME); 1101 /* This isn't volatile - readback doesn't correspond to write */
1102 reg = codec->hw_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1163 dev_info(codec->dev, "WM8961 family %d revision %c\n", 1103 dev_info(codec->dev, "WM8961 family %d revision %c\n",
1164 (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT, 1104 (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
1165 ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT) 1105 ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
@@ -1172,37 +1112,37 @@ static int wm8961_register(struct wm8961_priv *wm8961)
1172 } 1112 }
1173 1113
1174 /* Enable class W */ 1114 /* Enable class W */
1175 reg = wm8961_read(codec, WM8961_CHARGE_PUMP_B); 1115 reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
1176 reg |= WM8961_CP_DYN_PWR_MASK; 1116 reg |= WM8961_CP_DYN_PWR_MASK;
1177 wm8961_write(codec, WM8961_CHARGE_PUMP_B, reg); 1117 snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
1178 1118
1179 /* Latch volume update bits (right channel only, we always 1119 /* Latch volume update bits (right channel only, we always
1180 * write both out) and default ZC on. */ 1120 * write both out) and default ZC on. */
1181 reg = wm8961_read(codec, WM8961_ROUT1_VOLUME); 1121 reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
1182 wm8961_write(codec, WM8961_ROUT1_VOLUME, 1122 snd_soc_write(codec, WM8961_ROUT1_VOLUME,
1183 reg | WM8961_LO1ZC | WM8961_OUT1VU); 1123 reg | WM8961_LO1ZC | WM8961_OUT1VU);
1184 wm8961_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC); 1124 snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
1185 reg = wm8961_read(codec, WM8961_ROUT2_VOLUME); 1125 reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
1186 wm8961_write(codec, WM8961_ROUT2_VOLUME, 1126 snd_soc_write(codec, WM8961_ROUT2_VOLUME,
1187 reg | WM8961_SPKRZC | WM8961_SPKVU); 1127 reg | WM8961_SPKRZC | WM8961_SPKVU);
1188 wm8961_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC); 1128 snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
1189 1129
1190 reg = wm8961_read(codec, WM8961_RIGHT_ADC_VOLUME); 1130 reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
1191 wm8961_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU); 1131 snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
1192 reg = wm8961_read(codec, WM8961_RIGHT_INPUT_VOLUME); 1132 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1193 wm8961_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU); 1133 snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
1194 1134
1195 /* Use soft mute by default */ 1135 /* Use soft mute by default */
1196 reg = wm8961_read(codec, WM8961_ADC_DAC_CONTROL_2); 1136 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
1197 reg |= WM8961_DACSMM; 1137 reg |= WM8961_DACSMM;
1198 wm8961_write(codec, WM8961_ADC_DAC_CONTROL_2, reg); 1138 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
1199 1139
1200 /* Use automatic clocking mode by default; for now this is all 1140 /* Use automatic clocking mode by default; for now this is all
1201 * we support. 1141 * we support.
1202 */ 1142 */
1203 reg = wm8961_read(codec, WM8961_CLOCKING_3); 1143 reg = snd_soc_read(codec, WM8961_CLOCKING_3);
1204 reg &= ~WM8961_MANUAL_MODE; 1144 reg &= ~WM8961_MANUAL_MODE;
1205 wm8961_write(codec, WM8961_CLOCKING_3, reg); 1145 snd_soc_write(codec, WM8961_CLOCKING_3, reg);
1206 1146
1207 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1147 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1208 1148
@@ -1250,7 +1190,6 @@ static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
1250 return -ENOMEM; 1190 return -ENOMEM;
1251 1191
1252 codec = &wm8961->codec; 1192 codec = &wm8961->codec;
1253 codec->hw_write = (hw_write_t)i2c_master_send;
1254 1193
1255 i2c_set_clientdata(i2c, wm8961); 1194 i2c_set_clientdata(i2c, wm8961);
1256 codec->control_data = i2c; 1195 codec->control_data = i2c;
diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c
index d029818350e9..2d702db4131d 100644
--- a/sound/soc/codecs/wm8990.c
+++ b/sound/soc/codecs/wm8990.c
@@ -108,53 +108,7 @@ static const u16 wm8990_reg[] = {
108 0x0000, /* R63 - Driver internal */ 108 0x0000, /* R63 - Driver internal */
109}; 109};
110 110
111/* 111#define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0)
112 * read wm8990 register cache
113 */
114static inline unsigned int wm8990_read_reg_cache(struct snd_soc_codec *codec,
115 unsigned int reg)
116{
117 u16 *cache = codec->reg_cache;
118 BUG_ON(reg >= ARRAY_SIZE(wm8990_reg));
119 return cache[reg];
120}
121
122/*
123 * write wm8990 register cache
124 */
125static inline void wm8990_write_reg_cache(struct snd_soc_codec *codec,
126 unsigned int reg, unsigned int value)
127{
128 u16 *cache = codec->reg_cache;
129
130 /* Reset register and reserved registers are uncached */
131 if (reg == 0 || reg >= ARRAY_SIZE(wm8990_reg))
132 return;
133
134 cache[reg] = value;
135}
136
137/*
138 * write to the wm8990 register space
139 */
140static int wm8990_write(struct snd_soc_codec *codec, unsigned int reg,
141 unsigned int value)
142{
143 u8 data[3];
144
145 data[0] = reg & 0xFF;
146 data[1] = (value >> 8) & 0xFF;
147 data[2] = value & 0xFF;
148
149 wm8990_write_reg_cache(codec, reg, value);
150
151 if (codec->hw_write(codec->control_data, data, 3) == 2)
152 return 0;
153 else
154 return -EIO;
155}
156
157#define wm8990_reset(c) wm8990_write(c, WM8990_RESET, 0)
158 112
159static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600); 113static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600);
160 114
@@ -187,8 +141,8 @@ static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
187 return ret; 141 return ret;
188 142
189 /* now hit the volume update bits (always bit 8) */ 143 /* now hit the volume update bits (always bit 8) */
190 val = wm8990_read_reg_cache(codec, reg); 144 val = snd_soc_read(codec, reg);
191 return wm8990_write(codec, reg, val | 0x0100); 145 return snd_soc_write(codec, reg, val | 0x0100);
192} 146}
193 147
194#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ 148#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
@@ -427,8 +381,8 @@ static int inmixer_event(struct snd_soc_dapm_widget *w,
427{ 381{
428 u16 reg, fakepower; 382 u16 reg, fakepower;
429 383
430 reg = wm8990_read_reg_cache(w->codec, WM8990_POWER_MANAGEMENT_2); 384 reg = snd_soc_read(w->codec, WM8990_POWER_MANAGEMENT_2);
431 fakepower = wm8990_read_reg_cache(w->codec, WM8990_INTDRIVBITS); 385 fakepower = snd_soc_read(w->codec, WM8990_INTDRIVBITS);
432 386
433 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) | 387 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) |
434 (1 << WM8990_AINLMUX_PWR_BIT))) { 388 (1 << WM8990_AINLMUX_PWR_BIT))) {
@@ -443,7 +397,7 @@ static int inmixer_event(struct snd_soc_dapm_widget *w,
443 } else { 397 } else {
444 reg &= ~WM8990_AINL_ENA; 398 reg &= ~WM8990_AINL_ENA;
445 } 399 }
446 wm8990_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg); 400 snd_soc_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg);
447 401
448 return 0; 402 return 0;
449} 403}
@@ -457,7 +411,7 @@ static int outmixer_event(struct snd_soc_dapm_widget *w,
457 411
458 switch (reg_shift) { 412 switch (reg_shift) {
459 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) : 413 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
460 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER1); 414 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1);
461 if (reg & WM8990_LDLO) { 415 if (reg & WM8990_LDLO) {
462 printk(KERN_WARNING 416 printk(KERN_WARNING
463 "Cannot set as Output Mixer 1 LDLO Set\n"); 417 "Cannot set as Output Mixer 1 LDLO Set\n");
@@ -465,7 +419,7 @@ static int outmixer_event(struct snd_soc_dapm_widget *w,
465 } 419 }
466 break; 420 break;
467 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8): 421 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
468 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER2); 422 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2);
469 if (reg & WM8990_RDRO) { 423 if (reg & WM8990_RDRO) {
470 printk(KERN_WARNING 424 printk(KERN_WARNING
471 "Cannot set as Output Mixer 2 RDRO Set\n"); 425 "Cannot set as Output Mixer 2 RDRO Set\n");
@@ -473,7 +427,7 @@ static int outmixer_event(struct snd_soc_dapm_widget *w,
473 } 427 }
474 break; 428 break;
475 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8): 429 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
476 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER); 430 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
477 if (reg & WM8990_LDSPK) { 431 if (reg & WM8990_LDSPK) {
478 printk(KERN_WARNING 432 printk(KERN_WARNING
479 "Cannot set as Speaker Mixer LDSPK Set\n"); 433 "Cannot set as Speaker Mixer LDSPK Set\n");
@@ -481,7 +435,7 @@ static int outmixer_event(struct snd_soc_dapm_widget *w,
481 } 435 }
482 break; 436 break;
483 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8): 437 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
484 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER); 438 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
485 if (reg & WM8990_RDSPK) { 439 if (reg & WM8990_RDSPK) {
486 printk(KERN_WARNING 440 printk(KERN_WARNING
487 "Cannot set as Speaker Mixer RDSPK Set\n"); 441 "Cannot set as Speaker Mixer RDSPK Set\n");
@@ -1029,24 +983,24 @@ static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai,
1029 pll_factors(&pll_div, freq_out * 4, freq_in); 983 pll_factors(&pll_div, freq_out * 4, freq_in);
1030 984
1031 /* Turn on PLL */ 985 /* Turn on PLL */
1032 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 986 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
1033 reg |= WM8990_PLL_ENA; 987 reg |= WM8990_PLL_ENA;
1034 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 988 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
1035 989
1036 /* sysclk comes from PLL */ 990 /* sysclk comes from PLL */
1037 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2); 991 reg = snd_soc_read(codec, WM8990_CLOCKING_2);
1038 wm8990_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC); 992 snd_soc_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC);
1039 993
1040 /* set up N , fractional mode and pre-divisor if neccessary */ 994 /* set up N , fractional mode and pre-divisor if neccessary */
1041 wm8990_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM | 995 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
1042 (pll_div.div2?WM8990_PRESCALE:0)); 996 (pll_div.div2?WM8990_PRESCALE:0));
1043 wm8990_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8)); 997 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
1044 wm8990_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF)); 998 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
1045 } else { 999 } else {
1046 /* Turn on PLL */ 1000 /* Turn on PLL */
1047 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1001 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
1048 reg &= ~WM8990_PLL_ENA; 1002 reg &= ~WM8990_PLL_ENA;
1049 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 1003 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
1050 } 1004 }
1051 return 0; 1005 return 0;
1052} 1006}
@@ -1073,8 +1027,8 @@ static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
1073 struct snd_soc_codec *codec = codec_dai->codec; 1027 struct snd_soc_codec *codec = codec_dai->codec;
1074 u16 audio1, audio3; 1028 u16 audio1, audio3;
1075 1029
1076 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1); 1030 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1077 audio3 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_3); 1031 audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3);
1078 1032
1079 /* set master/slave audio interface */ 1033 /* set master/slave audio interface */
1080 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1034 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -1115,8 +1069,8 @@ static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
1115 return -EINVAL; 1069 return -EINVAL;
1116 } 1070 }
1117 1071
1118 wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1072 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1119 wm8990_write(codec, WM8990_AUDIO_INTERFACE_3, audio3); 1073 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
1120 return 0; 1074 return 0;
1121} 1075}
1122 1076
@@ -1128,24 +1082,24 @@ static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1128 1082
1129 switch (div_id) { 1083 switch (div_id) {
1130 case WM8990_MCLK_DIV: 1084 case WM8990_MCLK_DIV:
1131 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1085 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
1132 ~WM8990_MCLK_DIV_MASK; 1086 ~WM8990_MCLK_DIV_MASK;
1133 wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1087 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
1134 break; 1088 break;
1135 case WM8990_DACCLK_DIV: 1089 case WM8990_DACCLK_DIV:
1136 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1090 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
1137 ~WM8990_DAC_CLKDIV_MASK; 1091 ~WM8990_DAC_CLKDIV_MASK;
1138 wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1092 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
1139 break; 1093 break;
1140 case WM8990_ADCCLK_DIV: 1094 case WM8990_ADCCLK_DIV:
1141 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1095 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
1142 ~WM8990_ADC_CLKDIV_MASK; 1096 ~WM8990_ADC_CLKDIV_MASK;
1143 wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1097 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
1144 break; 1098 break;
1145 case WM8990_BCLK_DIV: 1099 case WM8990_BCLK_DIV:
1146 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_1) & 1100 reg = snd_soc_read(codec, WM8990_CLOCKING_1) &
1147 ~WM8990_BCLK_DIV_MASK; 1101 ~WM8990_BCLK_DIV_MASK;
1148 wm8990_write(codec, WM8990_CLOCKING_1, reg | div); 1102 snd_soc_write(codec, WM8990_CLOCKING_1, reg | div);
1149 break; 1103 break;
1150 default: 1104 default:
1151 return -EINVAL; 1105 return -EINVAL;
@@ -1164,7 +1118,7 @@ static int wm8990_hw_params(struct snd_pcm_substream *substream,
1164 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1118 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1165 struct snd_soc_device *socdev = rtd->socdev; 1119 struct snd_soc_device *socdev = rtd->socdev;
1166 struct snd_soc_codec *codec = socdev->card->codec; 1120 struct snd_soc_codec *codec = socdev->card->codec;
1167 u16 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1); 1121 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1168 1122
1169 audio1 &= ~WM8990_AIF_WL_MASK; 1123 audio1 &= ~WM8990_AIF_WL_MASK;
1170 /* bit size */ 1124 /* bit size */
@@ -1182,7 +1136,7 @@ static int wm8990_hw_params(struct snd_pcm_substream *substream,
1182 break; 1136 break;
1183 } 1137 }
1184 1138
1185 wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1139 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1186 return 0; 1140 return 0;
1187} 1141}
1188 1142
@@ -1191,12 +1145,12 @@ static int wm8990_mute(struct snd_soc_dai *dai, int mute)
1191 struct snd_soc_codec *codec = dai->codec; 1145 struct snd_soc_codec *codec = dai->codec;
1192 u16 val; 1146 u16 val;
1193 1147
1194 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; 1148 val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1195 1149
1196 if (mute) 1150 if (mute)
1197 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1151 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1198 else 1152 else
1199 wm8990_write(codec, WM8990_DAC_CTRL, val); 1153 snd_soc_write(codec, WM8990_DAC_CTRL, val);
1200 1154
1201 return 0; 1155 return 0;
1202} 1156}
@@ -1212,21 +1166,21 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1212 1166
1213 case SND_SOC_BIAS_PREPARE: 1167 case SND_SOC_BIAS_PREPARE:
1214 /* VMID=2*50k */ 1168 /* VMID=2*50k */
1215 val = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_1) & 1169 val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) &
1216 ~WM8990_VMID_MODE_MASK; 1170 ~WM8990_VMID_MODE_MASK;
1217 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2); 1171 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2);
1218 break; 1172 break;
1219 1173
1220 case SND_SOC_BIAS_STANDBY: 1174 case SND_SOC_BIAS_STANDBY:
1221 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1175 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1222 /* Enable all output discharge bits */ 1176 /* Enable all output discharge bits */
1223 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1177 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1224 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1178 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1225 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1179 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1226 WM8990_DIS_ROUT); 1180 WM8990_DIS_ROUT);
1227 1181
1228 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1182 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1229 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1183 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1230 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1184 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1231 WM8990_VMIDTOG); 1185 WM8990_VMIDTOG);
1232 1186
@@ -1234,83 +1188,83 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1234 msleep(msecs_to_jiffies(300)); 1188 msleep(msecs_to_jiffies(300));
1235 1189
1236 /* Disable VMIDTOG */ 1190 /* Disable VMIDTOG */
1237 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1191 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1238 WM8990_BUFDCOPEN | WM8990_POBCTRL); 1192 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1239 1193
1240 /* disable all output discharge bits */ 1194 /* disable all output discharge bits */
1241 wm8990_write(codec, WM8990_ANTIPOP1, 0); 1195 snd_soc_write(codec, WM8990_ANTIPOP1, 0);
1242 1196
1243 /* Enable outputs */ 1197 /* Enable outputs */
1244 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00); 1198 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1245 1199
1246 msleep(msecs_to_jiffies(50)); 1200 msleep(msecs_to_jiffies(50));
1247 1201
1248 /* Enable VMID at 2x50k */ 1202 /* Enable VMID at 2x50k */
1249 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02); 1203 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1250 1204
1251 msleep(msecs_to_jiffies(100)); 1205 msleep(msecs_to_jiffies(100));
1252 1206
1253 /* Enable VREF */ 1207 /* Enable VREF */
1254 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1208 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1255 1209
1256 msleep(msecs_to_jiffies(600)); 1210 msleep(msecs_to_jiffies(600));
1257 1211
1258 /* Enable BUFIOEN */ 1212 /* Enable BUFIOEN */
1259 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1213 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1260 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1214 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1261 WM8990_BUFIOEN); 1215 WM8990_BUFIOEN);
1262 1216
1263 /* Disable outputs */ 1217 /* Disable outputs */
1264 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3); 1218 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
1265 1219
1266 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1220 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1267 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN); 1221 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
1268 1222
1269 /* Enable workaround for ADC clocking issue. */ 1223 /* Enable workaround for ADC clocking issue. */
1270 wm8990_write(codec, WM8990_EXT_ACCESS_ENA, 0x2); 1224 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2);
1271 wm8990_write(codec, WM8990_EXT_CTL1, 0xa003); 1225 snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003);
1272 wm8990_write(codec, WM8990_EXT_ACCESS_ENA, 0); 1226 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0);
1273 } 1227 }
1274 1228
1275 /* VMID=2*250k */ 1229 /* VMID=2*250k */
1276 val = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_1) & 1230 val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) &
1277 ~WM8990_VMID_MODE_MASK; 1231 ~WM8990_VMID_MODE_MASK;
1278 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4); 1232 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4);
1279 break; 1233 break;
1280 1234
1281 case SND_SOC_BIAS_OFF: 1235 case SND_SOC_BIAS_OFF:
1282 /* Enable POBCTRL and SOFT_ST */ 1236 /* Enable POBCTRL and SOFT_ST */
1283 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1237 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1284 WM8990_POBCTRL | WM8990_BUFIOEN); 1238 WM8990_POBCTRL | WM8990_BUFIOEN);
1285 1239
1286 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1240 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1287 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1241 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1288 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1242 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1289 WM8990_BUFIOEN); 1243 WM8990_BUFIOEN);
1290 1244
1291 /* mute DAC */ 1245 /* mute DAC */
1292 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL); 1246 val = snd_soc_read(codec, WM8990_DAC_CTRL);
1293 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1247 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1294 1248
1295 /* Enable any disabled outputs */ 1249 /* Enable any disabled outputs */
1296 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1250 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1297 1251
1298 /* Disable VMID */ 1252 /* Disable VMID */
1299 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01); 1253 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1300 1254
1301 msleep(msecs_to_jiffies(300)); 1255 msleep(msecs_to_jiffies(300));
1302 1256
1303 /* Enable all output discharge bits */ 1257 /* Enable all output discharge bits */
1304 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1258 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1305 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1259 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1306 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1260 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1307 WM8990_DIS_ROUT); 1261 WM8990_DIS_ROUT);
1308 1262
1309 /* Disable VREF */ 1263 /* Disable VREF */
1310 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0); 1264 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
1311 1265
1312 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1266 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1313 wm8990_write(codec, WM8990_ANTIPOP2, 0x0); 1267 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0);
1314 break; 1268 break;
1315 } 1269 }
1316 1270
@@ -1411,8 +1365,6 @@ static int wm8990_init(struct snd_soc_device *socdev)
1411 1365
1412 codec->name = "WM8990"; 1366 codec->name = "WM8990";
1413 codec->owner = THIS_MODULE; 1367 codec->owner = THIS_MODULE;
1414 codec->read = wm8990_read_reg_cache;
1415 codec->write = wm8990_write;
1416 codec->set_bias_level = wm8990_set_bias_level; 1368 codec->set_bias_level = wm8990_set_bias_level;
1417 codec->dai = &wm8990_dai; 1369 codec->dai = &wm8990_dai;
1418 codec->num_dai = 2; 1370 codec->num_dai = 2;
@@ -1422,6 +1374,12 @@ static int wm8990_init(struct snd_soc_device *socdev)
1422 if (codec->reg_cache == NULL) 1374 if (codec->reg_cache == NULL)
1423 return -ENOMEM; 1375 return -ENOMEM;
1424 1376
1377 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1378 if (ret < 0) {
1379 printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret);
1380 goto pcm_err;
1381 }
1382
1425 wm8990_reset(codec); 1383 wm8990_reset(codec);
1426 1384
1427 /* register pcms */ 1385 /* register pcms */
@@ -1435,18 +1393,18 @@ static int wm8990_init(struct snd_soc_device *socdev)
1435 codec->bias_level = SND_SOC_BIAS_OFF; 1393 codec->bias_level = SND_SOC_BIAS_OFF;
1436 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1394 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1437 1395
1438 reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_4); 1396 reg = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_4);
1439 wm8990_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1); 1397 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1);
1440 1398
1441 reg = wm8990_read_reg_cache(codec, WM8990_GPIO1_GPIO2) & 1399 reg = snd_soc_read(codec, WM8990_GPIO1_GPIO2) &
1442 ~WM8990_GPIO1_SEL_MASK; 1400 ~WM8990_GPIO1_SEL_MASK;
1443 wm8990_write(codec, WM8990_GPIO1_GPIO2, reg | 1); 1401 snd_soc_write(codec, WM8990_GPIO1_GPIO2, reg | 1);
1444 1402
1445 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1403 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
1446 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA); 1404 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA);
1447 1405
1448 wm8990_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1406 snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1449 wm8990_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1407 snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1450 1408
1451 snd_soc_add_controls(codec, wm8990_snd_controls, 1409 snd_soc_add_controls(codec, wm8990_snd_controls,
1452 ARRAY_SIZE(wm8990_snd_controls)); 1410 ARRAY_SIZE(wm8990_snd_controls));
diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c
index dbe20597d872..dc383c29cce5 100644
--- a/sound/soc/codecs/wm9081.c
+++ b/sound/soc/codecs/wm9081.c
@@ -168,84 +168,19 @@ struct wm9081_priv {
168 struct wm9081_retune_mobile_config *retune; 168 struct wm9081_retune_mobile_config *retune;
169}; 169};
170 170
171static int wm9081_reg_is_volatile(int reg) 171static int wm9081_volatile_register(unsigned int reg)
172{ 172{
173 switch (reg) { 173 switch (reg) {
174 case WM9081_SOFTWARE_RESET:
175 return 1;
174 default: 176 default:
175 return 0; 177 return 0;
176 } 178 }
177} 179}
178 180
179static unsigned int wm9081_read_reg_cache(struct snd_soc_codec *codec,
180 unsigned int reg)
181{
182 u16 *cache = codec->reg_cache;
183 BUG_ON(reg > WM9081_MAX_REGISTER);
184 return cache[reg];
185}
186
187static unsigned int wm9081_read_hw(struct snd_soc_codec *codec, u8 reg)
188{
189 struct i2c_msg xfer[2];
190 u16 data;
191 int ret;
192 struct i2c_client *client = codec->control_data;
193
194 BUG_ON(reg > WM9081_MAX_REGISTER);
195
196 /* Write register */
197 xfer[0].addr = client->addr;
198 xfer[0].flags = 0;
199 xfer[0].len = 1;
200 xfer[0].buf = &reg;
201
202 /* Read data */
203 xfer[1].addr = client->addr;
204 xfer[1].flags = I2C_M_RD;
205 xfer[1].len = 2;
206 xfer[1].buf = (u8 *)&data;
207
208 ret = i2c_transfer(client->adapter, xfer, 2);
209 if (ret != 2) {
210 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
211 return 0;
212 }
213
214 return (data >> 8) | ((data & 0xff) << 8);
215}
216
217static unsigned int wm9081_read(struct snd_soc_codec *codec, unsigned int reg)
218{
219 if (wm9081_reg_is_volatile(reg))
220 return wm9081_read_hw(codec, reg);
221 else
222 return wm9081_read_reg_cache(codec, reg);
223}
224
225static int wm9081_write(struct snd_soc_codec *codec, unsigned int reg,
226 unsigned int value)
227{
228 u16 *cache = codec->reg_cache;
229 u8 data[3];
230
231 BUG_ON(reg > WM9081_MAX_REGISTER);
232
233 if (!wm9081_reg_is_volatile(reg))
234 cache[reg] = value;
235
236 data[0] = reg;
237 data[1] = value >> 8;
238 data[2] = value & 0x00ff;
239
240 if (codec->hw_write(codec->control_data, data, 3) == 3)
241 return 0;
242 else
243 return -EIO;
244}
245
246static int wm9081_reset(struct snd_soc_codec *codec) 181static int wm9081_reset(struct snd_soc_codec *codec)
247{ 182{
248 return wm9081_write(codec, WM9081_SOFTWARE_RESET, 0); 183 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
249} 184}
250 185
251static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0); 186static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
@@ -356,7 +291,7 @@ static int speaker_mode_get(struct snd_kcontrol *kcontrol,
356 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 291 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
357 unsigned int reg; 292 unsigned int reg;
358 293
359 reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2); 294 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
360 if (reg & WM9081_SPK_MODE) 295 if (reg & WM9081_SPK_MODE)
361 ucontrol->value.integer.value[0] = 1; 296 ucontrol->value.integer.value[0] = 1;
362 else 297 else
@@ -375,8 +310,8 @@ static int speaker_mode_put(struct snd_kcontrol *kcontrol,
375 struct snd_ctl_elem_value *ucontrol) 310 struct snd_ctl_elem_value *ucontrol)
376{ 311{
377 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 312 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
378 unsigned int reg_pwr = wm9081_read(codec, WM9081_POWER_MANAGEMENT); 313 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
379 unsigned int reg2 = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2); 314 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
380 315
381 /* Are we changing anything? */ 316 /* Are we changing anything? */
382 if (ucontrol->value.integer.value[0] == 317 if (ucontrol->value.integer.value[0] ==
@@ -397,7 +332,7 @@ static int speaker_mode_put(struct snd_kcontrol *kcontrol,
397 reg2 &= ~WM9081_SPK_MODE; 332 reg2 &= ~WM9081_SPK_MODE;
398 } 333 }
399 334
400 wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2); 335 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
401 336
402 return 0; 337 return 0;
403} 338}
@@ -456,7 +391,7 @@ static int speaker_event(struct snd_soc_dapm_widget *w,
456 struct snd_kcontrol *kcontrol, int event) 391 struct snd_kcontrol *kcontrol, int event)
457{ 392{
458 struct snd_soc_codec *codec = w->codec; 393 struct snd_soc_codec *codec = w->codec;
459 unsigned int reg = wm9081_read(codec, WM9081_POWER_MANAGEMENT); 394 unsigned int reg = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
460 395
461 switch (event) { 396 switch (event) {
462 case SND_SOC_DAPM_POST_PMU: 397 case SND_SOC_DAPM_POST_PMU:
@@ -468,7 +403,7 @@ static int speaker_event(struct snd_soc_dapm_widget *w,
468 break; 403 break;
469 } 404 }
470 405
471 wm9081_write(codec, WM9081_POWER_MANAGEMENT, reg); 406 snd_soc_write(codec, WM9081_POWER_MANAGEMENT, reg);
472 407
473 return 0; 408 return 0;
474} 409}
@@ -607,7 +542,7 @@ static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
607 if (ret != 0) 542 if (ret != 0)
608 return ret; 543 return ret;
609 544
610 reg5 = wm9081_read(codec, WM9081_FLL_CONTROL_5); 545 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
611 reg5 &= ~WM9081_FLL_CLK_SRC_MASK; 546 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
612 547
613 switch (fll_id) { 548 switch (fll_id) {
@@ -621,44 +556,44 @@ static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
621 } 556 }
622 557
623 /* Disable CLK_SYS while we reconfigure */ 558 /* Disable CLK_SYS while we reconfigure */
624 clk_sys_reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3); 559 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
625 if (clk_sys_reg & WM9081_CLK_SYS_ENA) 560 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
626 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, 561 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
627 clk_sys_reg & ~WM9081_CLK_SYS_ENA); 562 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
628 563
629 /* Any FLL configuration change requires that the FLL be 564 /* Any FLL configuration change requires that the FLL be
630 * disabled first. */ 565 * disabled first. */
631 reg1 = wm9081_read(codec, WM9081_FLL_CONTROL_1); 566 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
632 reg1 &= ~WM9081_FLL_ENA; 567 reg1 &= ~WM9081_FLL_ENA;
633 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1); 568 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
634 569
635 /* Apply the configuration */ 570 /* Apply the configuration */
636 if (fll_div.k) 571 if (fll_div.k)
637 reg1 |= WM9081_FLL_FRAC_MASK; 572 reg1 |= WM9081_FLL_FRAC_MASK;
638 else 573 else
639 reg1 &= ~WM9081_FLL_FRAC_MASK; 574 reg1 &= ~WM9081_FLL_FRAC_MASK;
640 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1); 575 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
641 576
642 wm9081_write(codec, WM9081_FLL_CONTROL_2, 577 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
643 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) | 578 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
644 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT)); 579 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
645 wm9081_write(codec, WM9081_FLL_CONTROL_3, fll_div.k); 580 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
646 581
647 reg4 = wm9081_read(codec, WM9081_FLL_CONTROL_4); 582 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
648 reg4 &= ~WM9081_FLL_N_MASK; 583 reg4 &= ~WM9081_FLL_N_MASK;
649 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT; 584 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
650 wm9081_write(codec, WM9081_FLL_CONTROL_4, reg4); 585 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
651 586
652 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK; 587 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
653 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT; 588 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
654 wm9081_write(codec, WM9081_FLL_CONTROL_5, reg5); 589 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
655 590
656 /* Enable the FLL */ 591 /* Enable the FLL */
657 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA); 592 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
658 593
659 /* Then bring CLK_SYS up again if it was disabled */ 594 /* Then bring CLK_SYS up again if it was disabled */
660 if (clk_sys_reg & WM9081_CLK_SYS_ENA) 595 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
661 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg); 596 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
662 597
663 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); 598 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
664 599
@@ -734,19 +669,19 @@ static int configure_clock(struct snd_soc_codec *codec)
734 return -EINVAL; 669 return -EINVAL;
735 } 670 }
736 671
737 reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_1); 672 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
738 if (mclkdiv) 673 if (mclkdiv)
739 reg |= WM9081_MCLKDIV2; 674 reg |= WM9081_MCLKDIV2;
740 else 675 else
741 reg &= ~WM9081_MCLKDIV2; 676 reg &= ~WM9081_MCLKDIV2;
742 wm9081_write(codec, WM9081_CLOCK_CONTROL_1, reg); 677 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
743 678
744 reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3); 679 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
745 if (fll) 680 if (fll)
746 reg |= WM9081_CLK_SRC_SEL; 681 reg |= WM9081_CLK_SRC_SEL;
747 else 682 else
748 reg &= ~WM9081_CLK_SRC_SEL; 683 reg &= ~WM9081_CLK_SRC_SEL;
749 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, reg); 684 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
750 685
751 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate); 686 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
752 687
@@ -846,76 +781,76 @@ static int wm9081_set_bias_level(struct snd_soc_codec *codec,
846 781
847 case SND_SOC_BIAS_PREPARE: 782 case SND_SOC_BIAS_PREPARE:
848 /* VMID=2*40k */ 783 /* VMID=2*40k */
849 reg = wm9081_read(codec, WM9081_VMID_CONTROL); 784 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
850 reg &= ~WM9081_VMID_SEL_MASK; 785 reg &= ~WM9081_VMID_SEL_MASK;
851 reg |= 0x2; 786 reg |= 0x2;
852 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 787 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
853 788
854 /* Normal bias current */ 789 /* Normal bias current */
855 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 790 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
856 reg &= ~WM9081_STBY_BIAS_ENA; 791 reg &= ~WM9081_STBY_BIAS_ENA;
857 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 792 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
858 break; 793 break;
859 794
860 case SND_SOC_BIAS_STANDBY: 795 case SND_SOC_BIAS_STANDBY:
861 /* Initial cold start */ 796 /* Initial cold start */
862 if (codec->bias_level == SND_SOC_BIAS_OFF) { 797 if (codec->bias_level == SND_SOC_BIAS_OFF) {
863 /* Disable LINEOUT discharge */ 798 /* Disable LINEOUT discharge */
864 reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL); 799 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
865 reg &= ~WM9081_LINEOUT_DISCH; 800 reg &= ~WM9081_LINEOUT_DISCH;
866 wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg); 801 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
867 802
868 /* Select startup bias source */ 803 /* Select startup bias source */
869 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 804 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
870 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA; 805 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
871 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 806 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
872 807
873 /* VMID 2*4k; Soft VMID ramp enable */ 808 /* VMID 2*4k; Soft VMID ramp enable */
874 reg = wm9081_read(codec, WM9081_VMID_CONTROL); 809 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
875 reg |= WM9081_VMID_RAMP | 0x6; 810 reg |= WM9081_VMID_RAMP | 0x6;
876 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 811 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
877 812
878 mdelay(100); 813 mdelay(100);
879 814
880 /* Normal bias enable & soft start off */ 815 /* Normal bias enable & soft start off */
881 reg |= WM9081_BIAS_ENA; 816 reg |= WM9081_BIAS_ENA;
882 reg &= ~WM9081_VMID_RAMP; 817 reg &= ~WM9081_VMID_RAMP;
883 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 818 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
884 819
885 /* Standard bias source */ 820 /* Standard bias source */
886 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 821 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
887 reg &= ~WM9081_BIAS_SRC; 822 reg &= ~WM9081_BIAS_SRC;
888 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 823 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
889 } 824 }
890 825
891 /* VMID 2*240k */ 826 /* VMID 2*240k */
892 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 827 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
893 reg &= ~WM9081_VMID_SEL_MASK; 828 reg &= ~WM9081_VMID_SEL_MASK;
894 reg |= 0x40; 829 reg |= 0x40;
895 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 830 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
896 831
897 /* Standby bias current on */ 832 /* Standby bias current on */
898 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 833 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
899 reg |= WM9081_STBY_BIAS_ENA; 834 reg |= WM9081_STBY_BIAS_ENA;
900 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 835 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
901 break; 836 break;
902 837
903 case SND_SOC_BIAS_OFF: 838 case SND_SOC_BIAS_OFF:
904 /* Startup bias source */ 839 /* Startup bias source */
905 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 840 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
906 reg |= WM9081_BIAS_SRC; 841 reg |= WM9081_BIAS_SRC;
907 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 842 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
908 843
909 /* Disable VMID and biases with soft ramping */ 844 /* Disable VMID and biases with soft ramping */
910 reg = wm9081_read(codec, WM9081_VMID_CONTROL); 845 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
911 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA); 846 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
912 reg |= WM9081_VMID_RAMP; 847 reg |= WM9081_VMID_RAMP;
913 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 848 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
914 849
915 /* Actively discharge LINEOUT */ 850 /* Actively discharge LINEOUT */
916 reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL); 851 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
917 reg |= WM9081_LINEOUT_DISCH; 852 reg |= WM9081_LINEOUT_DISCH;
918 wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg); 853 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
919 break; 854 break;
920 } 855 }
921 856
@@ -929,7 +864,7 @@ static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
929{ 864{
930 struct snd_soc_codec *codec = dai->codec; 865 struct snd_soc_codec *codec = dai->codec;
931 struct wm9081_priv *wm9081 = codec->private_data; 866 struct wm9081_priv *wm9081 = codec->private_data;
932 unsigned int aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2); 867 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
933 868
934 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV | 869 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
935 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK); 870 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
@@ -1010,7 +945,7 @@ static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
1010 return -EINVAL; 945 return -EINVAL;
1011 } 946 }
1012 947
1013 wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2); 948 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1014 949
1015 return 0; 950 return 0;
1016} 951}
@@ -1024,18 +959,18 @@ static int wm9081_hw_params(struct snd_pcm_substream *substream,
1024 int ret, i, best, best_val, cur_val; 959 int ret, i, best, best_val, cur_val;
1025 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4; 960 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
1026 961
1027 clk_ctrl2 = wm9081_read(codec, WM9081_CLOCK_CONTROL_2); 962 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
1028 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK); 963 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
1029 964
1030 aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1); 965 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1031 966
1032 aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2); 967 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
1033 aif2 &= ~WM9081_AIF_WL_MASK; 968 aif2 &= ~WM9081_AIF_WL_MASK;
1034 969
1035 aif3 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_3); 970 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
1036 aif3 &= ~WM9081_BCLK_DIV_MASK; 971 aif3 &= ~WM9081_BCLK_DIV_MASK;
1037 972
1038 aif4 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_4); 973 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
1039 aif4 &= ~WM9081_LRCLK_RATE_MASK; 974 aif4 &= ~WM9081_LRCLK_RATE_MASK;
1040 975
1041 /* What BCLK do we need? */ 976 /* What BCLK do we need? */
@@ -1149,22 +1084,22 @@ static int wm9081_hw_params(struct snd_pcm_substream *substream,
1149 s->name, s->rate); 1084 s->name, s->rate);
1150 1085
1151 /* If the EQ is enabled then disable it while we write out */ 1086 /* If the EQ is enabled then disable it while we write out */
1152 eq1 = wm9081_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA; 1087 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
1153 if (eq1 & WM9081_EQ_ENA) 1088 if (eq1 & WM9081_EQ_ENA)
1154 wm9081_write(codec, WM9081_EQ_1, 0); 1089 snd_soc_write(codec, WM9081_EQ_1, 0);
1155 1090
1156 /* Write out the other values */ 1091 /* Write out the other values */
1157 for (i = 1; i < ARRAY_SIZE(s->config); i++) 1092 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1158 wm9081_write(codec, WM9081_EQ_1 + i, s->config[i]); 1093 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
1159 1094
1160 eq1 |= (s->config[0] & ~WM9081_EQ_ENA); 1095 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1161 wm9081_write(codec, WM9081_EQ_1, eq1); 1096 snd_soc_write(codec, WM9081_EQ_1, eq1);
1162 } 1097 }
1163 1098
1164 wm9081_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2); 1099 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1165 wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2); 1100 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1166 wm9081_write(codec, WM9081_AUDIO_INTERFACE_3, aif3); 1101 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1167 wm9081_write(codec, WM9081_AUDIO_INTERFACE_4, aif4); 1102 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
1168 1103
1169 return 0; 1104 return 0;
1170} 1105}
@@ -1174,14 +1109,14 @@ static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1174 struct snd_soc_codec *codec = codec_dai->codec; 1109 struct snd_soc_codec *codec = codec_dai->codec;
1175 unsigned int reg; 1110 unsigned int reg;
1176 1111
1177 reg = wm9081_read(codec, WM9081_DAC_DIGITAL_2); 1112 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
1178 1113
1179 if (mute) 1114 if (mute)
1180 reg |= WM9081_DAC_MUTE; 1115 reg |= WM9081_DAC_MUTE;
1181 else 1116 else
1182 reg &= ~WM9081_DAC_MUTE; 1117 reg &= ~WM9081_DAC_MUTE;
1183 1118
1184 wm9081_write(codec, WM9081_DAC_DIGITAL_2, reg); 1119 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
1185 1120
1186 return 0; 1121 return 0;
1187} 1122}
@@ -1210,7 +1145,7 @@ static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1210 unsigned int mask, int slots) 1145 unsigned int mask, int slots)
1211{ 1146{
1212 struct snd_soc_codec *codec = dai->codec; 1147 struct snd_soc_codec *codec = dai->codec;
1213 unsigned int aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1); 1148 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1214 1149
1215 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK); 1150 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1216 1151
@@ -1235,7 +1170,7 @@ static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1235 return -EINVAL; 1170 return -EINVAL;
1236 } 1171 }
1237 1172
1238 wm9081_write(codec, WM9081_AUDIO_INTERFACE_1, aif1); 1173 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
1239 1174
1240 return 0; 1175 return 0;
1241} 1176}
@@ -1357,7 +1292,7 @@ static int wm9081_resume(struct platform_device *pdev)
1357 if (i == WM9081_SOFTWARE_RESET) 1292 if (i == WM9081_SOFTWARE_RESET)
1358 continue; 1293 continue;
1359 1294
1360 wm9081_write(codec, i, reg_cache[i]); 1295 snd_soc_write(codec, i, reg_cache[i]);
1361 } 1296 }
1362 1297
1363 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1298 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
@@ -1377,7 +1312,8 @@ struct snd_soc_codec_device soc_codec_dev_wm9081 = {
1377}; 1312};
1378EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081); 1313EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081);
1379 1314
1380static int wm9081_register(struct wm9081_priv *wm9081) 1315static int wm9081_register(struct wm9081_priv *wm9081,
1316 enum snd_soc_control_type control)
1381{ 1317{
1382 struct snd_soc_codec *codec = &wm9081->codec; 1318 struct snd_soc_codec *codec = &wm9081->codec;
1383 int ret; 1319 int ret;
@@ -1396,19 +1332,24 @@ static int wm9081_register(struct wm9081_priv *wm9081)
1396 codec->private_data = wm9081; 1332 codec->private_data = wm9081;
1397 codec->name = "WM9081"; 1333 codec->name = "WM9081";
1398 codec->owner = THIS_MODULE; 1334 codec->owner = THIS_MODULE;
1399 codec->read = wm9081_read;
1400 codec->write = wm9081_write;
1401 codec->dai = &wm9081_dai; 1335 codec->dai = &wm9081_dai;
1402 codec->num_dai = 1; 1336 codec->num_dai = 1;
1403 codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache); 1337 codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache);
1404 codec->reg_cache = &wm9081->reg_cache; 1338 codec->reg_cache = &wm9081->reg_cache;
1405 codec->bias_level = SND_SOC_BIAS_OFF; 1339 codec->bias_level = SND_SOC_BIAS_OFF;
1406 codec->set_bias_level = wm9081_set_bias_level; 1340 codec->set_bias_level = wm9081_set_bias_level;
1341 codec->volatile_register = wm9081_volatile_register;
1407 1342
1408 memcpy(codec->reg_cache, wm9081_reg_defaults, 1343 memcpy(codec->reg_cache, wm9081_reg_defaults,
1409 sizeof(wm9081_reg_defaults)); 1344 sizeof(wm9081_reg_defaults));
1410 1345
1411 reg = wm9081_read_hw(codec, WM9081_SOFTWARE_RESET); 1346 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
1347 if (ret != 0) {
1348 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1349 return ret;
1350 }
1351
1352 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
1412 if (reg != 0x9081) { 1353 if (reg != 0x9081) {
1413 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg); 1354 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1414 ret = -EINVAL; 1355 ret = -EINVAL;
@@ -1424,10 +1365,10 @@ static int wm9081_register(struct wm9081_priv *wm9081)
1424 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1365 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1425 1366
1426 /* Enable zero cross by default */ 1367 /* Enable zero cross by default */
1427 reg = wm9081_read(codec, WM9081_ANALOGUE_LINEOUT); 1368 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1428 wm9081_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC); 1369 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1429 reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_PGA); 1370 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1430 wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_PGA, 1371 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1431 reg | WM9081_SPKPGAZC); 1372 reg | WM9081_SPKPGAZC);
1432 1373
1433 wm9081_dai.dev = codec->dev; 1374 wm9081_dai.dev = codec->dev;
@@ -1482,7 +1423,7 @@ static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1482 1423
1483 codec->dev = &i2c->dev; 1424 codec->dev = &i2c->dev;
1484 1425
1485 return wm9081_register(wm9081); 1426 return wm9081_register(wm9081, SND_SOC_I2C);
1486} 1427}
1487 1428
1488static __devexit int wm9081_i2c_remove(struct i2c_client *client) 1429static __devexit int wm9081_i2c_remove(struct i2c_client *client)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 08:16:46 -0500