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authorMike Frysinger <michael.frysinger@analog.com>2007-06-11 03:31:30 -0400
committerBryan Wu <bryan.wu@analog.com>2007-06-11 03:31:30 -0400
commit83a5c3e3218f138b1a99f787c76e380d6a6ecec9 (patch)
treed71fb83fb0406af38d4e3266cb2d54dabb1bb3eb
parent16983de0cec7b93cc2568f96909d4ea7c118bd8a (diff)
Blackfin arch: unify differences between our diff head.S files -- no functional changes
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
-rw-r--r--arch/blackfin/mach-bf533/head.S17
-rw-r--r--arch/blackfin/mach-bf537/head.S22
-rw-r--r--arch/blackfin/mach-bf561/head.S20
3 files changed, 32 insertions, 27 deletions
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 4db9e6240906..33d1f623fe4e 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -51,13 +51,14 @@ ENTRY(__start)
51ENTRY(__stext) 51ENTRY(__stext)
52 /* R0: argument of command line string, passed from uboot, save it */ 52 /* R0: argument of command line string, passed from uboot, save it */
53 R7 = R0; 53 R7 = R0;
54 /* Set the SYSCFG register */ 54 /* Set the SYSCFG register:
55 * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
56 */
55 R0 = 0x36; 57 R0 = 0x36;
56 /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
57 SYSCFG = R0; 58 SYSCFG = R0;
58 R0 = 0; 59 R0 = 0;
59 60
60 /*Clear Out All the data and pointer Registers*/ 61 /* Clear Out All the data and pointer Registers */
61 R1 = R0; 62 R1 = R0;
62 R2 = R0; 63 R2 = R0;
63 R3 = R0; 64 R3 = R0;
@@ -79,7 +80,7 @@ ENTRY(__stext)
79 L2 = r0; 80 L2 = r0;
80 L3 = r0; 81 L3 = r0;
81 82
82 /* Clear Out All the DAG Registers*/ 83 /* Clear Out All the DAG Registers */
83 B0 = r0; 84 B0 = r0;
84 B1 = r0; 85 B1 = r0;
85 B2 = r0; 86 B2 = r0;
@@ -303,7 +304,7 @@ ENTRY(_real_start)
303.L_clear_zero: 304.L_clear_zero:
304 W[p1++] = r0; 305 W[p1++] = r0;
305 306
306/* pass the uboot arguments to the global value command line */ 307 /* pass the uboot arguments to the global value command line */
307 R0 = R7; 308 R0 = R7;
308 call _cmdline_init; 309 call _cmdline_init;
309 310
@@ -322,7 +323,7 @@ ENTRY(_real_start)
322 [p1] = r1; 323 [p1] = r1;
323 324
324 /* 325 /*
325 * load the current thread pointer and stack 326 * load the current thread pointer and stack
326 */ 327 */
327 r1.l = _init_thread_union; 328 r1.l = _init_thread_union;
328 r1.h = _init_thread_union; 329 r1.h = _init_thread_union;
@@ -439,8 +440,8 @@ ENTRY(_start_dma_code)
439 440
440 p0.h = hi(SIC_IWR); 441 p0.h = hi(SIC_IWR);
441 p0.l = lo(SIC_IWR); 442 p0.l = lo(SIC_IWR);
442 r0.l = lo(IWR_ENABLE_ALL) 443 r0.l = lo(IWR_ENABLE_ALL);
443 r0.h = hi(IWR_ENABLE_ALL) 444 r0.h = hi(IWR_ENABLE_ALL);
444 [p0] = r0; 445 [p0] = r0;
445 SSYNC; 446 SSYNC;
446 447
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 2c2652bee7e5..3f490bfb73fa 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -40,7 +40,7 @@
40.extern ___bss_start 40.extern ___bss_start
41.extern _bf53x_relocate_l1_mem 41.extern _bf53x_relocate_l1_mem
42 42
43#define INITIAL_STACK 0xFFB01000 43#define INITIAL_STACK 0xFFB01000
44 44
45.text 45.text
46 46
@@ -48,12 +48,14 @@ ENTRY(__start)
48ENTRY(__stext) 48ENTRY(__stext)
49 /* R0: argument of command line string, passed from uboot, save it */ 49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0; 50 R7 = R0;
51 /* Set the SYSCFG register */ 51 /* Set the SYSCFG register:
52 * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
53 */
52 R0 = 0x36; 54 R0 = 0x36;
53 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/ 55 SYSCFG = R0;
54 R0 = 0; 56 R0 = 0;
55 57
56 /* Clear Out All the data and pointer Registers*/ 58 /* Clear Out All the data and pointer Registers */
57 R1 = R0; 59 R1 = R0;
58 R2 = R0; 60 R2 = R0;
59 R3 = R0; 61 R3 = R0;
@@ -75,7 +77,7 @@ ENTRY(__stext)
75 L2 = r0; 77 L2 = r0;
76 L3 = r0; 78 L3 = r0;
77 79
78 /* Clear Out All the DAG Registers*/ 80 /* Clear Out All the DAG Registers */
79 B0 = r0; 81 B0 = r0;
80 B1 = r0; 82 B1 = r0;
81 B2 = r0; 83 B2 = r0;
@@ -191,7 +193,7 @@ ENTRY(__stext)
191 193
192 p0.h = hi(UART_DLL); 194 p0.h = hi(UART_DLL);
193 p0.l = lo(UART_DLL); 195 p0.l = lo(UART_DLL);
194 r0 = 0x00(Z); 196 r0 = 0x0(Z);
195 w[p0] = r0.L; 197 w[p0] = r0.L;
196 ssync; 198 ssync;
197 199
@@ -218,6 +220,7 @@ ENTRY(__stext)
218#if CONFIG_BFIN_KERNEL_CLOCK 220#if CONFIG_BFIN_KERNEL_CLOCK
219 call _start_dma_code; 221 call _start_dma_code;
220#endif 222#endif
223
221 /* Code for initializing Async memory banks */ 224 /* Code for initializing Async memory banks */
222 225
223 p2.h = hi(EBIU_AMBCTL1); 226 p2.h = hi(EBIU_AMBCTL1);
@@ -291,7 +294,7 @@ ENTRY(_real_start)
291 p2.h = ___bss_stop; 294 p2.h = ___bss_stop;
292 r0 = 0; 295 r0 = 0;
293 p2 -= p1; 296 p2 -= p1;
294 lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2; 297 lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
295.L_clear_bss: 298.L_clear_bss:
296 B[p1++] = r0; 299 B[p1++] = r0;
297 300
@@ -306,7 +309,7 @@ ENTRY(_real_start)
306 r0 = r0 >> 1; 309 r0 = r0 >> 1;
307 p2 = r0; 310 p2 = r0;
308 r0 = 0; 311 r0 = 0;
309 lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2; 312 lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
310.L_clear_zero: 313.L_clear_zero:
311 W[p1++] = r0; 314 W[p1++] = r0;
312 315
@@ -328,9 +331,8 @@ ENTRY(_real_start)
328 r1 = p3; 331 r1 = p3;
329 [p1] = r1; 332 [p1] = r1;
330 333
331
332 /* 334 /*
333 * load the current thread pointer and stack 335 * load the current thread pointer and stack
334 */ 336 */
335 r1.l = _init_thread_union; 337 r1.l = _init_thread_union;
336 r1.h = _init_thread_union; 338 r1.h = _init_thread_union;
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index ad9187a866a5..3029e940ddcd 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -46,14 +46,16 @@
46 46
47ENTRY(__start) 47ENTRY(__start)
48ENTRY(__stext) 48ENTRY(__stext)
49 /* R0: argument of command line string, passed from uboot, save it */ 49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0; 50 R7 = R0;
51 /* Set the SYSCFG register */ 51 /* Set the SYSCFG register:
52 * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
53 */
52 R0 = 0x36; 54 R0 = 0x36;
53 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/ 55 SYSCFG = R0;
54 R0 = 0; 56 R0 = 0;
55 57
56 /*Clear Out All the data and pointer Registers*/ 58 /* Clear Out All the data and pointer Registers */
57 R1 = R0; 59 R1 = R0;
58 R2 = R0; 60 R2 = R0;
59 R3 = R0; 61 R3 = R0;
@@ -75,7 +77,7 @@ ENTRY(__stext)
75 L2 = r0; 77 L2 = r0;
76 L3 = r0; 78 L3 = r0;
77 79
78 /* Clear Out All the DAG Registers*/ 80 /* Clear Out All the DAG Registers */
79 B0 = r0; 81 B0 = r0;
80 B1 = r0; 82 B1 = r0;
81 B2 = r0; 83 B2 = r0;
@@ -238,7 +240,7 @@ ENTRY(_real_start)
238 p2.h = ___bss_stop; 240 p2.h = ___bss_stop;
239 r0 = 0; 241 r0 = 0;
240 p2 -= p1; 242 p2 -= p1;
241 lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2; 243 lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
242.L_clear_bss: 244.L_clear_bss:
243 B[p1++] = r0; 245 B[p1++] = r0;
244 246
@@ -253,11 +255,11 @@ ENTRY(_real_start)
253 r0 = r0 >> 1; 255 r0 = r0 >> 1;
254 p2 = r0; 256 p2 = r0;
255 r0 = 0; 257 r0 = 0;
256 lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2; 258 lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
257.L_clear_zero: 259.L_clear_zero:
258 W[p1++] = r0; 260 W[p1++] = r0;
259 261
260/* pass the uboot arguments to the global value command line */ 262 /* pass the uboot arguments to the global value command line */
261 R0 = R7; 263 R0 = R7;
262 call _cmdline_init; 264 call _cmdline_init;
263 265
@@ -350,7 +352,7 @@ ENTRY(_start_dma_code)
350 if ! CC jump .Lcheck_again; 352 if ! CC jump .Lcheck_again;
351 353
352 /* Configure SCLK & CCLK Dividers */ 354 /* Configure SCLK & CCLK Dividers */
353 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV); 355 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
354 p0.h = hi(PLL_DIV); 356 p0.h = hi(PLL_DIV);
355 p0.l = lo(PLL_DIV); 357 p0.l = lo(PLL_DIV);
356 w[p0] = r0.l; 358 w[p0] = r0.l;