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authorMark Brown <broonie@opensource.wolfsonmicro.com>2009-07-27 09:45:53 -0400
committerSamuel Ortiz <sameo@linux.intel.com>2009-09-17 03:46:57 -0400
commit7d4d0a3e7343e3190afaa17253073db58e3d9bff (patch)
tree586ad0e591e512a567e90588a35670034fd2a6ff
parentd2bedfe7a8b2f34beee2cad9cae74a088ee8ed07 (diff)
mfd: Add WM831x interrupt support
The WM831x includes an interrupt controller managing interrupts for the various functions on the chip. This patch adds support for the core interrupt block on the device. Ideally this would be supported by genirq, particularly for the GPIOs, but currently genirq is unable to cope with controllers on interrupt driven buses so we cut'n'paste the generic interface. Once genirq is able to cope chips like this it should be a case of filing the prefixes off the code and redoing wm831x-irq.c to move over. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat
-rw-r--r--drivers/mfd/wm831x-core.c12
-rw-r--r--drivers/mfd/wm831x-irq.c559
-rw-r--r--include/linux/mfd/wm831x/core.h21
-rw-r--r--include/linux/mfd/wm831x/irq.h764
4 files changed, 1354 insertions, 2 deletions
diff --git a/drivers/mfd/wm831x-core.c b/drivers/mfd/wm831x-core.c
index cc1040c9d46c..eb63d22160d1 100644
--- a/drivers/mfd/wm831x-core.c
+++ b/drivers/mfd/wm831x-core.c
@@ -19,6 +19,7 @@
19 19
20#include <linux/mfd/wm831x/core.h> 20#include <linux/mfd/wm831x/core.h>
21#include <linux/mfd/wm831x/pdata.h> 21#include <linux/mfd/wm831x/pdata.h>
22#include <linux/mfd/wm831x/irq.h>
22 23
23enum wm831x_parent { 24enum wm831x_parent {
24 WM8310 = 0, 25 WM8310 = 0,
@@ -1189,6 +1190,10 @@ static int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq)
1189 } 1190 }
1190 } 1191 }
1191 1192
1193 ret = wm831x_irq_init(wm831x, irq);
1194 if (ret != 0)
1195 goto err;
1196
1192 /* The core device is up, instantiate the subdevices. */ 1197 /* The core device is up, instantiate the subdevices. */
1193 switch (parent) { 1198 switch (parent) {
1194 case WM8310: 1199 case WM8310:
@@ -1216,19 +1221,21 @@ static int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq)
1216 1221
1217 if (ret != 0) { 1222 if (ret != 0) {
1218 dev_err(wm831x->dev, "Failed to add children\n"); 1223 dev_err(wm831x->dev, "Failed to add children\n");
1219 goto err; 1224 goto err_irq;
1220 } 1225 }
1221 1226
1222 if (pdata && pdata->post_init) { 1227 if (pdata && pdata->post_init) {
1223 ret = pdata->post_init(wm831x); 1228 ret = pdata->post_init(wm831x);
1224 if (ret != 0) { 1229 if (ret != 0) {
1225 dev_err(wm831x->dev, "post_init() failed: %d\n", ret); 1230 dev_err(wm831x->dev, "post_init() failed: %d\n", ret);
1226 goto err; 1231 goto err_irq;
1227 } 1232 }
1228 } 1233 }
1229 1234
1230 return 0; 1235 return 0;
1231 1236
1237err_irq:
1238 wm831x_irq_exit(wm831x);
1232err: 1239err:
1233 mfd_remove_devices(wm831x->dev); 1240 mfd_remove_devices(wm831x->dev);
1234 kfree(wm831x); 1241 kfree(wm831x);
@@ -1238,6 +1245,7 @@ err:
1238static void wm831x_device_exit(struct wm831x *wm831x) 1245static void wm831x_device_exit(struct wm831x *wm831x)
1239{ 1246{
1240 mfd_remove_devices(wm831x->dev); 1247 mfd_remove_devices(wm831x->dev);
1248 wm831x_irq_exit(wm831x);
1241 kfree(wm831x); 1249 kfree(wm831x);
1242} 1250}
1243 1251
diff --git a/drivers/mfd/wm831x-irq.c b/drivers/mfd/wm831x-irq.c
new file mode 100644
index 000000000000..d3015dfb9134
--- /dev/null
+++ b/drivers/mfd/wm831x-irq.c
@@ -0,0 +1,559 @@
1/*
2 * wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/i2c.h>
18#include <linux/mfd/core.h>
19#include <linux/interrupt.h>
20
21#include <linux/mfd/wm831x/core.h>
22#include <linux/mfd/wm831x/pdata.h>
23#include <linux/mfd/wm831x/irq.h>
24
25#include <linux/delay.h>
26
27/*
28 * Since generic IRQs don't currently support interrupt controllers on
29 * interrupt driven buses we don't use genirq but instead provide an
30 * interface that looks very much like the standard ones. This leads
31 * to some bodges, including storing interrupt handler information in
32 * the static irq_data table we use to look up the data for individual
33 * interrupts, but hopefully won't last too long.
34 */
35
36struct wm831x_irq_data {
37 int primary;
38 int reg;
39 int mask;
40 irq_handler_t handler;
41 void *handler_data;
42};
43
44static struct wm831x_irq_data wm831x_irqs[] = {
45 [WM831X_IRQ_TEMP_THW] = {
46 .primary = WM831X_TEMP_INT,
47 .reg = 1,
48 .mask = WM831X_TEMP_THW_EINT,
49 },
50 [WM831X_IRQ_GPIO_1] = {
51 .primary = WM831X_GP_INT,
52 .reg = 5,
53 .mask = WM831X_GP1_EINT,
54 },
55 [WM831X_IRQ_GPIO_2] = {
56 .primary = WM831X_GP_INT,
57 .reg = 5,
58 .mask = WM831X_GP2_EINT,
59 },
60 [WM831X_IRQ_GPIO_3] = {
61 .primary = WM831X_GP_INT,
62 .reg = 5,
63 .mask = WM831X_GP3_EINT,
64 },
65 [WM831X_IRQ_GPIO_4] = {
66 .primary = WM831X_GP_INT,
67 .reg = 5,
68 .mask = WM831X_GP4_EINT,
69 },
70 [WM831X_IRQ_GPIO_5] = {
71 .primary = WM831X_GP_INT,
72 .reg = 5,
73 .mask = WM831X_GP5_EINT,
74 },
75 [WM831X_IRQ_GPIO_6] = {
76 .primary = WM831X_GP_INT,
77 .reg = 5,
78 .mask = WM831X_GP6_EINT,
79 },
80 [WM831X_IRQ_GPIO_7] = {
81 .primary = WM831X_GP_INT,
82 .reg = 5,
83 .mask = WM831X_GP7_EINT,
84 },
85 [WM831X_IRQ_GPIO_8] = {
86 .primary = WM831X_GP_INT,
87 .reg = 5,
88 .mask = WM831X_GP8_EINT,
89 },
90 [WM831X_IRQ_GPIO_9] = {
91 .primary = WM831X_GP_INT,
92 .reg = 5,
93 .mask = WM831X_GP9_EINT,
94 },
95 [WM831X_IRQ_GPIO_10] = {
96 .primary = WM831X_GP_INT,
97 .reg = 5,
98 .mask = WM831X_GP10_EINT,
99 },
100 [WM831X_IRQ_GPIO_11] = {
101 .primary = WM831X_GP_INT,
102 .reg = 5,
103 .mask = WM831X_GP11_EINT,
104 },
105 [WM831X_IRQ_GPIO_12] = {
106 .primary = WM831X_GP_INT,
107 .reg = 5,
108 .mask = WM831X_GP12_EINT,
109 },
110 [WM831X_IRQ_GPIO_13] = {
111 .primary = WM831X_GP_INT,
112 .reg = 5,
113 .mask = WM831X_GP13_EINT,
114 },
115 [WM831X_IRQ_GPIO_14] = {
116 .primary = WM831X_GP_INT,
117 .reg = 5,
118 .mask = WM831X_GP14_EINT,
119 },
120 [WM831X_IRQ_GPIO_15] = {
121 .primary = WM831X_GP_INT,
122 .reg = 5,
123 .mask = WM831X_GP15_EINT,
124 },
125 [WM831X_IRQ_GPIO_16] = {
126 .primary = WM831X_GP_INT,
127 .reg = 5,
128 .mask = WM831X_GP16_EINT,
129 },
130 [WM831X_IRQ_ON] = {
131 .primary = WM831X_ON_PIN_INT,
132 .reg = 1,
133 .mask = WM831X_ON_PIN_EINT,
134 },
135 [WM831X_IRQ_PPM_SYSLO] = {
136 .primary = WM831X_PPM_INT,
137 .reg = 1,
138 .mask = WM831X_PPM_SYSLO_EINT,
139 },
140 [WM831X_IRQ_PPM_PWR_SRC] = {
141 .primary = WM831X_PPM_INT,
142 .reg = 1,
143 .mask = WM831X_PPM_PWR_SRC_EINT,
144 },
145 [WM831X_IRQ_PPM_USB_CURR] = {
146 .primary = WM831X_PPM_INT,
147 .reg = 1,
148 .mask = WM831X_PPM_USB_CURR_EINT,
149 },
150 [WM831X_IRQ_WDOG_TO] = {
151 .primary = WM831X_WDOG_INT,
152 .reg = 1,
153 .mask = WM831X_WDOG_TO_EINT,
154 },
155 [WM831X_IRQ_RTC_PER] = {
156 .primary = WM831X_RTC_INT,
157 .reg = 1,
158 .mask = WM831X_RTC_PER_EINT,
159 },
160 [WM831X_IRQ_RTC_ALM] = {
161 .primary = WM831X_RTC_INT,
162 .reg = 1,
163 .mask = WM831X_RTC_ALM_EINT,
164 },
165 [WM831X_IRQ_CHG_BATT_HOT] = {
166 .primary = WM831X_CHG_INT,
167 .reg = 2,
168 .mask = WM831X_CHG_BATT_HOT_EINT,
169 },
170 [WM831X_IRQ_CHG_BATT_COLD] = {
171 .primary = WM831X_CHG_INT,
172 .reg = 2,
173 .mask = WM831X_CHG_BATT_COLD_EINT,
174 },
175 [WM831X_IRQ_CHG_BATT_FAIL] = {
176 .primary = WM831X_CHG_INT,
177 .reg = 2,
178 .mask = WM831X_CHG_BATT_FAIL_EINT,
179 },
180 [WM831X_IRQ_CHG_OV] = {
181 .primary = WM831X_CHG_INT,
182 .reg = 2,
183 .mask = WM831X_CHG_OV_EINT,
184 },
185 [WM831X_IRQ_CHG_END] = {
186 .primary = WM831X_CHG_INT,
187 .reg = 2,
188 .mask = WM831X_CHG_END_EINT,
189 },
190 [WM831X_IRQ_CHG_TO] = {
191 .primary = WM831X_CHG_INT,
192 .reg = 2,
193 .mask = WM831X_CHG_TO_EINT,
194 },
195 [WM831X_IRQ_CHG_MODE] = {
196 .primary = WM831X_CHG_INT,
197 .reg = 2,
198 .mask = WM831X_CHG_MODE_EINT,
199 },
200 [WM831X_IRQ_CHG_START] = {
201 .primary = WM831X_CHG_INT,
202 .reg = 2,
203 .mask = WM831X_CHG_START_EINT,
204 },
205 [WM831X_IRQ_TCHDATA] = {
206 .primary = WM831X_TCHDATA_INT,
207 .reg = 1,
208 .mask = WM831X_TCHDATA_EINT,
209 },
210 [WM831X_IRQ_TCHPD] = {
211 .primary = WM831X_TCHPD_INT,
212 .reg = 1,
213 .mask = WM831X_TCHPD_EINT,
214 },
215 [WM831X_IRQ_AUXADC_DATA] = {
216 .primary = WM831X_AUXADC_INT,
217 .reg = 1,
218 .mask = WM831X_AUXADC_DATA_EINT,
219 },
220 [WM831X_IRQ_AUXADC_DCOMP1] = {
221 .primary = WM831X_AUXADC_INT,
222 .reg = 1,
223 .mask = WM831X_AUXADC_DCOMP1_EINT,
224 },
225 [WM831X_IRQ_AUXADC_DCOMP2] = {
226 .primary = WM831X_AUXADC_INT,
227 .reg = 1,
228 .mask = WM831X_AUXADC_DCOMP2_EINT,
229 },
230 [WM831X_IRQ_AUXADC_DCOMP3] = {
231 .primary = WM831X_AUXADC_INT,
232 .reg = 1,
233 .mask = WM831X_AUXADC_DCOMP3_EINT,
234 },
235 [WM831X_IRQ_AUXADC_DCOMP4] = {
236 .primary = WM831X_AUXADC_INT,
237 .reg = 1,
238 .mask = WM831X_AUXADC_DCOMP4_EINT,
239 },
240 [WM831X_IRQ_CS1] = {
241 .primary = WM831X_CS_INT,
242 .reg = 2,
243 .mask = WM831X_CS1_EINT,
244 },
245 [WM831X_IRQ_CS2] = {
246 .primary = WM831X_CS_INT,
247 .reg = 2,
248 .mask = WM831X_CS2_EINT,
249 },
250 [WM831X_IRQ_HC_DC1] = {
251 .primary = WM831X_HC_INT,
252 .reg = 4,
253 .mask = WM831X_HC_DC1_EINT,
254 },
255 [WM831X_IRQ_HC_DC2] = {
256 .primary = WM831X_HC_INT,
257 .reg = 4,
258 .mask = WM831X_HC_DC2_EINT,
259 },
260 [WM831X_IRQ_UV_LDO1] = {
261 .primary = WM831X_UV_INT,
262 .reg = 3,
263 .mask = WM831X_UV_LDO1_EINT,
264 },
265 [WM831X_IRQ_UV_LDO2] = {
266 .primary = WM831X_UV_INT,
267 .reg = 3,
268 .mask = WM831X_UV_LDO2_EINT,
269 },
270 [WM831X_IRQ_UV_LDO3] = {
271 .primary = WM831X_UV_INT,
272 .reg = 3,
273 .mask = WM831X_UV_LDO3_EINT,
274 },
275 [WM831X_IRQ_UV_LDO4] = {
276 .primary = WM831X_UV_INT,
277 .reg = 3,
278 .mask = WM831X_UV_LDO4_EINT,
279 },
280 [WM831X_IRQ_UV_LDO5] = {
281 .primary = WM831X_UV_INT,
282 .reg = 3,
283 .mask = WM831X_UV_LDO5_EINT,
284 },
285 [WM831X_IRQ_UV_LDO6] = {
286 .primary = WM831X_UV_INT,
287 .reg = 3,
288 .mask = WM831X_UV_LDO6_EINT,
289 },
290 [WM831X_IRQ_UV_LDO7] = {
291 .primary = WM831X_UV_INT,
292 .reg = 3,
293 .mask = WM831X_UV_LDO7_EINT,
294 },
295 [WM831X_IRQ_UV_LDO8] = {
296 .primary = WM831X_UV_INT,
297 .reg = 3,
298 .mask = WM831X_UV_LDO8_EINT,
299 },
300 [WM831X_IRQ_UV_LDO9] = {
301 .primary = WM831X_UV_INT,
302 .reg = 3,
303 .mask = WM831X_UV_LDO9_EINT,
304 },
305 [WM831X_IRQ_UV_LDO10] = {
306 .primary = WM831X_UV_INT,
307 .reg = 3,
308 .mask = WM831X_UV_LDO10_EINT,
309 },
310 [WM831X_IRQ_UV_DC1] = {
311 .primary = WM831X_UV_INT,
312 .reg = 4,
313 .mask = WM831X_UV_DC1_EINT,
314 },
315 [WM831X_IRQ_UV_DC2] = {
316 .primary = WM831X_UV_INT,
317 .reg = 4,
318 .mask = WM831X_UV_DC2_EINT,
319 },
320 [WM831X_IRQ_UV_DC3] = {
321 .primary = WM831X_UV_INT,
322 .reg = 4,
323 .mask = WM831X_UV_DC3_EINT,
324 },
325 [WM831X_IRQ_UV_DC4] = {
326 .primary = WM831X_UV_INT,
327 .reg = 4,
328 .mask = WM831X_UV_DC4_EINT,
329 },
330};
331
332static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
333{
334 return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
335}
336
337static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data)
338{
339 return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg;
340}
341
342static void __wm831x_enable_irq(struct wm831x *wm831x, int irq)
343{
344 struct wm831x_irq_data *irq_data = &wm831x_irqs[irq];
345
346 wm831x->irq_masks[irq_data->reg - 1] &= ~irq_data->mask;
347 wm831x_reg_write(wm831x, irq_data_to_mask_reg(irq_data),
348 wm831x->irq_masks[irq_data->reg - 1]);
349}
350
351void wm831x_enable_irq(struct wm831x *wm831x, int irq)
352{
353 mutex_lock(&wm831x->irq_lock);
354 __wm831x_enable_irq(wm831x, irq);
355 mutex_unlock(&wm831x->irq_lock);
356}
357EXPORT_SYMBOL_GPL(wm831x_enable_irq);
358
359static void __wm831x_disable_irq(struct wm831x *wm831x, int irq)
360{
361 struct wm831x_irq_data *irq_data = &wm831x_irqs[irq];
362
363 wm831x->irq_masks[irq_data->reg - 1] |= irq_data->mask;
364 wm831x_reg_write(wm831x, irq_data_to_mask_reg(irq_data),
365 wm831x->irq_masks[irq_data->reg - 1]);
366}
367
368void wm831x_disable_irq(struct wm831x *wm831x, int irq)
369{
370 mutex_lock(&wm831x->irq_lock);
371 __wm831x_disable_irq(wm831x, irq);
372 mutex_unlock(&wm831x->irq_lock);
373}
374EXPORT_SYMBOL_GPL(wm831x_disable_irq);
375
376int wm831x_request_irq(struct wm831x *wm831x,
377 unsigned int irq, irq_handler_t handler,
378 unsigned long flags, const char *name,
379 void *dev)
380{
381 int ret = 0;
382
383 if (irq < 0 || irq >= WM831X_NUM_IRQS)
384 return -EINVAL;
385
386 mutex_lock(&wm831x->irq_lock);
387
388 if (wm831x_irqs[irq].handler) {
389 dev_err(wm831x->dev, "Already have handler for IRQ %d\n", irq);
390 ret = -EINVAL;
391 goto out;
392 }
393
394 wm831x_irqs[irq].handler = handler;
395 wm831x_irqs[irq].handler_data = dev;
396
397 __wm831x_enable_irq(wm831x, irq);
398
399out:
400 mutex_unlock(&wm831x->irq_lock);
401
402 return ret;
403}
404EXPORT_SYMBOL_GPL(wm831x_request_irq);
405
406void wm831x_free_irq(struct wm831x *wm831x, unsigned int irq, void *data)
407{
408 if (irq < 0 || irq >= WM831X_NUM_IRQS)
409 return;
410
411 mutex_lock(&wm831x->irq_lock);
412
413 wm831x_irqs[irq].handler = NULL;
414 wm831x_irqs[irq].handler_data = NULL;
415
416 __wm831x_disable_irq(wm831x, irq);
417
418 mutex_unlock(&wm831x->irq_lock);
419}
420EXPORT_SYMBOL_GPL(wm831x_free_irq);
421
422
423static void wm831x_handle_irq(struct wm831x *wm831x, int irq, int status)
424{
425 struct wm831x_irq_data *irq_data = &wm831x_irqs[irq];
426
427 if (irq_data->handler) {
428 irq_data->handler(irq, irq_data->handler_data);
429 wm831x_reg_write(wm831x, irq_data_to_status_reg(irq_data),
430 irq_data->mask);
431 } else {
432 dev_err(wm831x->dev, "Unhandled IRQ %d, masking\n", irq);
433 __wm831x_disable_irq(wm831x, irq);
434 }
435}
436
437/* Main interrupt handling occurs in a workqueue since we need
438 * interrupts enabled to interact with the chip. */
439static void wm831x_irq_worker(struct work_struct *work)
440{
441 struct wm831x *wm831x = container_of(work, struct wm831x, irq_work);
442 unsigned int i;
443 int primary;
444 int status_regs[5];
445 int read[5] = { 0 };
446 int *status;
447
448 primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
449 if (primary < 0) {
450 dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
451 primary);
452 goto out;
453 }
454
455 mutex_lock(&wm831x->irq_lock);
456
457 for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
458 int offset = wm831x_irqs[i].reg - 1;
459
460 if (!(primary & wm831x_irqs[i].primary))
461 continue;
462
463 status = &status_regs[offset];
464
465 /* Hopefully there should only be one register to read
466 * each time otherwise we ought to do a block read. */
467 if (!read[offset]) {
468 *status = wm831x_reg_read(wm831x,
469 irq_data_to_status_reg(&wm831x_irqs[i]));
470 if (*status < 0) {
471 dev_err(wm831x->dev,
472 "Failed to read IRQ status: %d\n",
473 *status);
474 goto out_lock;
475 }
476
477 /* Mask out the disabled IRQs */
478 *status &= ~wm831x->irq_masks[offset];
479 read[offset] = 1;
480 }
481
482 if (*status & wm831x_irqs[i].mask)
483 wm831x_handle_irq(wm831x, i, *status);
484 }
485
486out_lock:
487 mutex_unlock(&wm831x->irq_lock);
488out:
489 enable_irq(wm831x->irq);
490}
491
492
493static irqreturn_t wm831x_cpu_irq(int irq, void *data)
494{
495 struct wm831x *wm831x = data;
496
497 /* Shut the interrupt to the CPU up and schedule the actual
498 * handler; we can't check that the IRQ is asserted. */
499 disable_irq_nosync(irq);
500
501 queue_work(wm831x->irq_wq, &wm831x->irq_work);
502
503 return IRQ_HANDLED;
504}
505
506int wm831x_irq_init(struct wm831x *wm831x, int irq)
507{
508 int i, ret;
509
510 if (!irq) {
511 dev_warn(wm831x->dev,
512 "No interrupt specified - functionality limited\n");
513 return 0;
514 }
515
516
517 wm831x->irq_wq = create_singlethread_workqueue("wm831x-irq");
518 if (!wm831x->irq_wq) {
519 dev_err(wm831x->dev, "Failed to allocate IRQ worker\n");
520 return -ESRCH;
521 }
522
523 wm831x->irq = irq;
524 mutex_init(&wm831x->irq_lock);
525 INIT_WORK(&wm831x->irq_work, wm831x_irq_worker);
526
527 /* Mask the individual interrupt sources */
528 for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks); i++) {
529 wm831x->irq_masks[i] = 0xffff;
530 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
531 0xffff);
532 }
533
534 /* Enable top level interrupts, we mask at secondary level */
535 wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
536
537 /* We're good to go. We set IRQF_SHARED since there's a
538 * chance the driver will interoperate with another driver but
539 * the need to disable the IRQ while handing via I2C/SPI means
540 * that this may break and performance will be impacted. If
541 * this does happen it's a hardware design issue and the only
542 * other alternative would be polling.
543 */
544 ret = request_irq(irq, wm831x_cpu_irq, IRQF_TRIGGER_LOW | IRQF_SHARED,
545 "wm831x", wm831x);
546 if (ret != 0) {
547 dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
548 irq, ret);
549 return ret;
550 }
551
552 return 0;
553}
554
555void wm831x_irq_exit(struct wm831x *wm831x)
556{
557 if (wm831x->irq)
558 free_irq(wm831x->irq, wm831x);
559}
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index d90e693053ba..b96c9355b16e 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -15,6 +15,9 @@
15#ifndef __MFD_WM831X_CORE_H__ 15#ifndef __MFD_WM831X_CORE_H__
16#define __MFD_WM831X_CORE_H__ 16#define __MFD_WM831X_CORE_H__
17 17
18#include <linux/interrupt.h>
19#include <linux/workqueue.h>
20
18/* 21/*
19 * Register values. 22 * Register values.
20 */ 23 */
@@ -224,6 +227,13 @@ struct wm831x {
224 227
225 void *control_data; 228 void *control_data;
226 229
230 int irq; /* Our chip IRQ */
231 struct mutex irq_lock;
232 struct workqueue_struct *irq_wq;
233 struct work_struct irq_work;
234 unsigned int irq_base;
235 int irq_masks[5];
236
227 /* The WM831x has a security key blocking access to certain 237 /* The WM831x has a security key blocking access to certain
228 * registers. The mutex is taken by the accessors for locking 238 * registers. The mutex is taken by the accessors for locking
229 * and unlocking the security key, locked is used to fail 239 * and unlocking the security key, locked is used to fail
@@ -244,4 +254,15 @@ int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
244int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg, 254int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
245 int count, u16 *buf); 255 int count, u16 *buf);
246 256
257int wm831x_irq_init(struct wm831x *wm831x, int irq);
258void wm831x_irq_exit(struct wm831x *wm831x);
259
260int __must_check wm831x_request_irq(struct wm831x *wm831x,
261 unsigned int irq, irq_handler_t handler,
262 unsigned long flags, const char *name,
263 void *dev);
264void wm831x_free_irq(struct wm831x *wm831x, unsigned int, void *);
265void wm831x_disable_irq(struct wm831x *wm831x, int irq);
266void wm831x_enable_irq(struct wm831x *wm831x, int irq);
267
247#endif 268#endif
diff --git a/include/linux/mfd/wm831x/irq.h b/include/linux/mfd/wm831x/irq.h
new file mode 100644
index 000000000000..3a8c97656fda
--- /dev/null
+++ b/include/linux/mfd/wm831x/irq.h
@@ -0,0 +1,764 @@
1/*
2 * include/linux/mfd/wm831x/irq.h -- Interrupt controller for WM831x
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __MFD_WM831X_IRQ_H__
16#define __MFD_WM831X_IRQ_H__
17
18/* Interrupt number assignments within Linux */
19#define WM831X_IRQ_TEMP_THW 0
20#define WM831X_IRQ_GPIO_1 1
21#define WM831X_IRQ_GPIO_2 2
22#define WM831X_IRQ_GPIO_3 3
23#define WM831X_IRQ_GPIO_4 4
24#define WM831X_IRQ_GPIO_5 5
25#define WM831X_IRQ_GPIO_6 6
26#define WM831X_IRQ_GPIO_7 7
27#define WM831X_IRQ_GPIO_8 8
28#define WM831X_IRQ_GPIO_9 9
29#define WM831X_IRQ_GPIO_10 10
30#define WM831X_IRQ_GPIO_11 11
31#define WM831X_IRQ_GPIO_12 12
32#define WM831X_IRQ_GPIO_13 13
33#define WM831X_IRQ_GPIO_14 14
34#define WM831X_IRQ_GPIO_15 15
35#define WM831X_IRQ_GPIO_16 16
36#define WM831X_IRQ_ON 17
37#define WM831X_IRQ_PPM_SYSLO 18
38#define WM831X_IRQ_PPM_PWR_SRC 19
39#define WM831X_IRQ_PPM_USB_CURR 20
40#define WM831X_IRQ_WDOG_TO 21
41#define WM831X_IRQ_RTC_PER 22
42#define WM831X_IRQ_RTC_ALM 23
43#define WM831X_IRQ_CHG_BATT_HOT 24
44#define WM831X_IRQ_CHG_BATT_COLD 25
45#define WM831X_IRQ_CHG_BATT_FAIL 26
46#define WM831X_IRQ_CHG_OV 27
47#define WM831X_IRQ_CHG_END 29
48#define WM831X_IRQ_CHG_TO 30
49#define WM831X_IRQ_CHG_MODE 31
50#define WM831X_IRQ_CHG_START 32
51#define WM831X_IRQ_TCHDATA 33
52#define WM831X_IRQ_TCHPD 34
53#define WM831X_IRQ_AUXADC_DATA 35
54#define WM831X_IRQ_AUXADC_DCOMP1 36
55#define WM831X_IRQ_AUXADC_DCOMP2 37
56#define WM831X_IRQ_AUXADC_DCOMP3 38
57#define WM831X_IRQ_AUXADC_DCOMP4 39
58#define WM831X_IRQ_CS1 40
59#define WM831X_IRQ_CS2 41
60#define WM831X_IRQ_HC_DC1 42
61#define WM831X_IRQ_HC_DC2 43
62#define WM831X_IRQ_UV_LDO1 44
63#define WM831X_IRQ_UV_LDO2 45
64#define WM831X_IRQ_UV_LDO3 46
65#define WM831X_IRQ_UV_LDO4 47
66#define WM831X_IRQ_UV_LDO5 48
67#define WM831X_IRQ_UV_LDO6 49
68#define WM831X_IRQ_UV_LDO7 50
69#define WM831X_IRQ_UV_LDO8 51
70#define WM831X_IRQ_UV_LDO9 52
71#define WM831X_IRQ_UV_LDO10 53
72#define WM831X_IRQ_UV_DC1 54
73#define WM831X_IRQ_UV_DC2 55
74#define WM831X_IRQ_UV_DC3 56
75#define WM831X_IRQ_UV_DC4 57
76
77#define WM831X_NUM_IRQS 58
78
79/*
80 * R16400 (0x4010) - System Interrupts
81 */
82#define WM831X_PS_INT 0x8000 /* PS_INT */
83#define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
84#define WM831X_PS_INT_SHIFT 15 /* PS_INT */
85#define WM831X_PS_INT_WIDTH 1 /* PS_INT */
86#define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
87#define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
88#define WM831X_TEMP_INT_SHIFT 14 /* TEMP_INT */
89#define WM831X_TEMP_INT_WIDTH 1 /* TEMP_INT */
90#define WM831X_GP_INT 0x2000 /* GP_INT */
91#define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
92#define WM831X_GP_INT_SHIFT 13 /* GP_INT */
93#define WM831X_GP_INT_WIDTH 1 /* GP_INT */
94#define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
95#define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
96#define WM831X_ON_PIN_INT_SHIFT 12 /* ON_PIN_INT */
97#define WM831X_ON_PIN_INT_WIDTH 1 /* ON_PIN_INT */
98#define WM831X_WDOG_INT 0x0800 /* WDOG_INT */
99#define WM831X_WDOG_INT_MASK 0x0800 /* WDOG_INT */
100#define WM831X_WDOG_INT_SHIFT 11 /* WDOG_INT */
101#define WM831X_WDOG_INT_WIDTH 1 /* WDOG_INT */
102#define WM831X_TCHDATA_INT 0x0400 /* TCHDATA_INT */
103#define WM831X_TCHDATA_INT_MASK 0x0400 /* TCHDATA_INT */
104#define WM831X_TCHDATA_INT_SHIFT 10 /* TCHDATA_INT */
105#define WM831X_TCHDATA_INT_WIDTH 1 /* TCHDATA_INT */
106#define WM831X_TCHPD_INT 0x0200 /* TCHPD_INT */
107#define WM831X_TCHPD_INT_MASK 0x0200 /* TCHPD_INT */
108#define WM831X_TCHPD_INT_SHIFT 9 /* TCHPD_INT */
109#define WM831X_TCHPD_INT_WIDTH 1 /* TCHPD_INT */
110#define WM831X_AUXADC_INT 0x0100 /* AUXADC_INT */
111#define WM831X_AUXADC_INT_MASK 0x0100 /* AUXADC_INT */
112#define WM831X_AUXADC_INT_SHIFT 8 /* AUXADC_INT */
113#define WM831X_AUXADC_INT_WIDTH 1 /* AUXADC_INT */
114#define WM831X_PPM_INT 0x0080 /* PPM_INT */
115#define WM831X_PPM_INT_MASK 0x0080 /* PPM_INT */
116#define WM831X_PPM_INT_SHIFT 7 /* PPM_INT */
117#define WM831X_PPM_INT_WIDTH 1 /* PPM_INT */
118#define WM831X_CS_INT 0x0040 /* CS_INT */
119#define WM831X_CS_INT_MASK 0x0040 /* CS_INT */
120#define WM831X_CS_INT_SHIFT 6 /* CS_INT */
121#define WM831X_CS_INT_WIDTH 1 /* CS_INT */
122#define WM831X_RTC_INT 0x0020 /* RTC_INT */
123#define WM831X_RTC_INT_MASK 0x0020 /* RTC_INT */
124#define WM831X_RTC_INT_SHIFT 5 /* RTC_INT */
125#define WM831X_RTC_INT_WIDTH 1 /* RTC_INT */
126#define WM831X_OTP_INT 0x0010 /* OTP_INT */
127#define WM831X_OTP_INT_MASK 0x0010 /* OTP_INT */
128#define WM831X_OTP_INT_SHIFT 4 /* OTP_INT */
129#define WM831X_OTP_INT_WIDTH 1 /* OTP_INT */
130#define WM831X_CHILD_INT 0x0008 /* CHILD_INT */
131#define WM831X_CHILD_INT_MASK 0x0008 /* CHILD_INT */
132#define WM831X_CHILD_INT_SHIFT 3 /* CHILD_INT */
133#define WM831X_CHILD_INT_WIDTH 1 /* CHILD_INT */
134#define WM831X_CHG_INT 0x0004 /* CHG_INT */
135#define WM831X_CHG_INT_MASK 0x0004 /* CHG_INT */
136#define WM831X_CHG_INT_SHIFT 2 /* CHG_INT */
137#define WM831X_CHG_INT_WIDTH 1 /* CHG_INT */
138#define WM831X_HC_INT 0x0002 /* HC_INT */
139#define WM831X_HC_INT_MASK 0x0002 /* HC_INT */
140#define WM831X_HC_INT_SHIFT 1 /* HC_INT */
141#define WM831X_HC_INT_WIDTH 1 /* HC_INT */
142#define WM831X_UV_INT 0x0001 /* UV_INT */
143#define WM831X_UV_INT_MASK 0x0001 /* UV_INT */
144#define WM831X_UV_INT_SHIFT 0 /* UV_INT */
145#define WM831X_UV_INT_WIDTH 1 /* UV_INT */
146
147/*
148 * R16401 (0x4011) - Interrupt Status 1
149 */
150#define WM831X_PPM_SYSLO_EINT 0x8000 /* PPM_SYSLO_EINT */
151#define WM831X_PPM_SYSLO_EINT_MASK 0x8000 /* PPM_SYSLO_EINT */
152#define WM831X_PPM_SYSLO_EINT_SHIFT 15 /* PPM_SYSLO_EINT */
153#define WM831X_PPM_SYSLO_EINT_WIDTH 1 /* PPM_SYSLO_EINT */
154#define WM831X_PPM_PWR_SRC_EINT 0x4000 /* PPM_PWR_SRC_EINT */
155#define WM831X_PPM_PWR_SRC_EINT_MASK 0x4000 /* PPM_PWR_SRC_EINT */
156#define WM831X_PPM_PWR_SRC_EINT_SHIFT 14 /* PPM_PWR_SRC_EINT */
157#define WM831X_PPM_PWR_SRC_EINT_WIDTH 1 /* PPM_PWR_SRC_EINT */
158#define WM831X_PPM_USB_CURR_EINT 0x2000 /* PPM_USB_CURR_EINT */
159#define WM831X_PPM_USB_CURR_EINT_MASK 0x2000 /* PPM_USB_CURR_EINT */
160#define WM831X_PPM_USB_CURR_EINT_SHIFT 13 /* PPM_USB_CURR_EINT */
161#define WM831X_PPM_USB_CURR_EINT_WIDTH 1 /* PPM_USB_CURR_EINT */
162#define WM831X_ON_PIN_EINT 0x1000 /* ON_PIN_EINT */
163#define WM831X_ON_PIN_EINT_MASK 0x1000 /* ON_PIN_EINT */
164#define WM831X_ON_PIN_EINT_SHIFT 12 /* ON_PIN_EINT */
165#define WM831X_ON_PIN_EINT_WIDTH 1 /* ON_PIN_EINT */
166#define WM831X_WDOG_TO_EINT 0x0800 /* WDOG_TO_EINT */
167#define WM831X_WDOG_TO_EINT_MASK 0x0800 /* WDOG_TO_EINT */
168#define WM831X_WDOG_TO_EINT_SHIFT 11 /* WDOG_TO_EINT */
169#define WM831X_WDOG_TO_EINT_WIDTH 1 /* WDOG_TO_EINT */
170#define WM831X_TCHDATA_EINT 0x0400 /* TCHDATA_EINT */
171#define WM831X_TCHDATA_EINT_MASK 0x0400 /* TCHDATA_EINT */
172#define WM831X_TCHDATA_EINT_SHIFT 10 /* TCHDATA_EINT */
173#define WM831X_TCHDATA_EINT_WIDTH 1 /* TCHDATA_EINT */
174#define WM831X_TCHPD_EINT 0x0200 /* TCHPD_EINT */
175#define WM831X_TCHPD_EINT_MASK 0x0200 /* TCHPD_EINT */
176#define WM831X_TCHPD_EINT_SHIFT 9 /* TCHPD_EINT */
177#define WM831X_TCHPD_EINT_WIDTH 1 /* TCHPD_EINT */
178#define WM831X_AUXADC_DATA_EINT 0x0100 /* AUXADC_DATA_EINT */
179#define WM831X_AUXADC_DATA_EINT_MASK 0x0100 /* AUXADC_DATA_EINT */
180#define WM831X_AUXADC_DATA_EINT_SHIFT 8 /* AUXADC_DATA_EINT */
181#define WM831X_AUXADC_DATA_EINT_WIDTH 1 /* AUXADC_DATA_EINT */
182#define WM831X_AUXADC_DCOMP4_EINT 0x0080 /* AUXADC_DCOMP4_EINT */
183#define WM831X_AUXADC_DCOMP4_EINT_MASK 0x0080 /* AUXADC_DCOMP4_EINT */
184#define WM831X_AUXADC_DCOMP4_EINT_SHIFT 7 /* AUXADC_DCOMP4_EINT */
185#define WM831X_AUXADC_DCOMP4_EINT_WIDTH 1 /* AUXADC_DCOMP4_EINT */
186#define WM831X_AUXADC_DCOMP3_EINT 0x0040 /* AUXADC_DCOMP3_EINT */
187#define WM831X_AUXADC_DCOMP3_EINT_MASK 0x0040 /* AUXADC_DCOMP3_EINT */
188#define WM831X_AUXADC_DCOMP3_EINT_SHIFT 6 /* AUXADC_DCOMP3_EINT */
189#define WM831X_AUXADC_DCOMP3_EINT_WIDTH 1 /* AUXADC_DCOMP3_EINT */
190#define WM831X_AUXADC_DCOMP2_EINT 0x0020 /* AUXADC_DCOMP2_EINT */
191#define WM831X_AUXADC_DCOMP2_EINT_MASK 0x0020 /* AUXADC_DCOMP2_EINT */
192#define WM831X_AUXADC_DCOMP2_EINT_SHIFT 5 /* AUXADC_DCOMP2_EINT */
193#define WM831X_AUXADC_DCOMP2_EINT_WIDTH 1 /* AUXADC_DCOMP2_EINT */
194#define WM831X_AUXADC_DCOMP1_EINT 0x0010 /* AUXADC_DCOMP1_EINT */
195#define WM831X_AUXADC_DCOMP1_EINT_MASK 0x0010 /* AUXADC_DCOMP1_EINT */
196#define WM831X_AUXADC_DCOMP1_EINT_SHIFT 4 /* AUXADC_DCOMP1_EINT */
197#define WM831X_AUXADC_DCOMP1_EINT_WIDTH 1 /* AUXADC_DCOMP1_EINT */
198#define WM831X_RTC_PER_EINT 0x0008 /* RTC_PER_EINT */
199#define WM831X_RTC_PER_EINT_MASK 0x0008 /* RTC_PER_EINT */
200#define WM831X_RTC_PER_EINT_SHIFT 3 /* RTC_PER_EINT */
201#define WM831X_RTC_PER_EINT_WIDTH 1 /* RTC_PER_EINT */
202#define WM831X_RTC_ALM_EINT 0x0004 /* RTC_ALM_EINT */
203#define WM831X_RTC_ALM_EINT_MASK 0x0004 /* RTC_ALM_EINT */
204#define WM831X_RTC_ALM_EINT_SHIFT 2 /* RTC_ALM_EINT */
205#define WM831X_RTC_ALM_EINT_WIDTH 1 /* RTC_ALM_EINT */
206#define WM831X_TEMP_THW_EINT 0x0002 /* TEMP_THW_EINT */
207#define WM831X_TEMP_THW_EINT_MASK 0x0002 /* TEMP_THW_EINT */
208#define WM831X_TEMP_THW_EINT_SHIFT 1 /* TEMP_THW_EINT */
209#define WM831X_TEMP_THW_EINT_WIDTH 1 /* TEMP_THW_EINT */
210
211/*
212 * R16402 (0x4012) - Interrupt Status 2
213 */
214#define WM831X_CHG_BATT_HOT_EINT 0x8000 /* CHG_BATT_HOT_EINT */
215#define WM831X_CHG_BATT_HOT_EINT_MASK 0x8000 /* CHG_BATT_HOT_EINT */
216#define WM831X_CHG_BATT_HOT_EINT_SHIFT 15 /* CHG_BATT_HOT_EINT */
217#define WM831X_CHG_BATT_HOT_EINT_WIDTH 1 /* CHG_BATT_HOT_EINT */
218#define WM831X_CHG_BATT_COLD_EINT 0x4000 /* CHG_BATT_COLD_EINT */
219#define WM831X_CHG_BATT_COLD_EINT_MASK 0x4000 /* CHG_BATT_COLD_EINT */
220#define WM831X_CHG_BATT_COLD_EINT_SHIFT 14 /* CHG_BATT_COLD_EINT */
221#define WM831X_CHG_BATT_COLD_EINT_WIDTH 1 /* CHG_BATT_COLD_EINT */
222#define WM831X_CHG_BATT_FAIL_EINT 0x2000 /* CHG_BATT_FAIL_EINT */
223#define WM831X_CHG_BATT_FAIL_EINT_MASK 0x2000 /* CHG_BATT_FAIL_EINT */
224#define WM831X_CHG_BATT_FAIL_EINT_SHIFT 13 /* CHG_BATT_FAIL_EINT */
225#define WM831X_CHG_BATT_FAIL_EINT_WIDTH 1 /* CHG_BATT_FAIL_EINT */
226#define WM831X_CHG_OV_EINT 0x1000 /* CHG_OV_EINT */
227#define WM831X_CHG_OV_EINT_MASK 0x1000 /* CHG_OV_EINT */
228#define WM831X_CHG_OV_EINT_SHIFT 12 /* CHG_OV_EINT */
229#define WM831X_CHG_OV_EINT_WIDTH 1 /* CHG_OV_EINT */
230#define WM831X_CHG_END_EINT 0x0800 /* CHG_END_EINT */
231#define WM831X_CHG_END_EINT_MASK 0x0800 /* CHG_END_EINT */
232#define WM831X_CHG_END_EINT_SHIFT 11 /* CHG_END_EINT */
233#define WM831X_CHG_END_EINT_WIDTH 1 /* CHG_END_EINT */
234#define WM831X_CHG_TO_EINT 0x0400 /* CHG_TO_EINT */
235#define WM831X_CHG_TO_EINT_MASK 0x0400 /* CHG_TO_EINT */
236#define WM831X_CHG_TO_EINT_SHIFT 10 /* CHG_TO_EINT */
237#define WM831X_CHG_TO_EINT_WIDTH 1 /* CHG_TO_EINT */
238#define WM831X_CHG_MODE_EINT 0x0200 /* CHG_MODE_EINT */
239#define WM831X_CHG_MODE_EINT_MASK 0x0200 /* CHG_MODE_EINT */
240#define WM831X_CHG_MODE_EINT_SHIFT 9 /* CHG_MODE_EINT */
241#define WM831X_CHG_MODE_EINT_WIDTH 1 /* CHG_MODE_EINT */
242#define WM831X_CHG_START_EINT 0x0100 /* CHG_START_EINT */
243#define WM831X_CHG_START_EINT_MASK 0x0100 /* CHG_START_EINT */
244#define WM831X_CHG_START_EINT_SHIFT 8 /* CHG_START_EINT */
245#define WM831X_CHG_START_EINT_WIDTH 1 /* CHG_START_EINT */
246#define WM831X_CS2_EINT 0x0080 /* CS2_EINT */
247#define WM831X_CS2_EINT_MASK 0x0080 /* CS2_EINT */
248#define WM831X_CS2_EINT_SHIFT 7 /* CS2_EINT */
249#define WM831X_CS2_EINT_WIDTH 1 /* CS2_EINT */
250#define WM831X_CS1_EINT 0x0040 /* CS1_EINT */
251#define WM831X_CS1_EINT_MASK 0x0040 /* CS1_EINT */
252#define WM831X_CS1_EINT_SHIFT 6 /* CS1_EINT */
253#define WM831X_CS1_EINT_WIDTH 1 /* CS1_EINT */
254#define WM831X_OTP_CMD_END_EINT 0x0020 /* OTP_CMD_END_EINT */
255#define WM831X_OTP_CMD_END_EINT_MASK 0x0020 /* OTP_CMD_END_EINT */
256#define WM831X_OTP_CMD_END_EINT_SHIFT 5 /* OTP_CMD_END_EINT */
257#define WM831X_OTP_CMD_END_EINT_WIDTH 1 /* OTP_CMD_END_EINT */
258#define WM831X_OTP_ERR_EINT 0x0010 /* OTP_ERR_EINT */
259#define WM831X_OTP_ERR_EINT_MASK 0x0010 /* OTP_ERR_EINT */
260#define WM831X_OTP_ERR_EINT_SHIFT 4 /* OTP_ERR_EINT */
261#define WM831X_OTP_ERR_EINT_WIDTH 1 /* OTP_ERR_EINT */
262#define WM831X_PS_POR_EINT 0x0004 /* PS_POR_EINT */
263#define WM831X_PS_POR_EINT_MASK 0x0004 /* PS_POR_EINT */
264#define WM831X_PS_POR_EINT_SHIFT 2 /* PS_POR_EINT */
265#define WM831X_PS_POR_EINT_WIDTH 1 /* PS_POR_EINT */
266#define WM831X_PS_SLEEP_OFF_EINT 0x0002 /* PS_SLEEP_OFF_EINT */
267#define WM831X_PS_SLEEP_OFF_EINT_MASK 0x0002 /* PS_SLEEP_OFF_EINT */
268#define WM831X_PS_SLEEP_OFF_EINT_SHIFT 1 /* PS_SLEEP_OFF_EINT */
269#define WM831X_PS_SLEEP_OFF_EINT_WIDTH 1 /* PS_SLEEP_OFF_EINT */
270#define WM831X_PS_ON_WAKE_EINT 0x0001 /* PS_ON_WAKE_EINT */
271#define WM831X_PS_ON_WAKE_EINT_MASK 0x0001 /* PS_ON_WAKE_EINT */
272#define WM831X_PS_ON_WAKE_EINT_SHIFT 0 /* PS_ON_WAKE_EINT */
273#define WM831X_PS_ON_WAKE_EINT_WIDTH 1 /* PS_ON_WAKE_EINT */
274
275/*
276 * R16403 (0x4013) - Interrupt Status 3
277 */
278#define WM831X_UV_LDO10_EINT 0x0200 /* UV_LDO10_EINT */
279#define WM831X_UV_LDO10_EINT_MASK 0x0200 /* UV_LDO10_EINT */
280#define WM831X_UV_LDO10_EINT_SHIFT 9 /* UV_LDO10_EINT */
281#define WM831X_UV_LDO10_EINT_WIDTH 1 /* UV_LDO10_EINT */
282#define WM831X_UV_LDO9_EINT 0x0100 /* UV_LDO9_EINT */
283#define WM831X_UV_LDO9_EINT_MASK 0x0100 /* UV_LDO9_EINT */
284#define WM831X_UV_LDO9_EINT_SHIFT 8 /* UV_LDO9_EINT */
285#define WM831X_UV_LDO9_EINT_WIDTH 1 /* UV_LDO9_EINT */
286#define WM831X_UV_LDO8_EINT 0x0080 /* UV_LDO8_EINT */
287#define WM831X_UV_LDO8_EINT_MASK 0x0080 /* UV_LDO8_EINT */
288#define WM831X_UV_LDO8_EINT_SHIFT 7 /* UV_LDO8_EINT */
289#define WM831X_UV_LDO8_EINT_WIDTH 1 /* UV_LDO8_EINT */
290#define WM831X_UV_LDO7_EINT 0x0040 /* UV_LDO7_EINT */
291#define WM831X_UV_LDO7_EINT_MASK 0x0040 /* UV_LDO7_EINT */
292#define WM831X_UV_LDO7_EINT_SHIFT 6 /* UV_LDO7_EINT */
293#define WM831X_UV_LDO7_EINT_WIDTH 1 /* UV_LDO7_EINT */
294#define WM831X_UV_LDO6_EINT 0x0020 /* UV_LDO6_EINT */
295#define WM831X_UV_LDO6_EINT_MASK 0x0020 /* UV_LDO6_EINT */
296#define WM831X_UV_LDO6_EINT_SHIFT 5 /* UV_LDO6_EINT */
297#define WM831X_UV_LDO6_EINT_WIDTH 1 /* UV_LDO6_EINT */
298#define WM831X_UV_LDO5_EINT 0x0010 /* UV_LDO5_EINT */
299#define WM831X_UV_LDO5_EINT_MASK 0x0010 /* UV_LDO5_EINT */
300#define WM831X_UV_LDO5_EINT_SHIFT 4 /* UV_LDO5_EINT */
301#define WM831X_UV_LDO5_EINT_WIDTH 1 /* UV_LDO5_EINT */
302#define WM831X_UV_LDO4_EINT 0x0008 /* UV_LDO4_EINT */
303#define WM831X_UV_LDO4_EINT_MASK 0x0008 /* UV_LDO4_EINT */
304#define WM831X_UV_LDO4_EINT_SHIFT 3 /* UV_LDO4_EINT */
305#define WM831X_UV_LDO4_EINT_WIDTH 1 /* UV_LDO4_EINT */
306#define WM831X_UV_LDO3_EINT 0x0004 /* UV_LDO3_EINT */
307#define WM831X_UV_LDO3_EINT_MASK 0x0004 /* UV_LDO3_EINT */
308#define WM831X_UV_LDO3_EINT_SHIFT 2 /* UV_LDO3_EINT */
309#define WM831X_UV_LDO3_EINT_WIDTH 1 /* UV_LDO3_EINT */
310#define WM831X_UV_LDO2_EINT 0x0002 /* UV_LDO2_EINT */
311#define WM831X_UV_LDO2_EINT_MASK 0x0002 /* UV_LDO2_EINT */
312#define WM831X_UV_LDO2_EINT_SHIFT 1 /* UV_LDO2_EINT */
313#define WM831X_UV_LDO2_EINT_WIDTH 1 /* UV_LDO2_EINT */
314#define WM831X_UV_LDO1_EINT 0x0001 /* UV_LDO1_EINT */
315#define WM831X_UV_LDO1_EINT_MASK 0x0001 /* UV_LDO1_EINT */
316#define WM831X_UV_LDO1_EINT_SHIFT 0 /* UV_LDO1_EINT */
317#define WM831X_UV_LDO1_EINT_WIDTH 1 /* UV_LDO1_EINT */
318
319/*
320 * R16404 (0x4014) - Interrupt Status 4
321 */
322#define WM831X_HC_DC2_EINT 0x0200 /* HC_DC2_EINT */
323#define WM831X_HC_DC2_EINT_MASK 0x0200 /* HC_DC2_EINT */
324#define WM831X_HC_DC2_EINT_SHIFT 9 /* HC_DC2_EINT */
325#define WM831X_HC_DC2_EINT_WIDTH 1 /* HC_DC2_EINT */
326#define WM831X_HC_DC1_EINT 0x0100 /* HC_DC1_EINT */
327#define WM831X_HC_DC1_EINT_MASK 0x0100 /* HC_DC1_EINT */
328#define WM831X_HC_DC1_EINT_SHIFT 8 /* HC_DC1_EINT */
329#define WM831X_HC_DC1_EINT_WIDTH 1 /* HC_DC1_EINT */
330#define WM831X_UV_DC4_EINT 0x0008 /* UV_DC4_EINT */
331#define WM831X_UV_DC4_EINT_MASK 0x0008 /* UV_DC4_EINT */
332#define WM831X_UV_DC4_EINT_SHIFT 3 /* UV_DC4_EINT */
333#define WM831X_UV_DC4_EINT_WIDTH 1 /* UV_DC4_EINT */
334#define WM831X_UV_DC3_EINT 0x0004 /* UV_DC3_EINT */
335#define WM831X_UV_DC3_EINT_MASK 0x0004 /* UV_DC3_EINT */
336#define WM831X_UV_DC3_EINT_SHIFT 2 /* UV_DC3_EINT */
337#define WM831X_UV_DC3_EINT_WIDTH 1 /* UV_DC3_EINT */
338#define WM831X_UV_DC2_EINT 0x0002 /* UV_DC2_EINT */
339#define WM831X_UV_DC2_EINT_MASK 0x0002 /* UV_DC2_EINT */
340#define WM831X_UV_DC2_EINT_SHIFT 1 /* UV_DC2_EINT */
341#define WM831X_UV_DC2_EINT_WIDTH 1 /* UV_DC2_EINT */
342#define WM831X_UV_DC1_EINT 0x0001 /* UV_DC1_EINT */
343#define WM831X_UV_DC1_EINT_MASK 0x0001 /* UV_DC1_EINT */
344#define WM831X_UV_DC1_EINT_SHIFT 0 /* UV_DC1_EINT */
345#define WM831X_UV_DC1_EINT_WIDTH 1 /* UV_DC1_EINT */
346
347/*
348 * R16405 (0x4015) - Interrupt Status 5
349 */
350#define WM831X_GP16_EINT 0x8000 /* GP16_EINT */
351#define WM831X_GP16_EINT_MASK 0x8000 /* GP16_EINT */
352#define WM831X_GP16_EINT_SHIFT 15 /* GP16_EINT */
353#define WM831X_GP16_EINT_WIDTH 1 /* GP16_EINT */
354#define WM831X_GP15_EINT 0x4000 /* GP15_EINT */
355#define WM831X_GP15_EINT_MASK 0x4000 /* GP15_EINT */
356#define WM831X_GP15_EINT_SHIFT 14 /* GP15_EINT */
357#define WM831X_GP15_EINT_WIDTH 1 /* GP15_EINT */
358#define WM831X_GP14_EINT 0x2000 /* GP14_EINT */
359#define WM831X_GP14_EINT_MASK 0x2000 /* GP14_EINT */
360#define WM831X_GP14_EINT_SHIFT 13 /* GP14_EINT */
361#define WM831X_GP14_EINT_WIDTH 1 /* GP14_EINT */
362#define WM831X_GP13_EINT 0x1000 /* GP13_EINT */
363#define WM831X_GP13_EINT_MASK 0x1000 /* GP13_EINT */
364#define WM831X_GP13_EINT_SHIFT 12 /* GP13_EINT */
365#define WM831X_GP13_EINT_WIDTH 1 /* GP13_EINT */
366#define WM831X_GP12_EINT 0x0800 /* GP12_EINT */
367#define WM831X_GP12_EINT_MASK 0x0800 /* GP12_EINT */
368#define WM831X_GP12_EINT_SHIFT 11 /* GP12_EINT */
369#define WM831X_GP12_EINT_WIDTH 1 /* GP12_EINT */
370#define WM831X_GP11_EINT 0x0400 /* GP11_EINT */
371#define WM831X_GP11_EINT_MASK 0x0400 /* GP11_EINT */
372#define WM831X_GP11_EINT_SHIFT 10 /* GP11_EINT */
373#define WM831X_GP11_EINT_WIDTH 1 /* GP11_EINT */
374#define WM831X_GP10_EINT 0x0200 /* GP10_EINT */
375#define WM831X_GP10_EINT_MASK 0x0200 /* GP10_EINT */
376#define WM831X_GP10_EINT_SHIFT 9 /* GP10_EINT */
377#define WM831X_GP10_EINT_WIDTH 1 /* GP10_EINT */
378#define WM831X_GP9_EINT 0x0100 /* GP9_EINT */
379#define WM831X_GP9_EINT_MASK 0x0100 /* GP9_EINT */
380#define WM831X_GP9_EINT_SHIFT 8 /* GP9_EINT */
381#define WM831X_GP9_EINT_WIDTH 1 /* GP9_EINT */
382#define WM831X_GP8_EINT 0x0080 /* GP8_EINT */
383#define WM831X_GP8_EINT_MASK 0x0080 /* GP8_EINT */
384#define WM831X_GP8_EINT_SHIFT 7 /* GP8_EINT */
385#define WM831X_GP8_EINT_WIDTH 1 /* GP8_EINT */
386#define WM831X_GP7_EINT 0x0040 /* GP7_EINT */
387#define WM831X_GP7_EINT_MASK 0x0040 /* GP7_EINT */
388#define WM831X_GP7_EINT_SHIFT 6 /* GP7_EINT */
389#define WM831X_GP7_EINT_WIDTH 1 /* GP7_EINT */
390#define WM831X_GP6_EINT 0x0020 /* GP6_EINT */
391#define WM831X_GP6_EINT_MASK 0x0020 /* GP6_EINT */
392#define WM831X_GP6_EINT_SHIFT 5 /* GP6_EINT */
393#define WM831X_GP6_EINT_WIDTH 1 /* GP6_EINT */
394#define WM831X_GP5_EINT 0x0010 /* GP5_EINT */
395#define WM831X_GP5_EINT_MASK 0x0010 /* GP5_EINT */
396#define WM831X_GP5_EINT_SHIFT 4 /* GP5_EINT */
397#define WM831X_GP5_EINT_WIDTH 1 /* GP5_EINT */
398#define WM831X_GP4_EINT 0x0008 /* GP4_EINT */
399#define WM831X_GP4_EINT_MASK 0x0008 /* GP4_EINT */
400#define WM831X_GP4_EINT_SHIFT 3 /* GP4_EINT */
401#define WM831X_GP4_EINT_WIDTH 1 /* GP4_EINT */
402#define WM831X_GP3_EINT 0x0004 /* GP3_EINT */
403#define WM831X_GP3_EINT_MASK 0x0004 /* GP3_EINT */
404#define WM831X_GP3_EINT_SHIFT 2 /* GP3_EINT */
405#define WM831X_GP3_EINT_WIDTH 1 /* GP3_EINT */
406#define WM831X_GP2_EINT 0x0002 /* GP2_EINT */
407#define WM831X_GP2_EINT_MASK 0x0002 /* GP2_EINT */
408#define WM831X_GP2_EINT_SHIFT 1 /* GP2_EINT */
409#define WM831X_GP2_EINT_WIDTH 1 /* GP2_EINT */
410#define WM831X_GP1_EINT 0x0001 /* GP1_EINT */
411#define WM831X_GP1_EINT_MASK 0x0001 /* GP1_EINT */
412#define WM831X_GP1_EINT_SHIFT 0 /* GP1_EINT */
413#define WM831X_GP1_EINT_WIDTH 1 /* GP1_EINT */
414
415/*
416 * R16407 (0x4017) - IRQ Config
417 */
418#define WM831X_IRQ_OD 0x0002 /* IRQ_OD */
419#define WM831X_IRQ_OD_MASK 0x0002 /* IRQ_OD */
420#define WM831X_IRQ_OD_SHIFT 1 /* IRQ_OD */
421#define WM831X_IRQ_OD_WIDTH 1 /* IRQ_OD */
422#define WM831X_IM_IRQ 0x0001 /* IM_IRQ */
423#define WM831X_IM_IRQ_MASK 0x0001 /* IM_IRQ */
424#define WM831X_IM_IRQ_SHIFT 0 /* IM_IRQ */
425#define WM831X_IM_IRQ_WIDTH 1 /* IM_IRQ */
426
427/*
428 * R16408 (0x4018) - System Interrupts Mask
429 */
430#define WM831X_IM_PS_INT 0x8000 /* IM_PS_INT */
431#define WM831X_IM_PS_INT_MASK 0x8000 /* IM_PS_INT */
432#define WM831X_IM_PS_INT_SHIFT 15 /* IM_PS_INT */
433#define WM831X_IM_PS_INT_WIDTH 1 /* IM_PS_INT */
434#define WM831X_IM_TEMP_INT 0x4000 /* IM_TEMP_INT */
435#define WM831X_IM_TEMP_INT_MASK 0x4000 /* IM_TEMP_INT */
436#define WM831X_IM_TEMP_INT_SHIFT 14 /* IM_TEMP_INT */
437#define WM831X_IM_TEMP_INT_WIDTH 1 /* IM_TEMP_INT */
438#define WM831X_IM_GP_INT 0x2000 /* IM_GP_INT */
439#define WM831X_IM_GP_INT_MASK 0x2000 /* IM_GP_INT */
440#define WM831X_IM_GP_INT_SHIFT 13 /* IM_GP_INT */
441#define WM831X_IM_GP_INT_WIDTH 1 /* IM_GP_INT */
442#define WM831X_IM_ON_PIN_INT 0x1000 /* IM_ON_PIN_INT */
443#define WM831X_IM_ON_PIN_INT_MASK 0x1000 /* IM_ON_PIN_INT */
444#define WM831X_IM_ON_PIN_INT_SHIFT 12 /* IM_ON_PIN_INT */
445#define WM831X_IM_ON_PIN_INT_WIDTH 1 /* IM_ON_PIN_INT */
446#define WM831X_IM_WDOG_INT 0x0800 /* IM_WDOG_INT */
447#define WM831X_IM_WDOG_INT_MASK 0x0800 /* IM_WDOG_INT */
448#define WM831X_IM_WDOG_INT_SHIFT 11 /* IM_WDOG_INT */
449#define WM831X_IM_WDOG_INT_WIDTH 1 /* IM_WDOG_INT */
450#define WM831X_IM_TCHDATA_INT 0x0400 /* IM_TCHDATA_INT */
451#define WM831X_IM_TCHDATA_INT_MASK 0x0400 /* IM_TCHDATA_INT */
452#define WM831X_IM_TCHDATA_INT_SHIFT 10 /* IM_TCHDATA_INT */
453#define WM831X_IM_TCHDATA_INT_WIDTH 1 /* IM_TCHDATA_INT */
454#define WM831X_IM_TCHPD_INT 0x0200 /* IM_TCHPD_INT */
455#define WM831X_IM_TCHPD_INT_MASK 0x0200 /* IM_TCHPD_INT */
456#define WM831X_IM_TCHPD_INT_SHIFT 9 /* IM_TCHPD_INT */
457#define WM831X_IM_TCHPD_INT_WIDTH 1 /* IM_TCHPD_INT */
458#define WM831X_IM_AUXADC_INT 0x0100 /* IM_AUXADC_INT */
459#define WM831X_IM_AUXADC_INT_MASK 0x0100 /* IM_AUXADC_INT */
460#define WM831X_IM_AUXADC_INT_SHIFT 8 /* IM_AUXADC_INT */
461#define WM831X_IM_AUXADC_INT_WIDTH 1 /* IM_AUXADC_INT */
462#define WM831X_IM_PPM_INT 0x0080 /* IM_PPM_INT */
463#define WM831X_IM_PPM_INT_MASK 0x0080 /* IM_PPM_INT */
464#define WM831X_IM_PPM_INT_SHIFT 7 /* IM_PPM_INT */
465#define WM831X_IM_PPM_INT_WIDTH 1 /* IM_PPM_INT */
466#define WM831X_IM_CS_INT 0x0040 /* IM_CS_INT */
467#define WM831X_IM_CS_INT_MASK 0x0040 /* IM_CS_INT */
468#define WM831X_IM_CS_INT_SHIFT 6 /* IM_CS_INT */
469#define WM831X_IM_CS_INT_WIDTH 1 /* IM_CS_INT */
470#define WM831X_IM_RTC_INT 0x0020 /* IM_RTC_INT */
471#define WM831X_IM_RTC_INT_MASK 0x0020 /* IM_RTC_INT */
472#define WM831X_IM_RTC_INT_SHIFT 5 /* IM_RTC_INT */
473#define WM831X_IM_RTC_INT_WIDTH 1 /* IM_RTC_INT */
474#define WM831X_IM_OTP_INT 0x0010 /* IM_OTP_INT */
475#define WM831X_IM_OTP_INT_MASK 0x0010 /* IM_OTP_INT */
476#define WM831X_IM_OTP_INT_SHIFT 4 /* IM_OTP_INT */
477#define WM831X_IM_OTP_INT_WIDTH 1 /* IM_OTP_INT */
478#define WM831X_IM_CHILD_INT 0x0008 /* IM_CHILD_INT */
479#define WM831X_IM_CHILD_INT_MASK 0x0008 /* IM_CHILD_INT */
480#define WM831X_IM_CHILD_INT_SHIFT 3 /* IM_CHILD_INT */
481#define WM831X_IM_CHILD_INT_WIDTH 1 /* IM_CHILD_INT */
482#define WM831X_IM_CHG_INT 0x0004 /* IM_CHG_INT */
483#define WM831X_IM_CHG_INT_MASK 0x0004 /* IM_CHG_INT */
484#define WM831X_IM_CHG_INT_SHIFT 2 /* IM_CHG_INT */
485#define WM831X_IM_CHG_INT_WIDTH 1 /* IM_CHG_INT */
486#define WM831X_IM_HC_INT 0x0002 /* IM_HC_INT */
487#define WM831X_IM_HC_INT_MASK 0x0002 /* IM_HC_INT */
488#define WM831X_IM_HC_INT_SHIFT 1 /* IM_HC_INT */
489#define WM831X_IM_HC_INT_WIDTH 1 /* IM_HC_INT */
490#define WM831X_IM_UV_INT 0x0001 /* IM_UV_INT */
491#define WM831X_IM_UV_INT_MASK 0x0001 /* IM_UV_INT */
492#define WM831X_IM_UV_INT_SHIFT 0 /* IM_UV_INT */
493#define WM831X_IM_UV_INT_WIDTH 1 /* IM_UV_INT */
494
495/*
496 * R16409 (0x4019) - Interrupt Status 1 Mask
497 */
498#define WM831X_IM_PPM_SYSLO_EINT 0x8000 /* IM_PPM_SYSLO_EINT */
499#define WM831X_IM_PPM_SYSLO_EINT_MASK 0x8000 /* IM_PPM_SYSLO_EINT */
500#define WM831X_IM_PPM_SYSLO_EINT_SHIFT 15 /* IM_PPM_SYSLO_EINT */
501#define WM831X_IM_PPM_SYSLO_EINT_WIDTH 1 /* IM_PPM_SYSLO_EINT */
502#define WM831X_IM_PPM_PWR_SRC_EINT 0x4000 /* IM_PPM_PWR_SRC_EINT */
503#define WM831X_IM_PPM_PWR_SRC_EINT_MASK 0x4000 /* IM_PPM_PWR_SRC_EINT */
504#define WM831X_IM_PPM_PWR_SRC_EINT_SHIFT 14 /* IM_PPM_PWR_SRC_EINT */
505#define WM831X_IM_PPM_PWR_SRC_EINT_WIDTH 1 /* IM_PPM_PWR_SRC_EINT */
506#define WM831X_IM_PPM_USB_CURR_EINT 0x2000 /* IM_PPM_USB_CURR_EINT */
507#define WM831X_IM_PPM_USB_CURR_EINT_MASK 0x2000 /* IM_PPM_USB_CURR_EINT */
508#define WM831X_IM_PPM_USB_CURR_EINT_SHIFT 13 /* IM_PPM_USB_CURR_EINT */
509#define WM831X_IM_PPM_USB_CURR_EINT_WIDTH 1 /* IM_PPM_USB_CURR_EINT */
510#define WM831X_IM_ON_PIN_EINT 0x1000 /* IM_ON_PIN_EINT */
511#define WM831X_IM_ON_PIN_EINT_MASK 0x1000 /* IM_ON_PIN_EINT */
512#define WM831X_IM_ON_PIN_EINT_SHIFT 12 /* IM_ON_PIN_EINT */
513#define WM831X_IM_ON_PIN_EINT_WIDTH 1 /* IM_ON_PIN_EINT */
514#define WM831X_IM_WDOG_TO_EINT 0x0800 /* IM_WDOG_TO_EINT */
515#define WM831X_IM_WDOG_TO_EINT_MASK 0x0800 /* IM_WDOG_TO_EINT */
516#define WM831X_IM_WDOG_TO_EINT_SHIFT 11 /* IM_WDOG_TO_EINT */
517#define WM831X_IM_WDOG_TO_EINT_WIDTH 1 /* IM_WDOG_TO_EINT */
518#define WM831X_IM_TCHDATA_EINT 0x0400 /* IM_TCHDATA_EINT */
519#define WM831X_IM_TCHDATA_EINT_MASK 0x0400 /* IM_TCHDATA_EINT */
520#define WM831X_IM_TCHDATA_EINT_SHIFT 10 /* IM_TCHDATA_EINT */
521#define WM831X_IM_TCHDATA_EINT_WIDTH 1 /* IM_TCHDATA_EINT */
522#define WM831X_IM_TCHPD_EINT 0x0200 /* IM_TCHPD_EINT */
523#define WM831X_IM_TCHPD_EINT_MASK 0x0200 /* IM_TCHPD_EINT */
524#define WM831X_IM_TCHPD_EINT_SHIFT 9 /* IM_TCHPD_EINT */
525#define WM831X_IM_TCHPD_EINT_WIDTH 1 /* IM_TCHPD_EINT */
526#define WM831X_IM_AUXADC_DATA_EINT 0x0100 /* IM_AUXADC_DATA_EINT */
527#define WM831X_IM_AUXADC_DATA_EINT_MASK 0x0100 /* IM_AUXADC_DATA_EINT */
528#define WM831X_IM_AUXADC_DATA_EINT_SHIFT 8 /* IM_AUXADC_DATA_EINT */
529#define WM831X_IM_AUXADC_DATA_EINT_WIDTH 1 /* IM_AUXADC_DATA_EINT */
530#define WM831X_IM_AUXADC_DCOMP4_EINT 0x0080 /* IM_AUXADC_DCOMP4_EINT */
531#define WM831X_IM_AUXADC_DCOMP4_EINT_MASK 0x0080 /* IM_AUXADC_DCOMP4_EINT */
532#define WM831X_IM_AUXADC_DCOMP4_EINT_SHIFT 7 /* IM_AUXADC_DCOMP4_EINT */
533#define WM831X_IM_AUXADC_DCOMP4_EINT_WIDTH 1 /* IM_AUXADC_DCOMP4_EINT */
534#define WM831X_IM_AUXADC_DCOMP3_EINT 0x0040 /* IM_AUXADC_DCOMP3_EINT */
535#define WM831X_IM_AUXADC_DCOMP3_EINT_MASK 0x0040 /* IM_AUXADC_DCOMP3_EINT */
536#define WM831X_IM_AUXADC_DCOMP3_EINT_SHIFT 6 /* IM_AUXADC_DCOMP3_EINT */
537#define WM831X_IM_AUXADC_DCOMP3_EINT_WIDTH 1 /* IM_AUXADC_DCOMP3_EINT */
538#define WM831X_IM_AUXADC_DCOMP2_EINT 0x0020 /* IM_AUXADC_DCOMP2_EINT */
539#define WM831X_IM_AUXADC_DCOMP2_EINT_MASK 0x0020 /* IM_AUXADC_DCOMP2_EINT */
540#define WM831X_IM_AUXADC_DCOMP2_EINT_SHIFT 5 /* IM_AUXADC_DCOMP2_EINT */
541#define WM831X_IM_AUXADC_DCOMP2_EINT_WIDTH 1 /* IM_AUXADC_DCOMP2_EINT */
542#define WM831X_IM_AUXADC_DCOMP1_EINT 0x0010 /* IM_AUXADC_DCOMP1_EINT */
543#define WM831X_IM_AUXADC_DCOMP1_EINT_MASK 0x0010 /* IM_AUXADC_DCOMP1_EINT */
544#define WM831X_IM_AUXADC_DCOMP1_EINT_SHIFT 4 /* IM_AUXADC_DCOMP1_EINT */
545#define WM831X_IM_AUXADC_DCOMP1_EINT_WIDTH 1 /* IM_AUXADC_DCOMP1_EINT */
546#define WM831X_IM_RTC_PER_EINT 0x0008 /* IM_RTC_PER_EINT */
547#define WM831X_IM_RTC_PER_EINT_MASK 0x0008 /* IM_RTC_PER_EINT */
548#define WM831X_IM_RTC_PER_EINT_SHIFT 3 /* IM_RTC_PER_EINT */
549#define WM831X_IM_RTC_PER_EINT_WIDTH 1 /* IM_RTC_PER_EINT */
550#define WM831X_IM_RTC_ALM_EINT 0x0004 /* IM_RTC_ALM_EINT */
551#define WM831X_IM_RTC_ALM_EINT_MASK 0x0004 /* IM_RTC_ALM_EINT */
552#define WM831X_IM_RTC_ALM_EINT_SHIFT 2 /* IM_RTC_ALM_EINT */
553#define WM831X_IM_RTC_ALM_EINT_WIDTH 1 /* IM_RTC_ALM_EINT */
554#define WM831X_IM_TEMP_THW_EINT 0x0002 /* IM_TEMP_THW_EINT */
555#define WM831X_IM_TEMP_THW_EINT_MASK 0x0002 /* IM_TEMP_THW_EINT */
556#define WM831X_IM_TEMP_THW_EINT_SHIFT 1 /* IM_TEMP_THW_EINT */
557#define WM831X_IM_TEMP_THW_EINT_WIDTH 1 /* IM_TEMP_THW_EINT */
558
559/*
560 * R16410 (0x401A) - Interrupt Status 2 Mask
561 */
562#define WM831X_IM_CHG_BATT_HOT_EINT 0x8000 /* IM_CHG_BATT_HOT_EINT */
563#define WM831X_IM_CHG_BATT_HOT_EINT_MASK 0x8000 /* IM_CHG_BATT_HOT_EINT */
564#define WM831X_IM_CHG_BATT_HOT_EINT_SHIFT 15 /* IM_CHG_BATT_HOT_EINT */
565#define WM831X_IM_CHG_BATT_HOT_EINT_WIDTH 1 /* IM_CHG_BATT_HOT_EINT */
566#define WM831X_IM_CHG_BATT_COLD_EINT 0x4000 /* IM_CHG_BATT_COLD_EINT */
567#define WM831X_IM_CHG_BATT_COLD_EINT_MASK 0x4000 /* IM_CHG_BATT_COLD_EINT */
568#define WM831X_IM_CHG_BATT_COLD_EINT_SHIFT 14 /* IM_CHG_BATT_COLD_EINT */
569#define WM831X_IM_CHG_BATT_COLD_EINT_WIDTH 1 /* IM_CHG_BATT_COLD_EINT */
570#define WM831X_IM_CHG_BATT_FAIL_EINT 0x2000 /* IM_CHG_BATT_FAIL_EINT */
571#define WM831X_IM_CHG_BATT_FAIL_EINT_MASK 0x2000 /* IM_CHG_BATT_FAIL_EINT */
572#define WM831X_IM_CHG_BATT_FAIL_EINT_SHIFT 13 /* IM_CHG_BATT_FAIL_EINT */
573#define WM831X_IM_CHG_BATT_FAIL_EINT_WIDTH 1 /* IM_CHG_BATT_FAIL_EINT */
574#define WM831X_IM_CHG_OV_EINT 0x1000 /* IM_CHG_OV_EINT */
575#define WM831X_IM_CHG_OV_EINT_MASK 0x1000 /* IM_CHG_OV_EINT */
576#define WM831X_IM_CHG_OV_EINT_SHIFT 12 /* IM_CHG_OV_EINT */
577#define WM831X_IM_CHG_OV_EINT_WIDTH 1 /* IM_CHG_OV_EINT */
578#define WM831X_IM_CHG_END_EINT 0x0800 /* IM_CHG_END_EINT */
579#define WM831X_IM_CHG_END_EINT_MASK 0x0800 /* IM_CHG_END_EINT */
580#define WM831X_IM_CHG_END_EINT_SHIFT 11 /* IM_CHG_END_EINT */
581#define WM831X_IM_CHG_END_EINT_WIDTH 1 /* IM_CHG_END_EINT */
582#define WM831X_IM_CHG_TO_EINT 0x0400 /* IM_CHG_TO_EINT */
583#define WM831X_IM_CHG_TO_EINT_MASK 0x0400 /* IM_CHG_TO_EINT */
584#define WM831X_IM_CHG_TO_EINT_SHIFT 10 /* IM_CHG_TO_EINT */
585#define WM831X_IM_CHG_TO_EINT_WIDTH 1 /* IM_CHG_TO_EINT */
586#define WM831X_IM_CHG_MODE_EINT 0x0200 /* IM_CHG_MODE_EINT */
587#define WM831X_IM_CHG_MODE_EINT_MASK 0x0200 /* IM_CHG_MODE_EINT */
588#define WM831X_IM_CHG_MODE_EINT_SHIFT 9 /* IM_CHG_MODE_EINT */
589#define WM831X_IM_CHG_MODE_EINT_WIDTH 1 /* IM_CHG_MODE_EINT */
590#define WM831X_IM_CHG_START_EINT 0x0100 /* IM_CHG_START_EINT */
591#define WM831X_IM_CHG_START_EINT_MASK 0x0100 /* IM_CHG_START_EINT */
592#define WM831X_IM_CHG_START_EINT_SHIFT 8 /* IM_CHG_START_EINT */
593#define WM831X_IM_CHG_START_EINT_WIDTH 1 /* IM_CHG_START_EINT */
594#define WM831X_IM_CS2_EINT 0x0080 /* IM_CS2_EINT */
595#define WM831X_IM_CS2_EINT_MASK 0x0080 /* IM_CS2_EINT */
596#define WM831X_IM_CS2_EINT_SHIFT 7 /* IM_CS2_EINT */
597#define WM831X_IM_CS2_EINT_WIDTH 1 /* IM_CS2_EINT */
598#define WM831X_IM_CS1_EINT 0x0040 /* IM_CS1_EINT */
599#define WM831X_IM_CS1_EINT_MASK 0x0040 /* IM_CS1_EINT */
600#define WM831X_IM_CS1_EINT_SHIFT 6 /* IM_CS1_EINT */
601#define WM831X_IM_CS1_EINT_WIDTH 1 /* IM_CS1_EINT */
602#define WM831X_IM_OTP_CMD_END_EINT 0x0020 /* IM_OTP_CMD_END_EINT */
603#define WM831X_IM_OTP_CMD_END_EINT_MASK 0x0020 /* IM_OTP_CMD_END_EINT */
604#define WM831X_IM_OTP_CMD_END_EINT_SHIFT 5 /* IM_OTP_CMD_END_EINT */
605#define WM831X_IM_OTP_CMD_END_EINT_WIDTH 1 /* IM_OTP_CMD_END_EINT */
606#define WM831X_IM_OTP_ERR_EINT 0x0010 /* IM_OTP_ERR_EINT */
607#define WM831X_IM_OTP_ERR_EINT_MASK 0x0010 /* IM_OTP_ERR_EINT */
608#define WM831X_IM_OTP_ERR_EINT_SHIFT 4 /* IM_OTP_ERR_EINT */
609#define WM831X_IM_OTP_ERR_EINT_WIDTH 1 /* IM_OTP_ERR_EINT */
610#define WM831X_IM_PS_POR_EINT 0x0004 /* IM_PS_POR_EINT */
611#define WM831X_IM_PS_POR_EINT_MASK 0x0004 /* IM_PS_POR_EINT */
612#define WM831X_IM_PS_POR_EINT_SHIFT 2 /* IM_PS_POR_EINT */
613#define WM831X_IM_PS_POR_EINT_WIDTH 1 /* IM_PS_POR_EINT */
614#define WM831X_IM_PS_SLEEP_OFF_EINT 0x0002 /* IM_PS_SLEEP_OFF_EINT */
615#define WM831X_IM_PS_SLEEP_OFF_EINT_MASK 0x0002 /* IM_PS_SLEEP_OFF_EINT */
616#define WM831X_IM_PS_SLEEP_OFF_EINT_SHIFT 1 /* IM_PS_SLEEP_OFF_EINT */
617#define WM831X_IM_PS_SLEEP_OFF_EINT_WIDTH 1 /* IM_PS_SLEEP_OFF_EINT */
618#define WM831X_IM_PS_ON_WAKE_EINT 0x0001 /* IM_PS_ON_WAKE_EINT */
619#define WM831X_IM_PS_ON_WAKE_EINT_MASK 0x0001 /* IM_PS_ON_WAKE_EINT */
620#define WM831X_IM_PS_ON_WAKE_EINT_SHIFT 0 /* IM_PS_ON_WAKE_EINT */
621#define WM831X_IM_PS_ON_WAKE_EINT_WIDTH 1 /* IM_PS_ON_WAKE_EINT */
622
623/*
624 * R16411 (0x401B) - Interrupt Status 3 Mask
625 */
626#define WM831X_IM_UV_LDO10_EINT 0x0200 /* IM_UV_LDO10_EINT */
627#define WM831X_IM_UV_LDO10_EINT_MASK 0x0200 /* IM_UV_LDO10_EINT */
628#define WM831X_IM_UV_LDO10_EINT_SHIFT 9 /* IM_UV_LDO10_EINT */
629#define WM831X_IM_UV_LDO10_EINT_WIDTH 1 /* IM_UV_LDO10_EINT */
630#define WM831X_IM_UV_LDO9_EINT 0x0100 /* IM_UV_LDO9_EINT */
631#define WM831X_IM_UV_LDO9_EINT_MASK 0x0100 /* IM_UV_LDO9_EINT */
632#define WM831X_IM_UV_LDO9_EINT_SHIFT 8 /* IM_UV_LDO9_EINT */
633#define WM831X_IM_UV_LDO9_EINT_WIDTH 1 /* IM_UV_LDO9_EINT */
634#define WM831X_IM_UV_LDO8_EINT 0x0080 /* IM_UV_LDO8_EINT */
635#define WM831X_IM_UV_LDO8_EINT_MASK 0x0080 /* IM_UV_LDO8_EINT */
636#define WM831X_IM_UV_LDO8_EINT_SHIFT 7 /* IM_UV_LDO8_EINT */
637#define WM831X_IM_UV_LDO8_EINT_WIDTH 1 /* IM_UV_LDO8_EINT */
638#define WM831X_IM_UV_LDO7_EINT 0x0040 /* IM_UV_LDO7_EINT */
639#define WM831X_IM_UV_LDO7_EINT_MASK 0x0040 /* IM_UV_LDO7_EINT */
640#define WM831X_IM_UV_LDO7_EINT_SHIFT 6 /* IM_UV_LDO7_EINT */
641#define WM831X_IM_UV_LDO7_EINT_WIDTH 1 /* IM_UV_LDO7_EINT */
642#define WM831X_IM_UV_LDO6_EINT 0x0020 /* IM_UV_LDO6_EINT */
643#define WM831X_IM_UV_LDO6_EINT_MASK 0x0020 /* IM_UV_LDO6_EINT */
644#define WM831X_IM_UV_LDO6_EINT_SHIFT 5 /* IM_UV_LDO6_EINT */
645#define WM831X_IM_UV_LDO6_EINT_WIDTH 1 /* IM_UV_LDO6_EINT */
646#define WM831X_IM_UV_LDO5_EINT 0x0010 /* IM_UV_LDO5_EINT */
647#define WM831X_IM_UV_LDO5_EINT_MASK 0x0010 /* IM_UV_LDO5_EINT */
648#define WM831X_IM_UV_LDO5_EINT_SHIFT 4 /* IM_UV_LDO5_EINT */
649#define WM831X_IM_UV_LDO5_EINT_WIDTH 1 /* IM_UV_LDO5_EINT */
650#define WM831X_IM_UV_LDO4_EINT 0x0008 /* IM_UV_LDO4_EINT */
651#define WM831X_IM_UV_LDO4_EINT_MASK 0x0008 /* IM_UV_LDO4_EINT */
652#define WM831X_IM_UV_LDO4_EINT_SHIFT 3 /* IM_UV_LDO4_EINT */
653#define WM831X_IM_UV_LDO4_EINT_WIDTH 1 /* IM_UV_LDO4_EINT */
654#define WM831X_IM_UV_LDO3_EINT 0x0004 /* IM_UV_LDO3_EINT */
655#define WM831X_IM_UV_LDO3_EINT_MASK 0x0004 /* IM_UV_LDO3_EINT */
656#define WM831X_IM_UV_LDO3_EINT_SHIFT 2 /* IM_UV_LDO3_EINT */
657#define WM831X_IM_UV_LDO3_EINT_WIDTH 1 /* IM_UV_LDO3_EINT */
658#define WM831X_IM_UV_LDO2_EINT 0x0002 /* IM_UV_LDO2_EINT */
659#define WM831X_IM_UV_LDO2_EINT_MASK 0x0002 /* IM_UV_LDO2_EINT */
660#define WM831X_IM_UV_LDO2_EINT_SHIFT 1 /* IM_UV_LDO2_EINT */
661#define WM831X_IM_UV_LDO2_EINT_WIDTH 1 /* IM_UV_LDO2_EINT */
662#define WM831X_IM_UV_LDO1_EINT 0x0001 /* IM_UV_LDO1_EINT */
663#define WM831X_IM_UV_LDO1_EINT_MASK 0x0001 /* IM_UV_LDO1_EINT */
664#define WM831X_IM_UV_LDO1_EINT_SHIFT 0 /* IM_UV_LDO1_EINT */
665#define WM831X_IM_UV_LDO1_EINT_WIDTH 1 /* IM_UV_LDO1_EINT */
666
667/*
668 * R16412 (0x401C) - Interrupt Status 4 Mask
669 */
670#define WM831X_IM_HC_DC2_EINT 0x0200 /* IM_HC_DC2_EINT */
671#define WM831X_IM_HC_DC2_EINT_MASK 0x0200 /* IM_HC_DC2_EINT */
672#define WM831X_IM_HC_DC2_EINT_SHIFT 9 /* IM_HC_DC2_EINT */
673#define WM831X_IM_HC_DC2_EINT_WIDTH 1 /* IM_HC_DC2_EINT */
674#define WM831X_IM_HC_DC1_EINT 0x0100 /* IM_HC_DC1_EINT */
675#define WM831X_IM_HC_DC1_EINT_MASK 0x0100 /* IM_HC_DC1_EINT */
676#define WM831X_IM_HC_DC1_EINT_SHIFT 8 /* IM_HC_DC1_EINT */
677#define WM831X_IM_HC_DC1_EINT_WIDTH 1 /* IM_HC_DC1_EINT */
678#define WM831X_IM_UV_DC4_EINT 0x0008 /* IM_UV_DC4_EINT */
679#define WM831X_IM_UV_DC4_EINT_MASK 0x0008 /* IM_UV_DC4_EINT */
680#define WM831X_IM_UV_DC4_EINT_SHIFT 3 /* IM_UV_DC4_EINT */
681#define WM831X_IM_UV_DC4_EINT_WIDTH 1 /* IM_UV_DC4_EINT */
682#define WM831X_IM_UV_DC3_EINT 0x0004 /* IM_UV_DC3_EINT */
683#define WM831X_IM_UV_DC3_EINT_MASK 0x0004 /* IM_UV_DC3_EINT */
684#define WM831X_IM_UV_DC3_EINT_SHIFT 2 /* IM_UV_DC3_EINT */
685#define WM831X_IM_UV_DC3_EINT_WIDTH 1 /* IM_UV_DC3_EINT */
686#define WM831X_IM_UV_DC2_EINT 0x0002 /* IM_UV_DC2_EINT */
687#define WM831X_IM_UV_DC2_EINT_MASK 0x0002 /* IM_UV_DC2_EINT */
688#define WM831X_IM_UV_DC2_EINT_SHIFT 1 /* IM_UV_DC2_EINT */
689#define WM831X_IM_UV_DC2_EINT_WIDTH 1 /* IM_UV_DC2_EINT */
690#define WM831X_IM_UV_DC1_EINT 0x0001 /* IM_UV_DC1_EINT */
691#define WM831X_IM_UV_DC1_EINT_MASK 0x0001 /* IM_UV_DC1_EINT */
692#define WM831X_IM_UV_DC1_EINT_SHIFT 0 /* IM_UV_DC1_EINT */
693#define WM831X_IM_UV_DC1_EINT_WIDTH 1 /* IM_UV_DC1_EINT */
694
695/*
696 * R16413 (0x401D) - Interrupt Status 5 Mask
697 */
698#define WM831X_IM_GP16_EINT 0x8000 /* IM_GP16_EINT */
699#define WM831X_IM_GP16_EINT_MASK 0x8000 /* IM_GP16_EINT */
700#define WM831X_IM_GP16_EINT_SHIFT 15 /* IM_GP16_EINT */
701#define WM831X_IM_GP16_EINT_WIDTH 1 /* IM_GP16_EINT */
702#define WM831X_IM_GP15_EINT 0x4000 /* IM_GP15_EINT */
703#define WM831X_IM_GP15_EINT_MASK 0x4000 /* IM_GP15_EINT */
704#define WM831X_IM_GP15_EINT_SHIFT 14 /* IM_GP15_EINT */
705#define WM831X_IM_GP15_EINT_WIDTH 1 /* IM_GP15_EINT */
706#define WM831X_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */
707#define WM831X_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */
708#define WM831X_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */
709#define WM831X_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */
710#define WM831X_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */
711#define WM831X_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */
712#define WM831X_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */
713#define WM831X_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */
714#define WM831X_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */
715#define WM831X_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */
716#define WM831X_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */
717#define WM831X_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */
718#define WM831X_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
719#define WM831X_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
720#define WM831X_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */
721#define WM831X_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
722#define WM831X_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
723#define WM831X_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
724#define WM831X_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */
725#define WM831X_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
726#define WM831X_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
727#define WM831X_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
728#define WM831X_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */
729#define WM831X_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
730#define WM831X_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
731#define WM831X_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
732#define WM831X_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */
733#define WM831X_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
734#define WM831X_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
735#define WM831X_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
736#define WM831X_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */
737#define WM831X_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
738#define WM831X_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
739#define WM831X_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
740#define WM831X_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
741#define WM831X_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
742#define WM831X_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
743#define WM831X_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
744#define WM831X_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
745#define WM831X_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
746#define WM831X_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
747#define WM831X_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
748#define WM831X_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
749#define WM831X_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
750#define WM831X_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
751#define WM831X_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
752#define WM831X_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
753#define WM831X_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
754#define WM831X_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
755#define WM831X_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
756#define WM831X_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
757#define WM831X_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
758#define WM831X_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
759#define WM831X_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
760#define WM831X_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
761#define WM831X_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
762
763
764#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 10:13:39 -0500