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authorJon Loeliger <jdl@freescale.com>2008-01-25 17:31:01 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-01-28 09:45:26 -0500
commit6e050d4e35659d26f4ca4c63d47e606d8aea763d (patch)
tree364408f7390c4b6b830e18c9cb0daf5f3a33f905
parentc42f3ad7f1bf17f31c3febdc71034ed6d793d40f (diff)
[POWERPC] 86xx: Convert all 86xx DTS files to /dts-v1/ format.
Also fixed a few minor indent problems as well. Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat
-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts227
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts333
2 files changed, 281 insertions, 279 deletions
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index d98715cbda28..16c947b8a721 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -8,6 +8,7 @@
8 * by the Free Software Foundation. 8 * by the Free Software Foundation.
9 */ 9 */
10 10
11/dts-v1/;
11 12
12/ { 13/ {
13 model = "MPC8610HPCD"; 14 model = "MPC8610HPCD";
@@ -29,11 +30,11 @@
29 PowerPC,8610@0 { 30 PowerPC,8610@0 {
30 device_type = "cpu"; 31 device_type = "cpu";
31 reg = <0>; 32 reg = <0>;
32 d-cache-line-size = <d# 32>; // bytes 33 d-cache-line-size = <32>;
33 i-cache-line-size = <d# 32>; // bytes 34 i-cache-line-size = <32>;
34 d-cache-size = <8000>; // L1, 32K 35 d-cache-size = <32768>; // L1
35 i-cache-size = <8000>; // L1, 32K 36 i-cache-size = <32768>; // L1
36 timebase-frequency = <0>; // 33 MHz, from uboot 37 timebase-frequency = <0>; // From uboot
37 bus-frequency = <0>; // From uboot 38 bus-frequency = <0>; // From uboot
38 clock-frequency = <0>; // From uboot 39 clock-frequency = <0>; // From uboot
39 }; 40 };
@@ -41,7 +42,7 @@
41 42
42 memory { 43 memory {
43 device_type = "memory"; 44 device_type = "memory";
44 reg = <00000000 20000000>; // 512M at 0x0 45 reg = <0x00000000 0x20000000>; // 512M at 0x0
45 }; 46 };
46 47
47 soc@e0000000 { 48 soc@e0000000 {
@@ -50,8 +51,8 @@
50 #interrupt-cells = <2>; 51 #interrupt-cells = <2>;
51 device_type = "soc"; 52 device_type = "soc";
52 compatible = "fsl,mpc8610-immr", "simple-bus"; 53 compatible = "fsl,mpc8610-immr", "simple-bus";
53 ranges = <0 e0000000 00100000>; 54 ranges = <0x0 0xe0000000 0x00100000>;
54 reg = <e0000000 1000>; 55 reg = <0xe0000000 0x1000>;
55 bus-frequency = <0>; 56 bus-frequency = <0>;
56 57
57 i2c@3000 { 58 i2c@3000 {
@@ -59,17 +60,17 @@
59 #size-cells = <0>; 60 #size-cells = <0>;
60 cell-index = <0>; 61 cell-index = <0>;
61 compatible = "fsl-i2c"; 62 compatible = "fsl-i2c";
62 reg = <3000 100>; 63 reg = <0x3000 0x100>;
63 interrupts = <2b 2>; 64 interrupts = <43 2>;
64 interrupt-parent = <&mpic>; 65 interrupt-parent = <&mpic>;
65 dfsrr; 66 dfsrr;
66 67
67 cs4270:codec@4f { 68 cs4270:codec@4f {
68 compatible = "cirrus,cs4270"; 69 compatible = "cirrus,cs4270";
69 reg = <4f>; 70 reg = <0x4f>;
70 /* MCLK source is a stand-alone oscillator */ 71 /* MCLK source is a stand-alone oscillator */
71 clock-frequency = <bb8000>; 72 clock-frequency = <12288000>;
72 }; 73 };
73 }; 74 };
74 75
75 i2c@3100 { 76 i2c@3100 {
@@ -77,8 +78,8 @@
77 #size-cells = <0>; 78 #size-cells = <0>;
78 cell-index = <1>; 79 cell-index = <1>;
79 compatible = "fsl-i2c"; 80 compatible = "fsl-i2c";
80 reg = <3100 100>; 81 reg = <0x3100 0x100>;
81 interrupts = <2b 2>; 82 interrupts = <43 2>;
82 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
83 dfsrr; 84 dfsrr;
84 }; 85 };
@@ -87,9 +88,9 @@
87 cell-index = <0>; 88 cell-index = <0>;
88 device_type = "serial"; 89 device_type = "serial";
89 compatible = "ns16550"; 90 compatible = "ns16550";
90 reg = <4500 100>; 91 reg = <0x4500 0x100>;
91 clock-frequency = <0>; 92 clock-frequency = <0>;
92 interrupts = <2a 2>; 93 interrupts = <42 2>;
93 interrupt-parent = <&mpic>; 94 interrupt-parent = <&mpic>;
94 }; 95 };
95 96
@@ -97,9 +98,9 @@
97 cell-index = <1>; 98 cell-index = <1>;
98 device_type = "serial"; 99 device_type = "serial";
99 compatible = "ns16550"; 100 compatible = "ns16550";
100 reg = <4600 100>; 101 reg = <0x4600 0x100>;
101 clock-frequency = <0>; 102 clock-frequency = <0>;
102 interrupts = <1c 2>; 103 interrupts = <28 2>;
103 interrupt-parent = <&mpic>; 104 interrupt-parent = <&mpic>;
104 }; 105 };
105 106
@@ -108,7 +109,7 @@
108 interrupt-controller; 109 interrupt-controller;
109 #address-cells = <0>; 110 #address-cells = <0>;
110 #interrupt-cells = <2>; 111 #interrupt-cells = <2>;
111 reg = <40000 40000>; 112 reg = <0x40000 0x40000>;
112 compatible = "chrp,open-pic"; 113 compatible = "chrp,open-pic";
113 device_type = "open-pic"; 114 device_type = "open-pic";
114 big-endian; 115 big-endian;
@@ -116,16 +117,16 @@
116 117
117 global-utilities@e0000 { 118 global-utilities@e0000 {
118 compatible = "fsl,mpc8610-guts"; 119 compatible = "fsl,mpc8610-guts";
119 reg = <e0000 1000>; 120 reg = <0xe0000 0x1000>;
120 fsl,has-rstcr; 121 fsl,has-rstcr;
121 }; 122 };
122 123
123 i2s@16000 { 124 i2s@16000 {
124 compatible = "fsl,mpc8610-ssi"; 125 compatible = "fsl,mpc8610-ssi";
125 cell-index = <0>; 126 cell-index = <0>;
126 reg = <16000 100>; 127 reg = <0x16000 0x100>;
127 interrupt-parent = <&mpic>; 128 interrupt-parent = <&mpic>;
128 interrupts = <3e 2>; 129 interrupts = <62 2>;
129 fsl,mode = "i2s-slave"; 130 fsl,mode = "i2s-slave";
130 codec-handle = <&cs4270>; 131 codec-handle = <&cs4270>;
131 }; 132 };
@@ -133,94 +134,94 @@
133 ssi@16100 { 134 ssi@16100 {
134 compatible = "fsl,mpc8610-ssi"; 135 compatible = "fsl,mpc8610-ssi";
135 cell-index = <1>; 136 cell-index = <1>;
136 reg = <16100 100>; 137 reg = <0x16100 0x100>;
137 interrupt-parent = <&mpic>; 138 interrupt-parent = <&mpic>;
138 interrupts = <3f 2>; 139 interrupts = <63 2>;
139 }; 140 };
140 141
141 dma@21300 { 142 dma@21300 {
142 #address-cells = <1>; 143 #address-cells = <1>;
143 #size-cells = <1>; 144 #size-cells = <1>;
144 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma"; 145 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
145 cell-index = <0>; 146 cell-index = <0>;
146 reg = <21300 4>; /* DMA general status register */ 147 reg = <0x21300 0x4>; /* DMA general status register */
147 ranges = <0 21100 200>; 148 ranges = <0x0 0x21100 0x200>;
148 149
149 dma-channel@0 { 150 dma-channel@0 {
150 compatible = "fsl,mpc8610-dma-channel", 151 compatible = "fsl,mpc8610-dma-channel",
151 "fsl,eloplus-dma-channel"; 152 "fsl,eloplus-dma-channel";
152 cell-index = <0>; 153 cell-index = <0>;
153 reg = <0 80>; 154 reg = <0x0 0x80>;
154 interrupt-parent = <&mpic>; 155 interrupt-parent = <&mpic>;
155 interrupts = <14 2>; 156 interrupts = <20 2>;
156 }; 157 };
157 dma-channel@1 { 158 dma-channel@1 {
158 compatible = "fsl,mpc8610-dma-channel", 159 compatible = "fsl,mpc8610-dma-channel",
159 "fsl,eloplus-dma-channel"; 160 "fsl,eloplus-dma-channel";
160 cell-index = <1>; 161 cell-index = <1>;
161 reg = <80 80>; 162 reg = <0x80 0x80>;
162 interrupt-parent = <&mpic>; 163 interrupt-parent = <&mpic>;
163 interrupts = <15 2>; 164 interrupts = <21 2>;
164 }; 165 };
165 dma-channel@2 { 166 dma-channel@2 {
166 compatible = "fsl,mpc8610-dma-channel", 167 compatible = "fsl,mpc8610-dma-channel",
167 "fsl,eloplus-dma-channel"; 168 "fsl,eloplus-dma-channel";
168 cell-index = <2>; 169 cell-index = <2>;
169 reg = <100 80>; 170 reg = <0x100 0x80>;
170 interrupt-parent = <&mpic>; 171 interrupt-parent = <&mpic>;
171 interrupts = <16 2>; 172 interrupts = <22 2>;
172 }; 173 };
173 dma-channel@3 { 174 dma-channel@3 {
174 compatible = "fsl,mpc8610-dma-channel", 175 compatible = "fsl,mpc8610-dma-channel",
175 "fsl,eloplus-dma-channel"; 176 "fsl,eloplus-dma-channel";
176 cell-index = <3>; 177 cell-index = <3>;
177 reg = <180 80>; 178 reg = <0x180 0x80>;
178 interrupt-parent = <&mpic>; 179 interrupt-parent = <&mpic>;
179 interrupts = <17 2>; 180 interrupts = <23 2>;
180 }; 181 };
181 }; 182 };
182 183
183 dma@c300 { 184 dma@c300 {
184 #address-cells = <1>; 185 #address-cells = <1>;
185 #size-cells = <1>; 186 #size-cells = <1>;
186 compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma"; 187 compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
187 cell-index = <1>; 188 cell-index = <1>;
188 reg = <c300 4>; /* DMA general status register */ 189 reg = <0xc300 0x4>; /* DMA general status register */
189 ranges = <0 c100 200>; 190 ranges = <0x0 0xc100 0x200>;
190 191
191 dma-channel@0 { 192 dma-channel@0 {
192 compatible = "fsl,mpc8610-dma-channel", 193 compatible = "fsl,mpc8610-dma-channel",
193 "fsl,mpc8540-dma-channel"; 194 "fsl,mpc8540-dma-channel";
194 cell-index = <0>; 195 cell-index = <0>;
195 reg = <0 80>; 196 reg = <0x0 0x80>;
196 interrupt-parent = <&mpic>; 197 interrupt-parent = <&mpic>;
197 interrupts = <3c 2>; 198 interrupts = <60 2>;
198 }; 199 };
199 dma-channel@1 { 200 dma-channel@1 {
200 compatible = "fsl,mpc8610-dma-channel", 201 compatible = "fsl,mpc8610-dma-channel",
201 "fsl,mpc8540-dma-channel"; 202 "fsl,mpc8540-dma-channel";
202 cell-index = <1>; 203 cell-index = <1>;
203 reg = <80 80>; 204 reg = <0x80 0x80>;
204 interrupt-parent = <&mpic>; 205 interrupt-parent = <&mpic>;
205 interrupts = <3d 2>; 206 interrupts = <61 2>;
206 }; 207 };
207 dma-channel@2 { 208 dma-channel@2 {
208 compatible = "fsl,mpc8610-dma-channel", 209 compatible = "fsl,mpc8610-dma-channel",
209 "fsl,mpc8540-dma-channel"; 210 "fsl,mpc8540-dma-channel";
210 cell-index = <2>; 211 cell-index = <2>;
211 reg = <100 80>; 212 reg = <0x100 0x80>;
212 interrupt-parent = <&mpic>; 213 interrupt-parent = <&mpic>;
213 interrupts = <3e 2>; 214 interrupts = <62 2>;
214 }; 215 };
215 dma-channel@3 { 216 dma-channel@3 {
216 compatible = "fsl,mpc8610-dma-channel", 217 compatible = "fsl,mpc8610-dma-channel",
217 "fsl,mpc8540-dma-channel"; 218 "fsl,mpc8540-dma-channel";
218 cell-index = <3>; 219 cell-index = <3>;
219 reg = <180 80>; 220 reg = <0x180 0x80>;
220 interrupt-parent = <&mpic>; 221 interrupt-parent = <&mpic>;
221 interrupts = <3f 2>; 222 interrupts = <63 2>;
222 }; 223 };
223 }; 224 };
224 225
225 }; 226 };
226 227
@@ -231,26 +232,26 @@
231 #interrupt-cells = <1>; 232 #interrupt-cells = <1>;
232 #size-cells = <2>; 233 #size-cells = <2>;
233 #address-cells = <3>; 234 #address-cells = <3>;
234 reg = <e0008000 1000>; 235 reg = <0xe0008000 0x1000>;
235 bus-range = <0 0>; 236 bus-range = <0 0>;
236 ranges = <02000000 0 80000000 80000000 0 10000000 237 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
237 01000000 0 00000000 e1000000 0 00100000>; 238 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
238 clock-frequency = <1fca055>; 239 clock-frequency = <33333333>;
239 interrupt-parent = <&mpic>; 240 interrupt-parent = <&mpic>;
240 interrupts = <18 2>; 241 interrupts = <24 2>;
241 interrupt-map-mask = <f800 0 0 7>; 242 interrupt-map-mask = <0xf800 0 0 7>;
242 interrupt-map = < 243 interrupt-map = <
243 /* IDSEL 0x11 */ 244 /* IDSEL 0x11 */
244 8800 0 0 1 &mpic 4 1 245 0x8800 0 0 1 &mpic 4 1
245 8800 0 0 2 &mpic 5 1 246 0x8800 0 0 2 &mpic 5 1
246 8800 0 0 3 &mpic 6 1 247 0x8800 0 0 3 &mpic 6 1
247 8800 0 0 4 &mpic 7 1 248 0x8800 0 0 4 &mpic 7 1
248 249
249 /* IDSEL 0x12 */ 250 /* IDSEL 0x12 */
250 9000 0 0 1 &mpic 5 1 251 0x9000 0 0 1 &mpic 5 1
251 9000 0 0 2 &mpic 6 1 252 0x9000 0 0 2 &mpic 6 1
252 9000 0 0 3 &mpic 7 1 253 0x9000 0 0 3 &mpic 7 1
253 9000 0 0 4 &mpic 4 1 254 0x9000 0 0 4 &mpic 4 1
254 >; 255 >;
255 }; 256 };
256 257
@@ -261,28 +262,28 @@
261 #interrupt-cells = <1>; 262 #interrupt-cells = <1>;
262 #size-cells = <2>; 263 #size-cells = <2>;
263 #address-cells = <3>; 264 #address-cells = <3>;
264 reg = <e000a000 1000>; 265 reg = <0xe000a000 0x1000>;
265 bus-range = <1 3>; 266 bus-range = <1 3>;
266 ranges = <02000000 0 a0000000 a0000000 0 10000000 267 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
267 01000000 0 00000000 e3000000 0 00100000>; 268 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
268 clock-frequency = <1fca055>; 269 clock-frequency = <33333333>;
269 interrupt-parent = <&mpic>; 270 interrupt-parent = <&mpic>;
270 interrupts = <1a 2>; 271 interrupts = <26 2>;
271 interrupt-map-mask = <f800 0 0 7>; 272 interrupt-map-mask = <0xf800 0 0 7>;
272 273
273 interrupt-map = < 274 interrupt-map = <
274 /* IDSEL 0x1b */ 275 /* IDSEL 0x1b */
275 d800 0 0 1 &mpic 2 1 276 0xd800 0 0 1 &mpic 2 1
276 277
277 /* IDSEL 0x1c*/ 278 /* IDSEL 0x1c*/
278 e000 0 0 1 &mpic 1 1 279 0xe000 0 0 1 &mpic 1 1
279 e000 0 0 2 &mpic 1 1 280 0xe000 0 0 2 &mpic 1 1
280 e000 0 0 3 &mpic 1 1 281 0xe000 0 0 3 &mpic 1 1
281 e000 0 0 4 &mpic 1 1 282 0xe000 0 0 4 &mpic 1 1
282 283
283 /* IDSEL 0x1f */ 284 /* IDSEL 0x1f */
284 f800 0 0 1 &mpic 3 0 285 0xf800 0 0 1 &mpic 3 0
285 f800 0 0 2 &mpic 0 1 286 0xf800 0 0 2 &mpic 0 1
286 >; 287 >;
287 288
288 pcie@0 { 289 pcie@0 {
@@ -290,22 +291,22 @@
290 #size-cells = <2>; 291 #size-cells = <2>;
291 #address-cells = <3>; 292 #address-cells = <3>;
292 device_type = "pci"; 293 device_type = "pci";
293 ranges = <02000000 0 a0000000 294 ranges = <0x02000000 0x0 0xa0000000
294 02000000 0 a0000000 295 0x02000000 0x0 0xa0000000
295 0 10000000 296 0x0 0x10000000
296 01000000 0 00000000 297 0x01000000 0x0 0x00000000
297 01000000 0 00000000 298 0x01000000 0x0 0x00000000
298 0 00100000>; 299 0x0 0x00100000>;
299 uli1575@0 { 300 uli1575@0 {
300 reg = <0 0 0 0 0>; 301 reg = <0 0 0 0 0>;
301 #size-cells = <2>; 302 #size-cells = <2>;
302 #address-cells = <3>; 303 #address-cells = <3>;
303 ranges = <02000000 0 a0000000 304 ranges = <0x02000000 0x0 0xa0000000
304 02000000 0 a0000000 305 0x02000000 0x0 0xa0000000
305 0 10000000 306 0x0 0x10000000
306 01000000 0 00000000 307 0x01000000 0x0 0x00000000
307 01000000 0 00000000 308 0x01000000 0x0 0x00000000
308 0 00100000>; 309 0x0 0x00100000>;
309 }; 310 };
310 }; 311 };
311 }; 312 };
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 556a9cac0793..79385bcd5c5f 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -9,6 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/;
12 13
13/ { 14/ {
14 model = "MPC8641HPCN"; 15 model = "MPC8641HPCN";
@@ -34,22 +35,22 @@
34 PowerPC,8641@0 { 35 PowerPC,8641@0 {
35 device_type = "cpu"; 36 device_type = "cpu";
36 reg = <0>; 37 reg = <0>;
37 d-cache-line-size = <20>; // 32 bytes 38 d-cache-line-size = <32>;
38 i-cache-line-size = <20>; // 32 bytes 39 i-cache-line-size = <32>;
39 d-cache-size = <8000>; // L1, 32K 40 d-cache-size = <32768>; // L1
40 i-cache-size = <8000>; // L1, 32K 41 i-cache-size = <32768>; // L1
41 timebase-frequency = <0>; // 33 MHz, from uboot 42 timebase-frequency = <0>; // From uboot
42 bus-frequency = <0>; // From uboot 43 bus-frequency = <0>; // From uboot
43 clock-frequency = <0>; // From uboot 44 clock-frequency = <0>; // From uboot
44 }; 45 };
45 PowerPC,8641@1 { 46 PowerPC,8641@1 {
46 device_type = "cpu"; 47 device_type = "cpu";
47 reg = <1>; 48 reg = <1>;
48 d-cache-line-size = <20>; // 32 bytes 49 d-cache-line-size = <32>;
49 i-cache-line-size = <20>; // 32 bytes 50 i-cache-line-size = <32>;
50 d-cache-size = <8000>; // L1, 32K 51 d-cache-size = <32768>;
51 i-cache-size = <8000>; // L1, 32K 52 i-cache-size = <32768>;
52 timebase-frequency = <0>; // 33 MHz, from uboot 53 timebase-frequency = <0>; // From uboot
53 bus-frequency = <0>; // From uboot 54 bus-frequency = <0>; // From uboot
54 clock-frequency = <0>; // From uboot 55 clock-frequency = <0>; // From uboot
55 }; 56 };
@@ -57,45 +58,45 @@
57 58
58 memory { 59 memory {
59 device_type = "memory"; 60 device_type = "memory";
60 reg = <00000000 40000000>; // 1G at 0x0 61 reg = <0x00000000 0x40000000>; // 1G at 0x0
61 }; 62 };
62 63
63 localbus@f8005000 { 64 localbus@f8005000 {
64 #address-cells = <2>; 65 #address-cells = <2>;
65 #size-cells = <1>; 66 #size-cells = <1>;
66 compatible = "fsl,mpc8641-localbus", "simple-bus"; 67 compatible = "fsl,mpc8641-localbus", "simple-bus";
67 reg = <f8005000 1000>; 68 reg = <0xf8005000 0x1000>;
68 interrupts = <13 2>; 69 interrupts = <19 2>;
69 interrupt-parent = <&mpic>; 70 interrupt-parent = <&mpic>;
70 71
71 ranges = <0 0 ff800000 00800000 72 ranges = <0 0 0xff800000 0x00800000
72 1 0 fe000000 01000000 73 1 0 0xfe000000 0x01000000
73 2 0 f8200000 00100000 74 2 0 0xf8200000 0x00100000
74 3 0 f8100000 00100000>; 75 3 0 0xf8100000 0x00100000>;
75 76
76 flash@0,0 { 77 flash@0,0 {
77 compatible = "cfi-flash"; 78 compatible = "cfi-flash";
78 reg = <0 0 00800000>; 79 reg = <0 0 0x00800000>;
79 bank-width = <2>; 80 bank-width = <2>;
80 device-width = <2>; 81 device-width = <2>;
81 #address-cells = <1>; 82 #address-cells = <1>;
82 #size-cells = <1>; 83 #size-cells = <1>;
83 partition@0 { 84 partition@0 {
84 label = "kernel"; 85 label = "kernel";
85 reg = <00000000 00300000>; 86 reg = <0x00000000 0x00300000>;
86 }; 87 };
87 partition@300000 { 88 partition@300000 {
88 label = "firmware b"; 89 label = "firmware b";
89 reg = <00300000 00100000>; 90 reg = <0x00300000 0x00100000>;
90 read-only; 91 read-only;
91 }; 92 };
92 partition@400000 { 93 partition@400000 {
93 label = "fs"; 94 label = "fs";
94 reg = <00400000 00300000>; 95 reg = <0x00400000 0x00300000>;
95 }; 96 };
96 partition@700000 { 97 partition@700000 {
97 label = "firmware a"; 98 label = "firmware a";
98 reg = <00700000 00100000>; 99 reg = <0x00700000 0x00100000>;
99 read-only; 100 read-only;
100 }; 101 };
101 }; 102 };
@@ -106,8 +107,8 @@
106 #size-cells = <1>; 107 #size-cells = <1>;
107 device_type = "soc"; 108 device_type = "soc";
108 compatible = "simple-bus"; 109 compatible = "simple-bus";
109 ranges = <00000000 f8000000 00100000>; 110 ranges = <0x00000000 0xf8000000 0x00100000>;
110 reg = <f8000000 00001000>; // CCSRBAR 111 reg = <0xf8000000 0x00001000>; // CCSRBAR
111 bus-frequency = <0>; 112 bus-frequency = <0>;
112 113
113 i2c@3000 { 114 i2c@3000 {
@@ -115,8 +116,8 @@
115 #size-cells = <0>; 116 #size-cells = <0>;
116 cell-index = <0>; 117 cell-index = <0>;
117 compatible = "fsl-i2c"; 118 compatible = "fsl-i2c";
118 reg = <3000 100>; 119 reg = <0x3000 0x100>;
119 interrupts = <2b 2>; 120 interrupts = <43 2>;
120 interrupt-parent = <&mpic>; 121 interrupt-parent = <&mpic>;
121 dfsrr; 122 dfsrr;
122 }; 123 };
@@ -126,8 +127,8 @@
126 #size-cells = <0>; 127 #size-cells = <0>;
127 cell-index = <1>; 128 cell-index = <1>;
128 compatible = "fsl-i2c"; 129 compatible = "fsl-i2c";
129 reg = <3100 100>; 130 reg = <0x3100 0x100>;
130 interrupts = <2b 2>; 131 interrupts = <43 2>;
131 interrupt-parent = <&mpic>; 132 interrupt-parent = <&mpic>;
132 dfsrr; 133 dfsrr;
133 }; 134 };
@@ -136,29 +137,29 @@
136 #address-cells = <1>; 137 #address-cells = <1>;
137 #size-cells = <0>; 138 #size-cells = <0>;
138 compatible = "fsl,gianfar-mdio"; 139 compatible = "fsl,gianfar-mdio";
139 reg = <24520 20>; 140 reg = <0x24520 0x20>;
140 141
141 phy0: ethernet-phy@0 { 142 phy0: ethernet-phy@0 {
142 interrupt-parent = <&mpic>; 143 interrupt-parent = <&mpic>;
143 interrupts = <a 1>; 144 interrupts = <10 1>;
144 reg = <0>; 145 reg = <0>;
145 device_type = "ethernet-phy"; 146 device_type = "ethernet-phy";
146 }; 147 };
147 phy1: ethernet-phy@1 { 148 phy1: ethernet-phy@1 {
148 interrupt-parent = <&mpic>; 149 interrupt-parent = <&mpic>;
149 interrupts = <a 1>; 150 interrupts = <10 1>;
150 reg = <1>; 151 reg = <1>;
151 device_type = "ethernet-phy"; 152 device_type = "ethernet-phy";
152 }; 153 };
153 phy2: ethernet-phy@2 { 154 phy2: ethernet-phy@2 {
154 interrupt-parent = <&mpic>; 155 interrupt-parent = <&mpic>;
155 interrupts = <a 1>; 156 interrupts = <10 1>;
156 reg = <2>; 157 reg = <2>;
157 device_type = "ethernet-phy"; 158 device_type = "ethernet-phy";
158 }; 159 };
159 phy3: ethernet-phy@3 { 160 phy3: ethernet-phy@3 {
160 interrupt-parent = <&mpic>; 161 interrupt-parent = <&mpic>;
161 interrupts = <a 1>; 162 interrupts = <10 1>;
162 reg = <3>; 163 reg = <3>;
163 device_type = "ethernet-phy"; 164 device_type = "ethernet-phy";
164 }; 165 };
@@ -169,9 +170,9 @@
169 device_type = "network"; 170 device_type = "network";
170 model = "TSEC"; 171 model = "TSEC";
171 compatible = "gianfar"; 172 compatible = "gianfar";
172 reg = <24000 1000>; 173 reg = <0x24000 0x1000>;
173 local-mac-address = [ 00 00 00 00 00 00 ]; 174 local-mac-address = [ 00 00 00 00 00 00 ];
174 interrupts = <1d 2 1e 2 22 2>; 175 interrupts = <29 2 30 2 34 2>;
175 interrupt-parent = <&mpic>; 176 interrupt-parent = <&mpic>;
176 phy-handle = <&phy0>; 177 phy-handle = <&phy0>;
177 phy-connection-type = "rgmii-id"; 178 phy-connection-type = "rgmii-id";
@@ -182,9 +183,9 @@
182 device_type = "network"; 183 device_type = "network";
183 model = "TSEC"; 184 model = "TSEC";
184 compatible = "gianfar"; 185 compatible = "gianfar";
185 reg = <25000 1000>; 186 reg = <0x25000 0x1000>;
186 local-mac-address = [ 00 00 00 00 00 00 ]; 187 local-mac-address = [ 00 00 00 00 00 00 ];
187 interrupts = <23 2 24 2 28 2>; 188 interrupts = <35 2 36 2 40 2>;
188 interrupt-parent = <&mpic>; 189 interrupt-parent = <&mpic>;
189 phy-handle = <&phy1>; 190 phy-handle = <&phy1>;
190 phy-connection-type = "rgmii-id"; 191 phy-connection-type = "rgmii-id";
@@ -195,9 +196,9 @@
195 device_type = "network"; 196 device_type = "network";
196 model = "TSEC"; 197 model = "TSEC";
197 compatible = "gianfar"; 198 compatible = "gianfar";
198 reg = <26000 1000>; 199 reg = <0x26000 0x1000>;
199 local-mac-address = [ 00 00 00 00 00 00 ]; 200 local-mac-address = [ 00 00 00 00 00 00 ];
200 interrupts = <1F 2 20 2 21 2>; 201 interrupts = <31 2 32 2 33 2>;
201 interrupt-parent = <&mpic>; 202 interrupt-parent = <&mpic>;
202 phy-handle = <&phy2>; 203 phy-handle = <&phy2>;
203 phy-connection-type = "rgmii-id"; 204 phy-connection-type = "rgmii-id";
@@ -208,9 +209,9 @@
208 device_type = "network"; 209 device_type = "network";
209 model = "TSEC"; 210 model = "TSEC";
210 compatible = "gianfar"; 211 compatible = "gianfar";
211 reg = <27000 1000>; 212 reg = <0x27000 0x1000>;
212 local-mac-address = [ 00 00 00 00 00 00 ]; 213 local-mac-address = [ 00 00 00 00 00 00 ];
213 interrupts = <25 2 26 2 27 2>; 214 interrupts = <37 2 38 2 39 2>;
214 interrupt-parent = <&mpic>; 215 interrupt-parent = <&mpic>;
215 phy-handle = <&phy3>; 216 phy-handle = <&phy3>;
216 phy-connection-type = "rgmii-id"; 217 phy-connection-type = "rgmii-id";
@@ -220,9 +221,9 @@
220 cell-index = <0>; 221 cell-index = <0>;
221 device_type = "serial"; 222 device_type = "serial";
222 compatible = "ns16550"; 223 compatible = "ns16550";
223 reg = <4500 100>; 224 reg = <0x4500 0x100>;
224 clock-frequency = <0>; 225 clock-frequency = <0>;
225 interrupts = <2a 2>; 226 interrupts = <42 2>;
226 interrupt-parent = <&mpic>; 227 interrupt-parent = <&mpic>;
227 }; 228 };
228 229
@@ -230,9 +231,9 @@
230 cell-index = <1>; 231 cell-index = <1>;
231 device_type = "serial"; 232 device_type = "serial";
232 compatible = "ns16550"; 233 compatible = "ns16550";
233 reg = <4600 100>; 234 reg = <0x4600 0x100>;
234 clock-frequency = <0>; 235 clock-frequency = <0>;
235 interrupts = <1c 2>; 236 interrupts = <28 2>;
236 interrupt-parent = <&mpic>; 237 interrupt-parent = <&mpic>;
237 }; 238 };
238 239
@@ -241,7 +242,7 @@
241 interrupt-controller; 242 interrupt-controller;
242 #address-cells = <0>; 243 #address-cells = <0>;
243 #interrupt-cells = <2>; 244 #interrupt-cells = <2>;
244 reg = <40000 40000>; 245 reg = <0x40000 0x40000>;
245 compatible = "chrp,open-pic"; 246 compatible = "chrp,open-pic";
246 device_type = "open-pic"; 247 device_type = "open-pic";
247 big-endian; 248 big-endian;
@@ -249,7 +250,7 @@
249 250
250 global-utilities@e0000 { 251 global-utilities@e0000 {
251 compatible = "fsl,mpc8641-guts"; 252 compatible = "fsl,mpc8641-guts";
252 reg = <e0000 1000>; 253 reg = <0xe0000 0x1000>;
253 fsl,has-rstcr; 254 fsl,has-rstcr;
254 }; 255 };
255 }; 256 };
@@ -261,127 +262,127 @@
261 #interrupt-cells = <1>; 262 #interrupt-cells = <1>;
262 #size-cells = <2>; 263 #size-cells = <2>;
263 #address-cells = <3>; 264 #address-cells = <3>;
264 reg = <f8008000 1000>; 265 reg = <0xf8008000 0x1000>;
265 bus-range = <0 ff>; 266 bus-range = <0x0 0xff>;
266 ranges = <02000000 0 80000000 80000000 0 20000000 267 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
267 01000000 0 00000000 e2000000 0 00100000>; 268 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
268 clock-frequency = <1fca055>; 269 clock-frequency = <33333333>;
269 interrupt-parent = <&mpic>; 270 interrupt-parent = <&mpic>;
270 interrupts = <18 2>; 271 interrupts = <24 2>;
271 interrupt-map-mask = <ff00 0 0 7>; 272 interrupt-map-mask = <0xff00 0 0 7>;
272 interrupt-map = < 273 interrupt-map = <
273 /* IDSEL 0x11 func 0 - PCI slot 1 */ 274 /* IDSEL 0x11 func 0 - PCI slot 1 */
274 8800 0 0 1 &mpic 2 1 275 0x8800 0 0 1 &mpic 2 1
275 8800 0 0 2 &mpic 3 1 276 0x8800 0 0 2 &mpic 3 1
276 8800 0 0 3 &mpic 4 1 277 0x8800 0 0 3 &mpic 4 1
277 8800 0 0 4 &mpic 1 1 278 0x8800 0 0 4 &mpic 1 1
278 279
279 /* IDSEL 0x11 func 1 - PCI slot 1 */ 280 /* IDSEL 0x11 func 1 - PCI slot 1 */
280 8900 0 0 1 &mpic 2 1 281 0x8900 0 0 1 &mpic 2 1
281 8900 0 0 2 &mpic 3 1 282 0x8900 0 0 2 &mpic 3 1
282 8900 0 0 3 &mpic 4 1 283 0x8900 0 0 3 &mpic 4 1
283 8900 0 0 4 &mpic 1 1 284 0x8900 0 0 4 &mpic 1 1
284 285
285 /* IDSEL 0x11 func 2 - PCI slot 1 */ 286 /* IDSEL 0x11 func 2 - PCI slot 1 */
286 8a00 0 0 1 &mpic 2 1 287 0x8a00 0 0 1 &mpic 2 1
287 8a00 0 0 2 &mpic 3 1 288 0x8a00 0 0 2 &mpic 3 1
288 8a00 0 0 3 &mpic 4 1 289 0x8a00 0 0 3 &mpic 4 1
289 8a00 0 0 4 &mpic 1 1 290 0x8a00 0 0 4 &mpic 1 1
290 291
291 /* IDSEL 0x11 func 3 - PCI slot 1 */ 292 /* IDSEL 0x11 func 3 - PCI slot 1 */
292 8b00 0 0 1 &mpic 2 1 293 0x8b00 0 0 1 &mpic 2 1
293 8b00 0 0 2 &mpic 3 1 294 0x8b00 0 0 2 &mpic 3 1
294 8b00 0 0 3 &mpic 4 1 295 0x8b00 0 0 3 &mpic 4 1
295 8b00 0 0 4 &mpic 1 1 296 0x8b00 0 0 4 &mpic 1 1
296 297
297 /* IDSEL 0x11 func 4 - PCI slot 1 */ 298 /* IDSEL 0x11 func 4 - PCI slot 1 */
298 8c00 0 0 1 &mpic 2 1 299 0x8c00 0 0 1 &mpic 2 1
299 8c00 0 0 2 &mpic 3 1 300 0x8c00 0 0 2 &mpic 3 1
300 8c00 0 0 3 &mpic 4 1 301 0x8c00 0 0 3 &mpic 4 1
301 8c00 0 0 4 &mpic 1 1 302 0x8c00 0 0 4 &mpic 1 1
302 303
303 /* IDSEL 0x11 func 5 - PCI slot 1 */ 304 /* IDSEL 0x11 func 5 - PCI slot 1 */
304 8d00 0 0 1 &mpic 2 1 305 0x8d00 0 0 1 &mpic 2 1
305 8d00 0 0 2 &mpic 3 1 306 0x8d00 0 0 2 &mpic 3 1
306 8d00 0 0 3 &mpic 4 1 307 0x8d00 0 0 3 &mpic 4 1
307 8d00 0 0 4 &mpic 1 1 308 0x8d00 0 0 4 &mpic 1 1
308 309
309 /* IDSEL 0x11 func 6 - PCI slot 1 */ 310 /* IDSEL 0x11 func 6 - PCI slot 1 */
310 8e00 0 0 1 &mpic 2 1 311 0x8e00 0 0 1 &mpic 2 1
311 8e00 0 0 2 &mpic 3 1 312 0x8e00 0 0 2 &mpic 3 1
312 8e00 0 0 3 &mpic 4 1 313 0x8e00 0 0 3 &mpic 4 1
313 8e00 0 0 4 &mpic 1 1 314 0x8e00 0 0 4 &mpic 1 1
314 315
315 /* IDSEL 0x11 func 7 - PCI slot 1 */ 316 /* IDSEL 0x11 func 7 - PCI slot 1 */
316 8f00 0 0 1 &mpic 2 1 317 0x8f00 0 0 1 &mpic 2 1
317 8f00 0 0 2 &mpic 3 1 318 0x8f00 0 0 2 &mpic 3 1
318 8f00 0 0 3 &mpic 4 1 319 0x8f00 0 0 3 &mpic 4 1
319 8f00 0 0 4 &mpic 1 1 320 0x8f00 0 0 4 &mpic 1 1
320 321
321 /* IDSEL 0x12 func 0 - PCI slot 2 */ 322 /* IDSEL 0x12 func 0 - PCI slot 2 */
322 9000 0 0 1 &mpic 3 1 323 0x9000 0 0 1 &mpic 3 1
323 9000 0 0 2 &mpic 4 1 324 0x9000 0 0 2 &mpic 4 1
324 9000 0 0 3 &mpic 1 1 325 0x9000 0 0 3 &mpic 1 1
325 9000 0 0 4 &mpic 2 1 326 0x9000 0 0 4 &mpic 2 1
326 327
327 /* IDSEL 0x12 func 1 - PCI slot 2 */ 328 /* IDSEL 0x12 func 1 - PCI slot 2 */
328 9100 0 0 1 &mpic 3 1 329 0x9100 0 0 1 &mpic 3 1
329 9100 0 0 2 &mpic 4 1 330 0x9100 0 0 2 &mpic 4 1
330 9100 0 0 3 &mpic 1 1 331 0x9100 0 0 3 &mpic 1 1
331 9100 0 0 4 &mpic 2 1 332 0x9100 0 0 4 &mpic 2 1
332 333
333 /* IDSEL 0x12 func 2 - PCI slot 2 */ 334 /* IDSEL 0x12 func 2 - PCI slot 2 */
334 9200 0 0 1 &mpic 3 1 335 0x9200 0 0 1 &mpic 3 1
335 9200 0 0 2 &mpic 4 1 336 0x9200 0 0 2 &mpic 4 1
336 9200 0 0 3 &mpic 1 1 337 0x9200 0 0 3 &mpic 1 1
337 9200 0 0 4 &mpic 2 1 338 0x9200 0 0 4 &mpic 2 1
338 339
339 /* IDSEL 0x12 func 3 - PCI slot 2 */ 340 /* IDSEL 0x12 func 3 - PCI slot 2 */
340 9300 0 0 1 &mpic 3 1 341 0x9300 0 0 1 &mpic 3 1
341 9300 0 0 2 &mpic 4 1 342 0x9300 0 0 2 &mpic 4 1
342 9300 0 0 3 &mpic 1 1 343 0x9300 0 0 3 &mpic 1 1
343 9300 0 0 4 &mpic 2 1 344 0x9300 0 0 4 &mpic 2 1
344 345
345 /* IDSEL 0x12 func 4 - PCI slot 2 */ 346 /* IDSEL 0x12 func 4 - PCI slot 2 */
346 9400 0 0 1 &mpic 3 1 347 0x9400 0 0 1 &mpic 3 1
347 9400 0 0 2 &mpic 4 1 348 0x9400 0 0 2 &mpic 4 1
348 9400 0 0 3 &mpic 1 1 349 0x9400 0 0 3 &mpic 1 1
349 9400 0 0 4 &mpic 2 1 350 0x9400 0 0 4 &mpic 2 1
350 351
351 /* IDSEL 0x12 func 5 - PCI slot 2 */ 352 /* IDSEL 0x12 func 5 - PCI slot 2 */
352 9500 0 0 1 &mpic 3 1 353 0x9500 0 0 1 &mpic 3 1
353 9500 0 0 2 &mpic 4 1 354 0x9500 0 0 2 &mpic 4 1
354 9500 0 0 3 &mpic 1 1 355 0x9500 0 0 3 &mpic 1 1
355 9500 0 0 4 &mpic 2 1 356 0x9500 0 0 4 &mpic 2 1
356 357
357 /* IDSEL 0x12 func 6 - PCI slot 2 */ 358 /* IDSEL 0x12 func 6 - PCI slot 2 */
358 9600 0 0 1 &mpic 3 1 359 0x9600 0 0 1 &mpic 3 1
359 9600 0 0 2 &mpic 4 1 360 0x9600 0 0 2 &mpic 4 1
360 9600 0 0 3 &mpic 1 1 361 0x9600 0 0 3 &mpic 1 1
361 9600 0 0 4 &mpic 2 1 362 0x9600 0 0 4 &mpic 2 1
362 363
363 /* IDSEL 0x12 func 7 - PCI slot 2 */ 364 /* IDSEL 0x12 func 7 - PCI slot 2 */
364 9700 0 0 1 &mpic 3 1 365 0x9700 0 0 1 &mpic 3 1
365 9700 0 0 2 &mpic 4 1 366 0x9700 0 0 2 &mpic 4 1
366 9700 0 0 3 &mpic 1 1 367 0x9700 0 0 3 &mpic 1 1
367 9700 0 0 4 &mpic 2 1 368 0x9700 0 0 4 &mpic 2 1
368 369
369 // IDSEL 0x1c USB 370 // IDSEL 0x1c USB
370 e000 0 0 1 &i8259 c 2 371 0xe000 0 0 1 &i8259 12 2
371 e100 0 0 2 &i8259 9 2 372 0xe100 0 0 2 &i8259 9 2
372 e200 0 0 3 &i8259 a 2 373 0xe200 0 0 3 &i8259 10 2
373 e300 0 0 4 &i8259 b 2 374 0xe300 0 0 4 &i8259 112
374 375
375 // IDSEL 0x1d Audio 376 // IDSEL 0x1d Audio
376 e800 0 0 1 &i8259 6 2 377 0xe800 0 0 1 &i8259 6 2
377 378
378 // IDSEL 0x1e Legacy 379 // IDSEL 0x1e Legacy
379 f000 0 0 1 &i8259 7 2 380 0xf000 0 0 1 &i8259 7 2
380 f100 0 0 1 &i8259 7 2 381 0xf100 0 0 1 &i8259 7 2
381 382
382 // IDSEL 0x1f IDE/SATA 383 // IDSEL 0x1f IDE/SATA
383 f800 0 0 1 &i8259 e 2 384 0xf800 0 0 1 &i8259 14 2
384 f900 0 0 1 &i8259 5 2 385 0xf900 0 0 1 &i8259 5 2
385 >; 386 >;
386 387
387 pcie@0 { 388 pcie@0 {
@@ -389,37 +390,37 @@
389 #size-cells = <2>; 390 #size-cells = <2>;
390 #address-cells = <3>; 391 #address-cells = <3>;
391 device_type = "pci"; 392 device_type = "pci";
392 ranges = <02000000 0 80000000 393 ranges = <0x02000000 0x0 0x80000000
393 02000000 0 80000000 394 0x02000000 0x0 0x80000000
394 0 20000000 395 0x0 0x20000000
395 396
396 01000000 0 00000000 397 0x01000000 0x0 0x00000000
397 01000000 0 00000000 398 0x01000000 0x0 0x00000000
398 0 00100000>; 399 0x0 0x00100000>;
399 uli1575@0 { 400 uli1575@0 {
400 reg = <0 0 0 0 0>; 401 reg = <0 0 0 0 0>;
401 #size-cells = <2>; 402 #size-cells = <2>;
402 #address-cells = <3>; 403 #address-cells = <3>;
403 ranges = <02000000 0 80000000 404 ranges = <0x02000000 0x0 0x80000000
404 02000000 0 80000000 405 0x02000000 0x0 0x80000000
405 0 20000000 406 0x0 0x20000000
406 01000000 0 00000000 407 0x01000000 0x0 0x00000000
407 01000000 0 00000000 408 0x01000000 0x0 0x00000000
408 0 00100000>; 409 0x0 0x00100000>;
409 isa@1e { 410 isa@1e {
410 device_type = "isa"; 411 device_type = "isa";
411 #interrupt-cells = <2>; 412 #interrupt-cells = <2>;
412 #size-cells = <1>; 413 #size-cells = <1>;
413 #address-cells = <2>; 414 #address-cells = <2>;
414 reg = <f000 0 0 0 0>; 415 reg = <0xf000 0 0 0 0>;
415 ranges = <1 0 01000000 0 0 416 ranges = <1 0 0x01000000 0 0
416 00001000>; 417 0x00001000>;
417 interrupt-parent = <&i8259>; 418 interrupt-parent = <&i8259>;
418 419
419 i8259: interrupt-controller@20 { 420 i8259: interrupt-controller@20 {
420 reg = <1 20 2 421 reg = <1 0x20 2
421 1 a0 2 422 1 0xa0 2
422 1 4d0 2>; 423 1 0x4d0 2>;
423 interrupt-controller; 424 interrupt-controller;
424 device_type = "interrupt-controller"; 425 device_type = "interrupt-controller";
425 #address-cells = <0>; 426 #address-cells = <0>;
@@ -432,8 +433,8 @@
432 i8042@60 { 433 i8042@60 {
433 #size-cells = <0>; 434 #size-cells = <0>;
434 #address-cells = <1>; 435 #address-cells = <1>;
435 reg = <1 60 1 1 64 1>; 436 reg = <1 0x60 1 1 0x64 1>;
436 interrupts = <1 3 c 3>; 437 interrupts = <1 3 12 3>;
437 interrupt-parent = 438 interrupt-parent =
438 <&i8259>; 439 <&i8259>;
439 440
@@ -451,11 +452,11 @@
451 rtc@70 { 452 rtc@70 {
452 compatible = 453 compatible =
453 "pnpPNP,b00"; 454 "pnpPNP,b00";
454 reg = <1 70 2>; 455 reg = <1 0x70 2>;
455 }; 456 };
456 457
457 gpio@400 { 458 gpio@400 {
458 reg = <1 400 80>; 459 reg = <1 0x400 0x80>;
459 }; 460 };
460 }; 461 };
461 }; 462 };
@@ -470,33 +471,33 @@
470 #interrupt-cells = <1>; 471 #interrupt-cells = <1>;
471 #size-cells = <2>; 472 #size-cells = <2>;
472 #address-cells = <3>; 473 #address-cells = <3>;
473 reg = <f8009000 1000>; 474 reg = <0xf8009000 0x1000>;
474 bus-range = <0 ff>; 475 bus-range = <0 0xff>;
475 ranges = <02000000 0 a0000000 a0000000 0 20000000 476 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
476 01000000 0 00000000 e3000000 0 00100000>; 477 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
477 clock-frequency = <1fca055>; 478 clock-frequency = <33333333>;
478 interrupt-parent = <&mpic>; 479 interrupt-parent = <&mpic>;
479 interrupts = <19 2>; 480 interrupts = <25 2>;
480 interrupt-map-mask = <f800 0 0 7>; 481 interrupt-map-mask = <0xf800 0 0 7>;
481 interrupt-map = < 482 interrupt-map = <
482 /* IDSEL 0x0 */ 483 /* IDSEL 0x0 */
483 0000 0 0 1 &mpic 4 1 484 0x0000 0 0 1 &mpic 4 1
484 0000 0 0 2 &mpic 5 1 485 0x0000 0 0 2 &mpic 5 1
485 0000 0 0 3 &mpic 6 1 486 0x0000 0 0 3 &mpic 6 1
486 0000 0 0 4 &mpic 7 1 487 0x0000 0 0 4 &mpic 7 1
487 >; 488 >;
488 pcie@0 { 489 pcie@0 {
489 reg = <0 0 0 0 0>; 490 reg = <0 0 0 0 0>;
490 #size-cells = <2>; 491 #size-cells = <2>;
491 #address-cells = <3>; 492 #address-cells = <3>;
492 device_type = "pci"; 493 device_type = "pci";
493 ranges = <02000000 0 a0000000 494 ranges = <0x02000000 0x0 0xa0000000
494 02000000 0 a0000000 495 0x02000000 0x0 0xa0000000
495 0 20000000 496 0x0 0x20000000
496 497
497 01000000 0 00000000 498 0x01000000 0x0 0x00000000
498 01000000 0 00000000 499 0x01000000 0x0 0x00000000
499 0 00100000>; 500 0x0 0x00100000>;
500 }; 501 };
501 }; 502 };
502}; 503};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 02:08:07 -0500