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authorMatt Carlson <mcarlson@broadcom.com>2010-02-12 09:47:08 -0500
committerDavid S. Miller <davem@davemloft.net>2010-02-12 20:05:53 -0500
commit6b10c1653e425e30cff7f41d0e6f9743bfa9810f (patch)
tree62fb40716bf0c80a2d808e3eee43a98e4d769dd0
parentf89f38b8ec3171664314669a1396ab70b43e8961 (diff)
tg3: Fix 57765 A0 bootcode race condition
On A0 revision of 57765 asic rev devices, the bootcode will perform some hardware operations, after the magic signature is presented, that will collide with setup operations performed by the driver. The best way to avoid the contention is to have the driver delay an additional 10 milliseconds. B0 revisions of the chip will make this workaround unnecessary. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Benjamin Li <benli@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/tg3.c7
-rw-r--r--drivers/net/tg3.h1
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index c140e1bf6e02..2c5e1b7e1088 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -6721,6 +6721,13 @@ static int tg3_poll_fw(struct tg3 *tp)
6721 tp->dev->name); 6721 tp->dev->name);
6722 } 6722 }
6723 6723
6724 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6725 /* The 57765 A0 needs a little more
6726 * time to do some important work.
6727 */
6728 mdelay(10);
6729 }
6730
6724 return 0; 6731 return 0;
6725} 6732}
6726 6733
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index cc8bf7d6823a..46db4ad46bbc 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -110,6 +110,7 @@
110#define CHIPREV_ID_57780_A0 0x57780000 110#define CHIPREV_ID_57780_A0 0x57780000
111#define CHIPREV_ID_57780_A1 0x57780001 111#define CHIPREV_ID_57780_A1 0x57780001
112#define CHIPREV_ID_5717_A0 0x05717000 112#define CHIPREV_ID_5717_A0 0x05717000
113#define CHIPREV_ID_57765_A0 0x57785000
113#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) 114#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
114#define ASIC_REV_5700 0x07 115#define ASIC_REV_5700 0x07
115#define ASIC_REV_5701 0x00 116#define ASIC_REV_5701 0x00