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authorLivio Soares <livio@eecg.toronto.edu>2007-02-06 20:51:36 -0500
committerPaul Mackerras <paulus@samba.org>2007-02-06 22:03:23 -0500
commit449d846dbcbf61bdf7d50a923e4791102168c292 (patch)
treef900c3743888a890c4862b1542eafd8f0dfb1249
parenta2c70211fa072f4076f0e59f909b69105f69072e (diff)
[POWERPC] Fix performance monitor exception
To the issue: some point during 2.6.20 development, Paul Mackerras introduced the "lazy IRQ disabling" patch (very cool work, BTW). In that patch, the performance monitor unit exception was marked as "maskable", in the sense that if interrupts were soft-disabled, that exception could be ignored. This broke my PowerPC profiling code. The symptom that I see is that a varying number of interrupts (from 0 to $n$, typically closer to 0) get delivered, when, in reality, it should always be very close to $n$. The issue stems from the way masking is being done. Masking in this fashion seems to work well with the decrementer and external interrupts, because they are raised again until "really" handled. For the PMU, however, this does not apply (at least on my Xserver machine with a 970FX processor). If the PMU exception is not handled, it will _not_ be re-raised (at least on my machine). The documentation states that the PMXE bit in MMCR0 is set to 0 when the PMU exception is raised. However, software must re-set the bit to re-enable PMU exceptions. If the exception is ignored (as currently) not only is that interrupt lost, but because software does not re-set PMXE, the PMU registers are "frozen" forever. [This patch means that performance monitor exceptions are taken and handled even if irqs are off, as long as some other interrupt hasn't come along and caused interrupts to be hard-disabled. In this sense the PMU exception becomes like an NMI. The oprofile code for most powerpc processors does nothing that is unsafe in an NMI context, but the Cell oprofile code does a spin_lock_irqsave. However, that turns out to be OK because Cell doesn't actually use the performance monitor exception; performance monitor interrupts come in as a regular interrupt on Cell, so will be disabled when irqs are off. -- paulus.] Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r--arch/powerpc/kernel/head_64.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 71b1fe58e9e4..97cedcd6c9b4 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -613,7 +613,7 @@ system_call_pSeries:
613/*** pSeries interrupt support ***/ 613/*** pSeries interrupt support ***/
614 614
615 /* moved from 0xf00 */ 615 /* moved from 0xf00 */
616 MASKABLE_EXCEPTION_PSERIES(., performance_monitor) 616 STD_EXCEPTION_PSERIES(., performance_monitor)
617 617
618/* 618/*
619 * An interrupt came in while soft-disabled; clear EE in SRR1, 619 * An interrupt came in while soft-disabled; clear EE in SRR1,