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authorYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>2007-12-25 21:45:06 -0500
committerPaul Mundt <lethal@linux-sh.org>2008-01-27 23:19:02 -0500
commit31a49c4bf8f964b7a9897baa889916d71b51d9c1 (patch)
treee6c900dfbdf51d97d4c189a712a8c4e1aa059cf4
parent52e8b118ecd17185ce514cd3f955094c1d8f4288 (diff)
sh: Add support for SH7721 CPU subtype.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/sh/Kconfig7
-rw-r--r--arch/sh/Kconfig.debug2
-rw-r--r--arch/sh/drivers/dma/Kconfig2
-rw-r--r--arch/sh/drivers/dma/dma-sh.c2
-rw-r--r--arch/sh/kernel/cpu/sh3/Makefile1
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c3
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c11
-rw-r--r--arch/sh/kernel/early_printk.c12
-rw-r--r--arch/sh/kernel/setup.c8
-rw-r--r--arch/sh/kernel/timers/timer-tmu.c1
-rw-r--r--drivers/serial/sh-sci.c2
-rw-r--r--drivers/serial/sh-sci.h21
-rw-r--r--include/asm-sh/cpu-sh3/cache.h3
-rw-r--r--include/asm-sh/cpu-sh3/dma.h4
-rw-r--r--include/asm-sh/cpu-sh3/gpio.h3
-rw-r--r--include/asm-sh/cpu-sh3/mmu_context.h3
-rw-r--r--include/asm-sh/cpu-sh3/timer.h7
-rw-r--r--include/asm-sh/cpu-sh3/ubc.h3
-rw-r--r--include/asm-sh/processor.h2
19 files changed, 68 insertions, 29 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 538631ca10a6..d2f557719489 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -214,6 +214,13 @@ config CPU_SUBTYPE_SH7720
214 help 214 help
215 Select SH7720 if you have a SH3-DSP SH7720 CPU. 215 Select SH7720 if you have a SH3-DSP SH7720 CPU.
216 216
217config CPU_SUBTYPE_SH7721
218 bool "Support SH7721 processor"
219 select CPU_SH3
220 select CPU_HAS_DSP
221 help
222 Select SH7721 if you have a SH3-DSP SH7721 CPU.
223
217# SH-4 Processor Support 224# SH-4 Processor Support
218 225
219config CPU_SUBTYPE_SH7750 226config CPU_SUBTYPE_SH7750
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index 2881d8471a17..dde00d5c2478 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -35,7 +35,7 @@ config EARLY_SCIF_CONSOLE_PORT
35 default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263 35 default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
36 default "0xf8420000" if CPU_SUBTYPE_SH7619 36 default "0xf8420000" if CPU_SUBTYPE_SH7619
37 default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705 37 default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
38 default "0xa4430000" if CPU_SUBTYPE_SH7720 38 default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
39 default "0xffc30000" if CPU_SUBTYPE_SHX3 39 default "0xffc30000" if CPU_SUBTYPE_SHX3
40 default "0xffe80000" if CPU_SH4 40 default "0xffe80000" if CPU_SH4
41 default "0x00000000" 41 default "0x00000000"
diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig
index 4e711a0c3dae..01936368b8b0 100644
--- a/arch/sh/drivers/dma/Kconfig
+++ b/arch/sh/drivers/dma/Kconfig
@@ -12,7 +12,7 @@ config SH_DMA
12config NR_ONCHIP_DMA_CHANNELS 12config NR_ONCHIP_DMA_CHANNELS
13 int 13 int
14 depends on SH_DMA 14 depends on SH_DMA
15 default "6" if CPU_SUBTYPE_SH7720 15 default "6" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
16 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R 16 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
17 default "12" if CPU_SUBTYPE_SH7780 17 default "12" if CPU_SUBTYPE_SH7780
18 default "4" 18 default "4"
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index 958bac1c585a..5c3359756a92 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -25,6 +25,7 @@ static int dmte_irq_map[] = {
25 DMTE2_IRQ, 25 DMTE2_IRQ,
26 DMTE3_IRQ, 26 DMTE3_IRQ,
27#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 27#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
28 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
28 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ 29 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
29 defined(CONFIG_CPU_SUBTYPE_SH7760) || \ 30 defined(CONFIG_CPU_SUBTYPE_SH7760) || \
30 defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
@@ -203,6 +204,7 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan)
203} 204}
204 205
205#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 206#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
207 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
206 defined(CONFIG_CPU_SUBTYPE_SH7780) 208 defined(CONFIG_CPU_SUBTYPE_SH7780)
207#define dmaor_read_reg() ctrl_inw(DMAOR) 209#define dmaor_read_reg() ctrl_inw(DMAOR)
208#define dmaor_write_reg(data) ctrl_outw(data, DMAOR) 210#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
index 646eb6933614..1afd05e62d1c 100644
--- a/arch/sh/kernel/cpu/sh3/Makefile
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh770x.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o 14obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o
15obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7721) += setup-sh7720.o
16 17
17# Primary on-chip clocks (common) 18# Primary on-chip clocks (common)
18clock-$(CONFIG_CPU_SH3) := clock-sh3.o 19clock-$(CONFIG_CPU_SH3) := clock-sh3.o
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index 22070e43e34d..fcc80bb7bee7 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -84,6 +84,9 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
84#if defined(CONFIG_CPU_SUBTYPE_SH7720) 84#if defined(CONFIG_CPU_SUBTYPE_SH7720)
85 boot_cpu_data.type = CPU_SH7720; 85 boot_cpu_data.type = CPU_SH7720;
86#endif 86#endif
87#if defined(CONFIG_CPU_SUBTYPE_SH7721)
88 boot_cpu_data.type = CPU_SH7721;
89#endif
87#if defined(CONFIG_CPU_SUBTYPE_SH7705) 90#if defined(CONFIG_CPU_SUBTYPE_SH7705)
88 boot_cpu_data.type = CPU_SH7705; 91 boot_cpu_data.type = CPU_SH7705;
89 92
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index a0929b8a95ae..00facd028a08 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -127,8 +127,11 @@ static struct intc_vect vectors[] __initdata = {
127 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800), 127 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800),
128 INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840), 128 INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840),
129 INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900), 129 INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900),
130 INTC_VECT(SSL, 0x980), INTC_VECT(USBFI0, 0xa20), 130#if defined(CONFIG_CPU_SUBTYPE_SH7720)
131 INTC_VECT(USBFI1, 0xa40), INTC_VECT(USBHI, 0xa60), 131 INTC_VECT(SSL, 0x980),
132#endif
133 INTC_VECT(USBFI0, 0xa20), INTC_VECT(USBFI1, 0xa40),
134 INTC_VECT(USBHI, 0xa60),
132 INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0), 135 INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0),
133 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), 136 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00),
134 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), 137 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80),
@@ -168,7 +171,11 @@ static struct intc_prio_reg prio_registers[] __initdata = {
168 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, 171 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
169 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, 172 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
170 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, 173 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
174#if defined(CONFIG_CPU_SUBTYPE_SH7720)
171 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, 175 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
176#else
177 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, 0 } },
178#endif
172 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, 179 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
173 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, 180 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
174 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, 181 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c
index 2f30977558ad..957f25611543 100644
--- a/arch/sh/kernel/early_printk.c
+++ b/arch/sh/kernel/early_printk.c
@@ -63,7 +63,8 @@ static struct console bios_console = {
63#include <linux/serial_core.h> 63#include <linux/serial_core.h>
64#include "../../../drivers/serial/sh-sci.h" 64#include "../../../drivers/serial/sh-sci.h"
65 65
66#if defined(CONFIG_CPU_SUBTYPE_SH7720) 66#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
67 defined(CONFIG_CPU_SUBTYPE_SH7721)
67#define EPK_SCSMR_VALUE 0x000 68#define EPK_SCSMR_VALUE 0x000
68#define EPK_SCBRR_VALUE 0x00C 69#define EPK_SCBRR_VALUE 0x00C
69#define EPK_FIFO_SIZE 64 70#define EPK_FIFO_SIZE 64
@@ -117,7 +118,8 @@ static struct console scif_console = {
117}; 118};
118 119
119#if !defined(CONFIG_SH_STANDARD_BIOS) 120#if !defined(CONFIG_SH_STANDARD_BIOS)
120#if defined(CONFIG_CPU_SUBTYPE_SH7720) 121#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
122 defined(CONFIG_CPU_SUBTYPE_SH7721)
121static void scif_sercon_init(char *s) 123static void scif_sercon_init(char *s)
122{ 124{
123 sci_out(&scif_port, SCSCR, 0x0000); /* clear TE and RE */ 125 sci_out(&scif_port, SCSCR, 0x0000); /* clear TE and RE */
@@ -208,10 +210,12 @@ static int __init setup_early_printk(char *buf)
208 if (!strncmp(buf, "serial", 6)) { 210 if (!strncmp(buf, "serial", 6)) {
209 early_console = &scif_console; 211 early_console = &scif_console;
210 212
211#if (defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720)) && \ 213#if !defined(CONFIG_SH_STANDARD_BIOS)
212 !defined(CONFIG_SH_STANDARD_BIOS) 214#if defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720) || \
215 defined(CONFIG_CPU_SUBTYPE_SH7721)
213 scif_sercon_init(buf + 6); 216 scif_sercon_init(buf + 6);
214#endif 217#endif
218#endif
215 } 219 }
216#endif 220#endif
217 221
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 9c105c827e86..48cd576754b5 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -314,10 +314,10 @@ static const char *cpu_name[] = {
314 [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708", 314 [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
315 [CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710", 315 [CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
316 [CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720", 316 [CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720",
317 [CPU_SH7729] = "SH7729", [CPU_SH7750] = "SH7750", 317 [CPU_SH7721] = "SH7721", [CPU_SH7729] = "SH7729",
318 [CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R", 318 [CPU_SH7750] = "SH7750", [CPU_SH7750S] = "SH7750S",
319 [CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R", 319 [CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751",
320 [CPU_SH7760] = "SH7760", 320 [CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760",
321 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501", 321 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
322 [CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780", 322 [CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
323 [CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343", 323 [CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",
diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c
index 628ec9a15e38..8935570008d2 100644
--- a/arch/sh/kernel/timers/timer-tmu.c
+++ b/arch/sh/kernel/timers/timer-tmu.c
@@ -174,6 +174,7 @@ static int tmu_timer_init(void)
174 tmu_timer_stop(); 174 tmu_timer_stop();
175 175
176#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ 176#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
177 !defined(CONFIG_CPU_SUBTYPE_SH7721) && \
177 !defined(CONFIG_CPU_SUBTYPE_SH7760) && \ 178 !defined(CONFIG_CPU_SUBTYPE_SH7760) && \
178 !defined(CONFIG_CPU_SUBTYPE_SH7785) && \ 179 !defined(CONFIG_CPU_SUBTYPE_SH7785) && \
179 !defined(CONFIG_CPU_SUBTYPE_SHX3) 180 !defined(CONFIG_CPU_SUBTYPE_SHX3)
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 73440e26834b..6fbfd140b7e7 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -302,7 +302,7 @@ static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
302 } 302 }
303 sci_out(port, SCFCR, fcr_val); 303 sci_out(port, SCFCR, fcr_val);
304} 304}
305#elif defined(CONFIG_CPU_SUBTYPE_SH7720) 305#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
306static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 306static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
307{ 307{
308 unsigned int fcr_val = 0; 308 unsigned int fcr_val = 0;
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 0187dccfe8c1..85562040a6d3 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -46,7 +46,8 @@
46 */ 46 */
47# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 47# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
48# define SCIF_ONLY 48# define SCIF_ONLY
49#elif defined(CONFIG_CPU_SUBTYPE_SH7720) 49#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
50 defined(CONFIG_CPU_SUBTYPE_SH7721)
50# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 51# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
51# define SCIF_ONLY 52# define SCIF_ONLY
52#define SCIF_ORER 0x0200 /* overrun error bit */ 53#define SCIF_ORER 0x0200 /* overrun error bit */
@@ -216,7 +217,8 @@
216#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 217#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217 218
218#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 219#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
219 defined(CONFIG_CPU_SUBTYPE_SH7720) 220 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
221 defined(CONFIG_CPU_SUBTYPE_SH7721)
220#define SCIF_ORER 0x0200 222#define SCIF_ORER 0x0200
221#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 223#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
222#define SCIF_RFDC_MASK 0x007f 224#define SCIF_RFDC_MASK 0x007f
@@ -254,7 +256,8 @@
254# define SCxSR_PER(port) SCIF_PER 256# define SCxSR_PER(port) SCIF_PER
255# define SCxSR_BRK(port) SCIF_BRK 257# define SCxSR_BRK(port) SCIF_BRK
256#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 258#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
257 defined(CONFIG_CPU_SUBTYPE_SH7720) 259 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
260 defined(CONFIG_CPU_SUBTYPE_SH7721)
258# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) 261# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
259# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) 262# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
260# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) 263# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
@@ -363,7 +366,8 @@
363#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 366#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
364 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 367 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
365#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 368#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
366 defined(CONFIG_CPU_SUBTYPE_SH7720) 369 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
370 defined(CONFIG_CPU_SUBTYPE_SH7721)
367#define SCIF_FNS(name, scif_offset, scif_size) \ 371#define SCIF_FNS(name, scif_offset, scif_size) \
368 CPU_SCIF_FNS(name, scif_offset, scif_size) 372 CPU_SCIF_FNS(name, scif_offset, scif_size)
369#else 373#else
@@ -390,7 +394,8 @@
390#endif 394#endif
391 395
392#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 396#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
393 defined(CONFIG_CPU_SUBTYPE_SH7720) 397 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
398 defined(CONFIG_CPU_SUBTYPE_SH7721)
394 399
395SCIF_FNS(SCSMR, 0x00, 16) 400SCIF_FNS(SCSMR, 0x00, 16)
396SCIF_FNS(SCBRR, 0x04, 8) 401SCIF_FNS(SCBRR, 0x04, 8)
@@ -512,7 +517,8 @@ static inline void set_sh771x_scif_pfc(struct uart_port *port)
512 return; 517 return;
513 } 518 }
514} 519}
515#elif defined(CONFIG_CPU_SUBTYPE_SH7720) 520#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
521 defined(CONFIG_CPU_SUBTYPE_SH7721)
516static inline int sci_rxd_in(struct uart_port *port) 522static inline int sci_rxd_in(struct uart_port *port)
517{ 523{
518 if (port->mapbase == 0xa4430000) 524 if (port->mapbase == 0xa4430000)
@@ -696,7 +702,8 @@ static inline int sci_rxd_in(struct uart_port *port)
696 defined(CONFIG_CPU_SUBTYPE_SH7785) 702 defined(CONFIG_CPU_SUBTYPE_SH7785)
697#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 703#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
698#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 704#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
699 defined(CONFIG_CPU_SUBTYPE_SH7720) 705 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
706 defined(CONFIG_CPU_SUBTYPE_SH7721)
700#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 707#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
701#elif defined(__H8300H__) || defined(__H8300S__) 708#elif defined(__H8300H__) || defined(__H8300S__)
702#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1) 709#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
index 77dd45d82414..56bd838b7db4 100644
--- a/include/asm-sh/cpu-sh3/cache.h
+++ b/include/asm-sh/cpu-sh3/cache.h
@@ -33,7 +33,8 @@
33 33
34#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 34#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 35 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
36 defined(CONFIG_CPU_SUBTYPE_SH7720) 36 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
37 defined(CONFIG_CPU_SUBTYPE_SH7721)
37#define CCR3 0xa40000b4 38#define CCR3 0xa40000b4
38#define CCR_CACHE_16KB 0x00010000 39#define CCR_CACHE_16KB 0x00010000
39#define CCR_CACHE_32KB 0x00020000 40#define CCR_CACHE_32KB 0x00020000
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
index 54bfece328c2..092ff9d872c3 100644
--- a/include/asm-sh/cpu-sh3/dma.h
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -2,7 +2,9 @@
2#define __ASM_CPU_SH3_DMA_H 2#define __ASM_CPU_SH3_DMA_H
3 3
4 4
5#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709) 5#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
7 defined(CONFIG_CPU_SUBTYPE_SH7709)
6#define SH_DMAC_BASE 0xa4010020 8#define SH_DMAC_BASE 0xa4010020
7 9
8#define DMTE0_IRQ 48 10#define DMTE0_IRQ 48
diff --git a/include/asm-sh/cpu-sh3/gpio.h b/include/asm-sh/cpu-sh3/gpio.h
index 48770c1c7bdf..4e53eb314b8f 100644
--- a/include/asm-sh/cpu-sh3/gpio.h
+++ b/include/asm-sh/cpu-sh3/gpio.h
@@ -12,7 +12,8 @@
12#ifndef _CPU_SH3_GPIO_H 12#ifndef _CPU_SH3_GPIO_H
13#define _CPU_SH3_GPIO_H 13#define _CPU_SH3_GPIO_H
14 14
15#if defined(CONFIG_CPU_SUBTYPE_SH7720) 15#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
16 defined(CONFIG_CPU_SUBTYPE_SH7721)
16 17
17/* Control registers */ 18/* Control registers */
18#define PORT_PACR 0xA4050100UL 19#define PORT_PACR 0xA4050100UL
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
index 16c2d63b7e39..ab09da73ce77 100644
--- a/include/asm-sh/cpu-sh3/mmu_context.h
+++ b/include/asm-sh/cpu-sh3/mmu_context.h
@@ -33,7 +33,8 @@
33 defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 33 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
34 defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 34 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7712) || \ 35 defined(CONFIG_CPU_SUBTYPE_SH7712) || \
36 defined(CONFIG_CPU_SUBTYPE_SH7720) 36 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
37 defined(CONFIG_CPU_SUBTYPE_SH7721)
37#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ 38#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
38#else 39#else
39#define INTEVT 0xffffffd8 40#define INTEVT 0xffffffd8
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
index 7b795ac5477c..793acf12aa08 100644
--- a/include/asm-sh/cpu-sh3/timer.h
+++ b/include/asm-sh/cpu-sh3/timer.h
@@ -23,12 +23,13 @@
23 * --------------------------------------------------------------------------- 23 * ---------------------------------------------------------------------------
24 */ 24 */
25 25
26#if !defined(CONFIG_CPU_SUBTYPE_SH7720) 26#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
27#define TMU_TOCR 0xfffffe90 /* Byte access */ 27#define TMU_TOCR 0xfffffe90 /* Byte access */
28#endif 28#endif
29 29
30#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 30#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7720) 31 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7721)
32#define TMU_012_TSTR 0xa412fe92 /* Byte access */ 33#define TMU_012_TSTR 0xa412fe92 /* Byte access */
33 34
34#define TMU0_TCOR 0xa412fe94 /* Long access */ 35#define TMU0_TCOR 0xa412fe94 /* Long access */
@@ -57,7 +58,7 @@
57#define TMU2_TCOR 0xfffffeac /* Long access */ 58#define TMU2_TCOR 0xfffffeac /* Long access */
58#define TMU2_TCNT 0xfffffeb0 /* Long access */ 59#define TMU2_TCNT 0xfffffeb0 /* Long access */
59#define TMU2_TCR 0xfffffeb4 /* Word access */ 60#define TMU2_TCR 0xfffffeb4 /* Word access */
60#if !defined(CONFIG_CPU_SUBTYPE_SH7720) 61#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
61#define TMU2_TCPR2 0xfffffeb8 /* Long access */ 62#define TMU2_TCPR2 0xfffffeb8 /* Long access */
62#endif 63#endif
63#endif 64#endif
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
index 18467c574534..4e6381d5ff7a 100644
--- a/include/asm-sh/cpu-sh3/ubc.h
+++ b/include/asm-sh/cpu-sh3/ubc.h
@@ -12,7 +12,8 @@
12#define __ASM_CPU_SH3_UBC_H 12#define __ASM_CPU_SH3_UBC_H
13 13
14#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 14#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7720) 15 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
16 defined(CONFIG_CPU_SUBTYPE_SH7721)
16#define UBC_BARA 0xa4ffffb0 17#define UBC_BARA 0xa4ffffb0
17#define UBC_BAMRA 0xa4ffffb4 18#define UBC_BAMRA 0xa4ffffb4
18#define UBC_BBRA 0xa4ffffb8 19#define UBC_BBRA 0xa4ffffb8
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index bbbdaab8de5f..f4a8da71ba45 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -23,7 +23,7 @@ enum cpu_type {
23 CPU_SH7705, CPU_SH7706, CPU_SH7707, 23 CPU_SH7705, CPU_SH7706, CPU_SH7707,
24 CPU_SH7708, CPU_SH7708S, CPU_SH7708R, 24 CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
25 CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, 25 CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
26 CPU_SH7720, CPU_SH7729, 26 CPU_SH7720, CPU_SH7721, CPU_SH7729,
27 27
28 /* SH-4 types */ 28 /* SH-4 types */
29 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, 29 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,