x86: merge smp_store_cpu_info

now that it is the same between arches, put it into smpboot.c

Signed-off-by: Glauber Costa <gcosta@redhat.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

5 files changed, 80 insertions, 87 deletions

diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index b13b9d55f9ce..a157a5245923 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -45,6 +45,83 @@ unsigned char *trampoline_base = __va(SMP_TRAMPOLINE_BASE);
 /* representing cpus for which sibling maps can be computed */
 static cpumask_t cpu_sibling_setup_map;
 
+#ifdef CONFIG_X86_32
+/* Set if we find a B stepping CPU */
+int __cpuinitdata smp_b_stepping;
+#endif
+
+static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_X86_32
+        /*
+         * Mask B, Pentium, but not Pentium MMX
+         */
+        if (c->x86_vendor == X86_VENDOR_INTEL &&
+            c->x86 == 5 &&
+            c->x86_mask >= 1 && c->x86_mask <= 4 &&
+            c->x86_model <= 3)
+                /*
+                 * Remember we have B step Pentia with bugs
+                 */
+                smp_b_stepping = 1;
+
+        /*
+         * Certain Athlons might work (for various values of 'work') in SMP
+         * but they are not certified as MP capable.
+         */
+        if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
+
+                if (num_possible_cpus() == 1)
+                        goto valid_k7;
+
+                /* Athlon 660/661 is valid. */
+                if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
+                    (c->x86_mask == 1)))
+                        goto valid_k7;
+
+                /* Duron 670 is valid */
+                if ((c->x86_model == 7) && (c->x86_mask == 0))
+                        goto valid_k7;
+
+                /*
+                 * Athlon 662, Duron 671, and Athlon >model 7 have capability
+                 * bit. It's worth noting that the A5 stepping (662) of some
+                 * Athlon XP's have the MP bit set.
+                 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
+                 * more.
+                 */
+                if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
+                    ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
+                     (c->x86_model > 7))
+                        if (cpu_has_mp)
+                                goto valid_k7;
+
+                /* If we get here, not a certified SMP capable AMD system. */
+                add_taint(TAINT_UNSAFE_SMP);
+        }
+
+valid_k7:
+        ;
+#endif
+}
+
+/*
+ * The bootstrap kernel entry code has set these up. Save them for
+ * a given CPU
+ */
+
+void __cpuinit smp_store_cpu_info(int id)
+{
+        struct cpuinfo_x86 *c = &cpu_data(id);
+
+        *c = boot_cpu_data;
+        c->cpu_index = id;
+        if (id != 0)
+                identify_secondary_cpu(c);
+        smp_apply_quirks(c);
+}
+
+
 void __cpuinit set_cpu_sibling_map(int cpu)
 {
         int i;
diff --git a/arch/x86/kernel/smpboot_32.c b/arch/x86/kernel/smpboot_32.c
index e05006416d8c..0bfb31e13540 100644
--- a/arch/x86/kernel/smpboot_32.c
+++ b/arch/x86/kernel/smpboot_32.c
@@ -59,8 +59,7 @@
 #include <asm/vmi.h>
 #include <asm/mtrr.h>
 
-/* Set if we find a B stepping CPU */
-static int __cpuinitdata smp_b_stepping;
+extern int smp_b_stepping;
 
 static cpumask_t smp_commenced_mask;
 
@@ -78,74 +77,6 @@ static void map_cpu_to_logical_apicid(void);
 /* State of each CPU. */
 DEFINE_PER_CPU(int, cpu_state) = { 0 };
 
-static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
-{
-        /*
-         * Mask B, Pentium, but not Pentium MMX
-         */
-        if (c->x86_vendor == X86_VENDOR_INTEL &&
-            c->x86 == 5 &&
-            c->x86_mask >= 1 && c->x86_mask <= 4 &&
-            c->x86_model <= 3)
-                /*
-                 * Remember we have B step Pentia with bugs
-                 */
-                smp_b_stepping = 1;
-
-        /*
-         * Certain Athlons might work (for various values of 'work') in SMP
-         * but they are not certified as MP capable.
-         */
-        if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
-
-                if (num_possible_cpus() == 1)
-                        goto valid_k7;
-
-                /* Athlon 660/661 is valid. */  
-                if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
-                        goto valid_k7;
-
-                /* Duron 670 is valid */
-                if ((c->x86_model==7) && (c->x86_mask==0))
-                        goto valid_k7;
-
-                /*
-                 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
-                 * It's worth noting that the A5 stepping (662) of some Athlon XP's
-                 * have the MP bit set.
-                 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
-                 */
-                if (((c->x86_model==6) && (c->x86_mask>=2)) ||
-                    ((c->x86_model==7) && (c->x86_mask>=1)) ||
-                     (c->x86_model> 7))
-                        if (cpu_has_mp)
-                                goto valid_k7;
-
-                /* If we get here, it's not a certified SMP capable AMD system. */
-                add_taint(TAINT_UNSAFE_SMP);
-        }
-
-valid_k7:
-        ;
-
-}
-
-/*
- * The bootstrap kernel entry code has set these up. Save them for
- * a given CPU
- */
-
-void __cpuinit smp_store_cpu_info(int id)
-{
-        struct cpuinfo_x86 *c = &cpu_data(id);
-
-        *c = boot_cpu_data;
-        c->cpu_index = id;
-        if (id != 0)
-                identify_secondary_cpu(c);
-        smp_apply_quirks(c);
-}
-
 static atomic_t init_deasserted;
 
 static void __cpuinit smp_callin(void)
diff --git a/arch/x86/kernel/smpboot_64.c b/arch/x86/kernel/smpboot_64.c
index f84e30da521a..c213345ca2f5 100644
--- a/arch/x86/kernel/smpboot_64.c
+++ b/arch/x86/kernel/smpboot_64.c
@@ -85,21 +85,6 @@ struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
 #define set_idle_for_cpu(x,p)   (idle_thread_array[(x)] = (p))
 #endif
 
-/*
- * The bootstrap kernel entry code has set these up. Save them for
- * a given CPU
- */
-
-static void __cpuinit smp_store_cpu_info(int id)
-{
-        struct cpuinfo_x86 *c = &cpu_data(id);
-
-        *c = boot_cpu_data;
-        c->cpu_index = id;
-        if (id != 0)
-                identify_secondary_cpu(c);
-}
-
 static inline void wait_for_init_deassert(atomic_t *deassert)
 {
         while (!atomic_read(deassert))
diff --git a/include/asm-x86/smp.h b/include/asm-x86/smp.h
index 4dc271b43767..b4c5143d7f8d 100644
--- a/include/asm-x86/smp.h
+++ b/include/asm-x86/smp.h
@@ -88,6 +88,8 @@ extern void prefill_possible_map(void);
 
 #define SMP_TRAMPOLINE_BASE 0x6000
 extern unsigned long setup_trampoline(void);
+
+void smp_store_cpu_info(int id);
 #endif
 
 #ifdef CONFIG_X86_32
diff --git a/include/asm-x86/smp_32.h b/include/asm-x86/smp_32.h
index 76740def6092..51624abda43a 100644
--- a/include/asm-x86/smp_32.h
+++ b/include/asm-x86/smp_32.h
@@ -42,8 +42,6 @@ DECLARE_PER_CPU(int, cpu_number);
 
 extern int safe_smp_processor_id(void);
 
-void __cpuinit smp_store_cpu_info(int id);
-
 /* We don't mark CPUs online until __cpu_up(), so we need another measure */
 static inline int num_booting_cpus(void)
 {