diff options
author | Roland Scheidegger <rscheidegger_lists@hispeed.ch> | 2006-08-30 18:17:55 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-08-30 19:06:14 -0400 |
commit | 18f2905fcec3e06deafd25a02e37eabaaaaef744 (patch) | |
tree | 4d5b14ddd63782e46056892a8b3c644f03a38842 | |
parent | a7dec1e0dbb9e8e032b56a62d07ab6ac009109d3 (diff) |
[PATCH] drm: radeon flush TCL VAP for vertex program enable/disable
The radeon requires a VAP state flush when enabling/disabling
vertex programs on the r200 cards.
Signed-off-by: Dave Airlie <airlied@linux.ie>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r-- | drivers/char/drm/radeon_state.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index 5bb2234a9094..39a7f685e3fd 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c | |||
@@ -175,6 +175,14 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * | |||
175 | } | 175 | } |
176 | break; | 176 | break; |
177 | 177 | ||
178 | case R200_EMIT_VAP_CTL:{ | ||
179 | RING_LOCALS; | ||
180 | BEGIN_RING(2); | ||
181 | OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); | ||
182 | ADVANCE_RING(); | ||
183 | } | ||
184 | break; | ||
185 | |||
178 | case RADEON_EMIT_RB3D_COLORPITCH: | 186 | case RADEON_EMIT_RB3D_COLORPITCH: |
179 | case RADEON_EMIT_RE_LINE_PATTERN: | 187 | case RADEON_EMIT_RE_LINE_PATTERN: |
180 | case RADEON_EMIT_SE_LINE_WIDTH: | 188 | case RADEON_EMIT_SE_LINE_WIDTH: |
@@ -202,7 +210,6 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * | |||
202 | case R200_EMIT_TCL_LIGHT_MODEL_CTL_0: | 210 | case R200_EMIT_TCL_LIGHT_MODEL_CTL_0: |
203 | case R200_EMIT_TFACTOR_0: | 211 | case R200_EMIT_TFACTOR_0: |
204 | case R200_EMIT_VTX_FMT_0: | 212 | case R200_EMIT_VTX_FMT_0: |
205 | case R200_EMIT_VAP_CTL: | ||
206 | case R200_EMIT_MATRIX_SELECT_0: | 213 | case R200_EMIT_MATRIX_SELECT_0: |
207 | case R200_EMIT_TEX_PROC_CTL_2: | 214 | case R200_EMIT_TEX_PROC_CTL_2: |
208 | case R200_EMIT_TCL_UCP_VERT_BLEND_CTL: | 215 | case R200_EMIT_TCL_UCP_VERT_BLEND_CTL: |