diff options
author | Al Viro <viro@ftp.linux.org.uk> | 2008-04-28 01:59:35 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-04-28 13:03:31 -0400 |
commit | d28aa3ac4cdc2d03a2bde4b78780064a00f7ef61 (patch) | |
tree | d67fe7b143b8e2caacba166e45a5cf8b418949e2 | |
parent | ac2f217baf0f24965e40bce9a5d1a780a06596d1 (diff) |
q40ide breakage
again, fallout from ide merge
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-rw-r--r-- | drivers/ide/legacy/q40ide.c | 47 |
1 files changed, 14 insertions, 33 deletions
diff --git a/drivers/ide/legacy/q40ide.c b/drivers/ide/legacy/q40ide.c index a3573d40b4b7..f9210458aea0 100644 --- a/drivers/ide/legacy/q40ide.c +++ b/drivers/ide/legacy/q40ide.c | |||
@@ -36,23 +36,6 @@ static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = { | |||
36 | PCIDE_BASE6 */ | 36 | PCIDE_BASE6 */ |
37 | }; | 37 | }; |
38 | 38 | ||
39 | |||
40 | /* | ||
41 | * Offsets from one of the above bases | ||
42 | */ | ||
43 | |||
44 | /* used to do addr translation here but it is easier to do in setup ports */ | ||
45 | /*#define IDE_OFF_B(x) ((unsigned long)Q40_ISA_IO_B((IDE_##x##_OFFSET)))*/ | ||
46 | |||
47 | #define IDE_OFF_B(x) ((unsigned long)((IDE_##x##_OFFSET))) | ||
48 | #define IDE_OFF_W(x) ((unsigned long)((IDE_##x##_OFFSET))) | ||
49 | |||
50 | static const int pcide_offsets[IDE_NR_PORTS] = { | ||
51 | IDE_OFF_W(DATA), IDE_OFF_B(ERROR), IDE_OFF_B(NSECTOR), IDE_OFF_B(SECTOR), | ||
52 | IDE_OFF_B(LCYL), IDE_OFF_B(HCYL), 6 /*IDE_OFF_B(CURRENT)*/, IDE_OFF_B(STATUS), | ||
53 | 518/*IDE_OFF(CMD)*/ | ||
54 | }; | ||
55 | |||
56 | static int q40ide_default_irq(unsigned long base) | 39 | static int q40ide_default_irq(unsigned long base) |
57 | { | 40 | { |
58 | switch (base) { | 41 | switch (base) { |
@@ -68,23 +51,22 @@ static int q40ide_default_irq(unsigned long base) | |||
68 | /* | 51 | /* |
69 | * Addresses are pretranslated for Q40 ISA access. | 52 | * Addresses are pretranslated for Q40 ISA access. |
70 | */ | 53 | */ |
71 | void q40_ide_setup_ports ( hw_regs_t *hw, | 54 | static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base, |
72 | unsigned long base, int *offsets, | ||
73 | unsigned long ctrl, unsigned long intr, | ||
74 | ide_ack_intr_t *ack_intr, | 55 | ide_ack_intr_t *ack_intr, |
75 | int irq) | 56 | int irq) |
76 | { | 57 | { |
77 | int i; | ||
78 | |||
79 | memset(hw, 0, sizeof(hw_regs_t)); | 58 | memset(hw, 0, sizeof(hw_regs_t)); |
80 | for (i = 0; i < IDE_NR_PORTS; i++) { | 59 | /* BIG FAT WARNING: |
81 | /* BIG FAT WARNING: | 60 | assumption: only DATA port is ever used in 16 bit mode */ |
82 | assumption: only DATA port is ever used in 16 bit mode */ | 61 | hw->io_ports.data_addr = Q40_ISA_IO_W(base); |
83 | if (i == 0) | 62 | hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1); |
84 | hw->io_ports_array[i] = Q40_ISA_IO_W(base + offsets[i]); | 63 | hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2); |
85 | else | 64 | hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3); |
86 | hw->io_ports_array[i] = Q40_ISA_IO_B(base + offsets[i]); | 65 | hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4); |
87 | } | 66 | hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5); |
67 | hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6); | ||
68 | hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7); | ||
69 | hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206); | ||
88 | 70 | ||
89 | hw->irq = irq; | 71 | hw->irq = irq; |
90 | hw->ack_intr = ack_intr; | 72 | hw->ack_intr = ack_intr; |
@@ -131,9 +113,8 @@ static int __init q40ide_init(void) | |||
131 | release_region(pcide_bases[i], 8); | 113 | release_region(pcide_bases[i], 8); |
132 | continue; | 114 | continue; |
133 | } | 115 | } |
134 | q40_ide_setup_ports(&hw,(unsigned long) pcide_bases[i], (int *)pcide_offsets, | 116 | q40_ide_setup_ports(&hw, pcide_bases[i], |
135 | pcide_bases[i]+0x206, | 117 | NULL, |
136 | 0, NULL, | ||
137 | // m68kide_iops, | 118 | // m68kide_iops, |
138 | q40ide_default_irq(pcide_bases[i])); | 119 | q40ide_default_irq(pcide_bases[i])); |
139 | 120 | ||