diff options
author | Florian Fainelli <florian@openwrt.org> | 2010-09-08 07:15:13 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-09-10 00:36:38 -0400 |
commit | d0e7cb5d401695809ba8c980124ab1d8c66efc8b (patch) | |
tree | ec2598de266cf3d9aa485d9f2f5e9b2b46e8bc4b | |
parent | 49a42c080fbba9e99b4339763dd7771569ee38c3 (diff) |
au1000-eth: remove volatiles, switch to I/O accessors
Remove all the volatile keywords where they were used, switch to using the
proper readl/writel accessors.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/au1000_eth.c | 107 | ||||
-rw-r--r-- | drivers/net/au1000_eth.h | 10 |
2 files changed, 65 insertions, 52 deletions
diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c index 4bbc537a7870..f4c394fa2d93 100644 --- a/drivers/net/au1000_eth.c +++ b/drivers/net/au1000_eth.c | |||
@@ -155,10 +155,10 @@ static void au1000_enable_mac(struct net_device *dev, int force_reset) | |||
155 | spin_lock_irqsave(&aup->lock, flags); | 155 | spin_lock_irqsave(&aup->lock, flags); |
156 | 156 | ||
157 | if (force_reset || (!aup->mac_enabled)) { | 157 | if (force_reset || (!aup->mac_enabled)) { |
158 | *aup->enable = MAC_EN_CLOCK_ENABLE; | 158 | writel(MAC_EN_CLOCK_ENABLE, &aup->enable); |
159 | au_sync_delay(2); | 159 | au_sync_delay(2); |
160 | *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 | 160 | writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
161 | | MAC_EN_CLOCK_ENABLE); | 161 | | MAC_EN_CLOCK_ENABLE), &aup->enable); |
162 | au_sync_delay(2); | 162 | au_sync_delay(2); |
163 | 163 | ||
164 | aup->mac_enabled = 1; | 164 | aup->mac_enabled = 1; |
@@ -173,12 +173,12 @@ static void au1000_enable_mac(struct net_device *dev, int force_reset) | |||
173 | static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) | 173 | static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) |
174 | { | 174 | { |
175 | struct au1000_private *aup = netdev_priv(dev); | 175 | struct au1000_private *aup = netdev_priv(dev); |
176 | volatile u32 *const mii_control_reg = &aup->mac->mii_control; | 176 | u32 *const mii_control_reg = &aup->mac->mii_control; |
177 | volatile u32 *const mii_data_reg = &aup->mac->mii_data; | 177 | u32 *const mii_data_reg = &aup->mac->mii_data; |
178 | u32 timedout = 20; | 178 | u32 timedout = 20; |
179 | u32 mii_control; | 179 | u32 mii_control; |
180 | 180 | ||
181 | while (*mii_control_reg & MAC_MII_BUSY) { | 181 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
182 | mdelay(1); | 182 | mdelay(1); |
183 | if (--timedout == 0) { | 183 | if (--timedout == 0) { |
184 | netdev_err(dev, "read_MII busy timeout!!\n"); | 184 | netdev_err(dev, "read_MII busy timeout!!\n"); |
@@ -189,29 +189,29 @@ static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) | |||
189 | mii_control = MAC_SET_MII_SELECT_REG(reg) | | 189 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
190 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; | 190 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; |
191 | 191 | ||
192 | *mii_control_reg = mii_control; | 192 | writel(mii_control, mii_control_reg); |
193 | 193 | ||
194 | timedout = 20; | 194 | timedout = 20; |
195 | while (*mii_control_reg & MAC_MII_BUSY) { | 195 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
196 | mdelay(1); | 196 | mdelay(1); |
197 | if (--timedout == 0) { | 197 | if (--timedout == 0) { |
198 | netdev_err(dev, "mdio_read busy timeout!!\n"); | 198 | netdev_err(dev, "mdio_read busy timeout!!\n"); |
199 | return -1; | 199 | return -1; |
200 | } | 200 | } |
201 | } | 201 | } |
202 | return (int)*mii_data_reg; | 202 | return readl(mii_data_reg); |
203 | } | 203 | } |
204 | 204 | ||
205 | static void au1000_mdio_write(struct net_device *dev, int phy_addr, | 205 | static void au1000_mdio_write(struct net_device *dev, int phy_addr, |
206 | int reg, u16 value) | 206 | int reg, u16 value) |
207 | { | 207 | { |
208 | struct au1000_private *aup = netdev_priv(dev); | 208 | struct au1000_private *aup = netdev_priv(dev); |
209 | volatile u32 *const mii_control_reg = &aup->mac->mii_control; | 209 | u32 *const mii_control_reg = &aup->mac->mii_control; |
210 | volatile u32 *const mii_data_reg = &aup->mac->mii_data; | 210 | u32 *const mii_data_reg = &aup->mac->mii_data; |
211 | u32 timedout = 20; | 211 | u32 timedout = 20; |
212 | u32 mii_control; | 212 | u32 mii_control; |
213 | 213 | ||
214 | while (*mii_control_reg & MAC_MII_BUSY) { | 214 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
215 | mdelay(1); | 215 | mdelay(1); |
216 | if (--timedout == 0) { | 216 | if (--timedout == 0) { |
217 | netdev_err(dev, "mdio_write busy timeout!!\n"); | 217 | netdev_err(dev, "mdio_write busy timeout!!\n"); |
@@ -222,8 +222,8 @@ static void au1000_mdio_write(struct net_device *dev, int phy_addr, | |||
222 | mii_control = MAC_SET_MII_SELECT_REG(reg) | | 222 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
223 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; | 223 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; |
224 | 224 | ||
225 | *mii_data_reg = value; | 225 | writel(value, mii_data_reg); |
226 | *mii_control_reg = mii_control; | 226 | writel(mii_control, mii_control_reg); |
227 | } | 227 | } |
228 | 228 | ||
229 | static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) | 229 | static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
@@ -260,20 +260,26 @@ static int au1000_mdiobus_reset(struct mii_bus *bus) | |||
260 | static void au1000_hard_stop(struct net_device *dev) | 260 | static void au1000_hard_stop(struct net_device *dev) |
261 | { | 261 | { |
262 | struct au1000_private *aup = netdev_priv(dev); | 262 | struct au1000_private *aup = netdev_priv(dev); |
263 | u32 reg; | ||
263 | 264 | ||
264 | netif_dbg(aup, drv, dev, "hard stop\n"); | 265 | netif_dbg(aup, drv, dev, "hard stop\n"); |
265 | 266 | ||
266 | aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); | 267 | reg = readl(&aup->mac->control); |
268 | reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); | ||
269 | writel(reg, &aup->mac->control); | ||
267 | au_sync_delay(10); | 270 | au_sync_delay(10); |
268 | } | 271 | } |
269 | 272 | ||
270 | static void au1000_enable_rx_tx(struct net_device *dev) | 273 | static void au1000_enable_rx_tx(struct net_device *dev) |
271 | { | 274 | { |
272 | struct au1000_private *aup = netdev_priv(dev); | 275 | struct au1000_private *aup = netdev_priv(dev); |
276 | u32 reg; | ||
273 | 277 | ||
274 | netif_dbg(aup, hw, dev, "enable_rx_tx\n"); | 278 | netif_dbg(aup, hw, dev, "enable_rx_tx\n"); |
275 | 279 | ||
276 | aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE); | 280 | reg = readl(&aup->mac->control); |
281 | reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE); | ||
282 | writel(reg, &aup->mac->control); | ||
277 | au_sync_delay(10); | 283 | au_sync_delay(10); |
278 | } | 284 | } |
279 | 285 | ||
@@ -283,6 +289,7 @@ au1000_adjust_link(struct net_device *dev) | |||
283 | struct au1000_private *aup = netdev_priv(dev); | 289 | struct au1000_private *aup = netdev_priv(dev); |
284 | struct phy_device *phydev = aup->phy_dev; | 290 | struct phy_device *phydev = aup->phy_dev; |
285 | unsigned long flags; | 291 | unsigned long flags; |
292 | u32 reg; | ||
286 | 293 | ||
287 | int status_change = 0; | 294 | int status_change = 0; |
288 | 295 | ||
@@ -314,14 +321,15 @@ au1000_adjust_link(struct net_device *dev) | |||
314 | /* switching duplex mode requires to disable rx and tx! */ | 321 | /* switching duplex mode requires to disable rx and tx! */ |
315 | au1000_hard_stop(dev); | 322 | au1000_hard_stop(dev); |
316 | 323 | ||
317 | if (DUPLEX_FULL == phydev->duplex) | 324 | reg = readl(&aup->mac->control); |
318 | aup->mac->control = ((aup->mac->control | 325 | if (DUPLEX_FULL == phydev->duplex) { |
319 | | MAC_FULL_DUPLEX) | 326 | reg |= MAC_FULL_DUPLEX; |
320 | & ~MAC_DISABLE_RX_OWN); | 327 | reg &= ~MAC_DISABLE_RX_OWN; |
321 | else | 328 | } else { |
322 | aup->mac->control = ((aup->mac->control | 329 | reg &= ~MAC_FULL_DUPLEX; |
323 | & ~MAC_FULL_DUPLEX) | 330 | reg |= MAC_DISABLE_RX_OWN; |
324 | | MAC_DISABLE_RX_OWN); | 331 | } |
332 | writel(reg, &aup->mac->control); | ||
325 | au_sync_delay(1); | 333 | au_sync_delay(1); |
326 | 334 | ||
327 | au1000_enable_rx_tx(dev); | 335 | au1000_enable_rx_tx(dev); |
@@ -484,9 +492,9 @@ static void au1000_reset_mac_unlocked(struct net_device *dev) | |||
484 | 492 | ||
485 | au1000_hard_stop(dev); | 493 | au1000_hard_stop(dev); |
486 | 494 | ||
487 | *aup->enable = MAC_EN_CLOCK_ENABLE; | 495 | writel(MAC_EN_CLOCK_ENABLE, &aup->enable); |
488 | au_sync_delay(2); | 496 | au_sync_delay(2); |
489 | *aup->enable = 0; | 497 | writel(0, &aup->enable); |
490 | au_sync_delay(2); | 498 | au_sync_delay(2); |
491 | 499 | ||
492 | aup->tx_full = 0; | 500 | aup->tx_full = 0; |
@@ -530,12 +538,12 @@ au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base) | |||
530 | 538 | ||
531 | for (i = 0; i < NUM_RX_DMA; i++) { | 539 | for (i = 0; i < NUM_RX_DMA; i++) { |
532 | aup->rx_dma_ring[i] = | 540 | aup->rx_dma_ring[i] = |
533 | (volatile struct rx_dma *) | 541 | (struct rx_dma *) |
534 | (rx_base + sizeof(struct rx_dma)*i); | 542 | (rx_base + sizeof(struct rx_dma)*i); |
535 | } | 543 | } |
536 | for (i = 0; i < NUM_TX_DMA; i++) { | 544 | for (i = 0; i < NUM_TX_DMA; i++) { |
537 | aup->tx_dma_ring[i] = | 545 | aup->tx_dma_ring[i] = |
538 | (volatile struct tx_dma *) | 546 | (struct tx_dma *) |
539 | (tx_base + sizeof(struct tx_dma)*i); | 547 | (tx_base + sizeof(struct tx_dma)*i); |
540 | } | 548 | } |
541 | } | 549 | } |
@@ -624,14 +632,16 @@ static int au1000_init(struct net_device *dev) | |||
624 | 632 | ||
625 | spin_lock_irqsave(&aup->lock, flags); | 633 | spin_lock_irqsave(&aup->lock, flags); |
626 | 634 | ||
627 | aup->mac->control = 0; | 635 | writel(0, &aup->mac->control); |
628 | aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; | 636 | aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; |
629 | aup->tx_tail = aup->tx_head; | 637 | aup->tx_tail = aup->tx_head; |
630 | aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; | 638 | aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; |
631 | 639 | ||
632 | aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4]; | 640 | writel(dev->dev_addr[5]<<8 | dev->dev_addr[4], |
633 | aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | | 641 | &aup->mac->mac_addr_high); |
634 | dev->dev_addr[1]<<8 | dev->dev_addr[0]; | 642 | writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | |
643 | dev->dev_addr[1]<<8 | dev->dev_addr[0], | ||
644 | &aup->mac->mac_addr_low); | ||
635 | 645 | ||
636 | 646 | ||
637 | for (i = 0; i < NUM_RX_DMA; i++) | 647 | for (i = 0; i < NUM_RX_DMA; i++) |
@@ -652,8 +662,8 @@ static int au1000_init(struct net_device *dev) | |||
652 | control |= MAC_FULL_DUPLEX; | 662 | control |= MAC_FULL_DUPLEX; |
653 | } | 663 | } |
654 | 664 | ||
655 | aup->mac->control = control; | 665 | writel(control, &aup->mac->control); |
656 | aup->mac->vlan1_tag = 0x8100; /* activate vlan support */ | 666 | writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */ |
657 | au_sync(); | 667 | au_sync(); |
658 | 668 | ||
659 | spin_unlock_irqrestore(&aup->lock, flags); | 669 | spin_unlock_irqrestore(&aup->lock, flags); |
@@ -690,7 +700,7 @@ static int au1000_rx(struct net_device *dev) | |||
690 | { | 700 | { |
691 | struct au1000_private *aup = netdev_priv(dev); | 701 | struct au1000_private *aup = netdev_priv(dev); |
692 | struct sk_buff *skb; | 702 | struct sk_buff *skb; |
693 | volatile struct rx_dma *prxd; | 703 | struct rx_dma *prxd; |
694 | u32 buff_stat, status; | 704 | u32 buff_stat, status; |
695 | struct db_dest *pDB; | 705 | struct db_dest *pDB; |
696 | u32 frmlen; | 706 | u32 frmlen; |
@@ -785,7 +795,7 @@ static void au1000_update_tx_stats(struct net_device *dev, u32 status) | |||
785 | static void au1000_tx_ack(struct net_device *dev) | 795 | static void au1000_tx_ack(struct net_device *dev) |
786 | { | 796 | { |
787 | struct au1000_private *aup = netdev_priv(dev); | 797 | struct au1000_private *aup = netdev_priv(dev); |
788 | volatile struct tx_dma *ptxd; | 798 | struct tx_dma *ptxd; |
789 | 799 | ||
790 | ptxd = aup->tx_dma_ring[aup->tx_tail]; | 800 | ptxd = aup->tx_dma_ring[aup->tx_tail]; |
791 | 801 | ||
@@ -884,7 +894,7 @@ static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) | |||
884 | { | 894 | { |
885 | struct au1000_private *aup = netdev_priv(dev); | 895 | struct au1000_private *aup = netdev_priv(dev); |
886 | struct net_device_stats *ps = &dev->stats; | 896 | struct net_device_stats *ps = &dev->stats; |
887 | volatile struct tx_dma *ptxd; | 897 | struct tx_dma *ptxd; |
888 | u32 buff_stat; | 898 | u32 buff_stat; |
889 | struct db_dest *pDB; | 899 | struct db_dest *pDB; |
890 | int i; | 900 | int i; |
@@ -946,14 +956,16 @@ static void au1000_tx_timeout(struct net_device *dev) | |||
946 | static void au1000_multicast_list(struct net_device *dev) | 956 | static void au1000_multicast_list(struct net_device *dev) |
947 | { | 957 | { |
948 | struct au1000_private *aup = netdev_priv(dev); | 958 | struct au1000_private *aup = netdev_priv(dev); |
959 | u32 reg; | ||
949 | 960 | ||
950 | netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags); | 961 | netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags); |
962 | reg = readl(&aup->mac->control); | ||
951 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | 963 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ |
952 | aup->mac->control |= MAC_PROMISCUOUS; | 964 | reg |= MAC_PROMISCUOUS; |
953 | } else if ((dev->flags & IFF_ALLMULTI) || | 965 | } else if ((dev->flags & IFF_ALLMULTI) || |
954 | netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) { | 966 | netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) { |
955 | aup->mac->control |= MAC_PASS_ALL_MULTI; | 967 | reg |= MAC_PASS_ALL_MULTI; |
956 | aup->mac->control &= ~MAC_PROMISCUOUS; | 968 | reg &= ~MAC_PROMISCUOUS; |
957 | netdev_info(dev, "Pass all multicast\n"); | 969 | netdev_info(dev, "Pass all multicast\n"); |
958 | } else { | 970 | } else { |
959 | struct netdev_hw_addr *ha; | 971 | struct netdev_hw_addr *ha; |
@@ -963,11 +975,12 @@ static void au1000_multicast_list(struct net_device *dev) | |||
963 | netdev_for_each_mc_addr(ha, dev) | 975 | netdev_for_each_mc_addr(ha, dev) |
964 | set_bit(ether_crc(ETH_ALEN, ha->addr)>>26, | 976 | set_bit(ether_crc(ETH_ALEN, ha->addr)>>26, |
965 | (long *)mc_filter); | 977 | (long *)mc_filter); |
966 | aup->mac->multi_hash_high = mc_filter[1]; | 978 | writel(mc_filter[1], &aup->mac->multi_hash_high); |
967 | aup->mac->multi_hash_low = mc_filter[0]; | 979 | writel(mc_filter[0], &aup->mac->multi_hash_low); |
968 | aup->mac->control &= ~MAC_PROMISCUOUS; | 980 | reg &= ~MAC_PROMISCUOUS; |
969 | aup->mac->control |= MAC_HASH_MODE; | 981 | reg |= MAC_HASH_MODE; |
970 | } | 982 | } |
983 | writel(reg, &aup->mac->control); | ||
971 | } | 984 | } |
972 | 985 | ||
973 | static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | 986 | static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
@@ -1067,7 +1080,7 @@ static int __devinit au1000_probe(struct platform_device *pdev) | |||
1067 | } | 1080 | } |
1068 | 1081 | ||
1069 | /* aup->mac is the base address of the MAC's registers */ | 1082 | /* aup->mac is the base address of the MAC's registers */ |
1070 | aup->mac = (volatile struct mac_reg *) | 1083 | aup->mac = (struct mac_reg *) |
1071 | ioremap_nocache(base->start, resource_size(base)); | 1084 | ioremap_nocache(base->start, resource_size(base)); |
1072 | if (!aup->mac) { | 1085 | if (!aup->mac) { |
1073 | dev_err(&pdev->dev, "failed to ioremap MAC registers\n"); | 1086 | dev_err(&pdev->dev, "failed to ioremap MAC registers\n"); |
@@ -1076,7 +1089,7 @@ static int __devinit au1000_probe(struct platform_device *pdev) | |||
1076 | } | 1089 | } |
1077 | 1090 | ||
1078 | /* Setup some variables for quick register address access */ | 1091 | /* Setup some variables for quick register address access */ |
1079 | aup->enable = (volatile u32 *)ioremap_nocache(macen->start, | 1092 | aup->enable = (u32 *)ioremap_nocache(macen->start, |
1080 | resource_size(macen)); | 1093 | resource_size(macen)); |
1081 | if (!aup->enable) { | 1094 | if (!aup->enable) { |
1082 | dev_err(&pdev->dev, "failed to ioremap MAC enable register\n"); | 1095 | dev_err(&pdev->dev, "failed to ioremap MAC enable register\n"); |
@@ -1093,7 +1106,7 @@ static int __devinit au1000_probe(struct platform_device *pdev) | |||
1093 | /* set a random MAC now in case platform_data doesn't provide one */ | 1106 | /* set a random MAC now in case platform_data doesn't provide one */ |
1094 | random_ether_addr(dev->dev_addr); | 1107 | random_ether_addr(dev->dev_addr); |
1095 | 1108 | ||
1096 | *aup->enable = 0; | 1109 | writel(0, &aup->enable); |
1097 | aup->mac_enabled = 0; | 1110 | aup->mac_enabled = 0; |
1098 | 1111 | ||
1099 | pd = pdev->dev.platform_data; | 1112 | pd = pdev->dev.platform_data; |
diff --git a/drivers/net/au1000_eth.h b/drivers/net/au1000_eth.h index 38c1d8845ac6..4b638df22240 100644 --- a/drivers/net/au1000_eth.h +++ b/drivers/net/au1000_eth.h | |||
@@ -46,7 +46,7 @@ | |||
46 | */ | 46 | */ |
47 | struct db_dest { | 47 | struct db_dest { |
48 | struct db_dest *pnext; | 48 | struct db_dest *pnext; |
49 | volatile u32 *vaddr; | 49 | u32 *vaddr; |
50 | dma_addr_t dma_addr; | 50 | dma_addr_t dma_addr; |
51 | }; | 51 | }; |
52 | 52 | ||
@@ -88,8 +88,8 @@ struct mac_reg { | |||
88 | struct au1000_private { | 88 | struct au1000_private { |
89 | struct db_dest *pDBfree; | 89 | struct db_dest *pDBfree; |
90 | struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS]; | 90 | struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS]; |
91 | volatile struct rx_dma *rx_dma_ring[NUM_RX_DMA]; | 91 | struct rx_dma *rx_dma_ring[NUM_RX_DMA]; |
92 | volatile struct tx_dma *tx_dma_ring[NUM_TX_DMA]; | 92 | struct tx_dma *tx_dma_ring[NUM_TX_DMA]; |
93 | struct db_dest *rx_db_inuse[NUM_RX_DMA]; | 93 | struct db_dest *rx_db_inuse[NUM_RX_DMA]; |
94 | struct db_dest *tx_db_inuse[NUM_TX_DMA]; | 94 | struct db_dest *tx_db_inuse[NUM_TX_DMA]; |
95 | u32 rx_head; | 95 | u32 rx_head; |
@@ -120,8 +120,8 @@ struct au1000_private { | |||
120 | 120 | ||
121 | /* These variables are just for quick access | 121 | /* These variables are just for quick access |
122 | * to certain regs addresses. */ | 122 | * to certain regs addresses. */ |
123 | volatile struct mac_reg *mac; /* mac registers */ | 123 | struct mac_reg *mac; /* mac registers */ |
124 | volatile u32 *enable; /* address of MAC Enable Register */ | 124 | u32 *enable; /* address of MAC Enable Register */ |
125 | 125 | ||
126 | u32 vaddr; /* virtual address of rx/tx buffers */ | 126 | u32 vaddr; /* virtual address of rx/tx buffers */ |
127 | dma_addr_t dma_addr; /* dma address of rx/tx buffers */ | 127 | dma_addr_t dma_addr; /* dma address of rx/tx buffers */ |