diff options
author | Chris Pascoe <c.pascoe@itee.uq.edu.au> | 2006-01-09 15:21:31 -0500 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@brturbo.com.br> | 2006-01-09 15:21:31 -0500 |
commit | 3d7d027a9bf41437aa93baf14a1aada521ad9b12 (patch) | |
tree | d53b9ab9cc50a9a3d02eea76fea2dc8a9c9d3a5e | |
parent | a07e60961e4c9cce911a6935bdc90e20c1c97c63 (diff) |
V4L/DVB (3315): Use correct AGC settings for DNTV Live! DVB-T Pro
- My original settings for this board were incorrect and resulted in
an increased number of signal dropouts. Replace this with the settings
from the Windows driver.
Signed-off-by: Chris Pascoe <c.pascoe@itee.uq.edu.au>
Signed-off-by: Mauro Carvalho Chehab <mchehab@brturbo.com.br>
-rw-r--r-- | drivers/media/video/cx88/cx88-dvb.c | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/drivers/media/video/cx88/cx88-dvb.c b/drivers/media/video/cx88/cx88-dvb.c index 8a5997bf4ccd..42c012aaa849 100644 --- a/drivers/media/video/cx88/cx88-dvb.c +++ b/drivers/media/video/cx88/cx88-dvb.c | |||
@@ -112,7 +112,7 @@ static struct videobuf_queue_ops dvb_qops = { | |||
112 | /* ------------------------------------------------------------------ */ | 112 | /* ------------------------------------------------------------------ */ |
113 | 113 | ||
114 | #ifdef HAVE_MT352 | 114 | #ifdef HAVE_MT352 |
115 | static int generic_mt352_demod_init(struct dvb_frontend* fe) | 115 | static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe) |
116 | { | 116 | { |
117 | static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 }; | 117 | static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 }; |
118 | static u8 reset [] = { RESET, 0x80 }; | 118 | static u8 reset [] = { RESET, 0x80 }; |
@@ -191,7 +191,7 @@ static int mt352_pll_set(struct dvb_frontend* fe, | |||
191 | 191 | ||
192 | static struct mt352_config dvico_fusionhdtv = { | 192 | static struct mt352_config dvico_fusionhdtv = { |
193 | .demod_address = 0x0F, | 193 | .demod_address = 0x0F, |
194 | .demod_init = generic_mt352_demod_init, | 194 | .demod_init = dvico_fusionhdtv_demod_init, |
195 | .pll_set = mt352_pll_set, | 195 | .pll_set = mt352_pll_set, |
196 | }; | 196 | }; |
197 | 197 | ||
@@ -208,6 +208,29 @@ static struct mt352_config dvico_fusionhdtv_dual = { | |||
208 | }; | 208 | }; |
209 | 209 | ||
210 | #ifdef HAVE_VP3054_I2C | 210 | #ifdef HAVE_VP3054_I2C |
211 | static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe) | ||
212 | { | ||
213 | static u8 clock_config [] = { 0x89, 0x38, 0x38 }; | ||
214 | static u8 reset [] = { 0x50, 0x80 }; | ||
215 | static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 }; | ||
216 | static u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF, | ||
217 | 0x00, 0xFF, 0x00, 0x40, 0x40 }; | ||
218 | static u8 dntv_extra[] = { 0xB5, 0x7A }; | ||
219 | static u8 capt_range_cfg[] = { 0x75, 0x32 }; | ||
220 | |||
221 | mt352_write(fe, clock_config, sizeof(clock_config)); | ||
222 | udelay(2000); | ||
223 | mt352_write(fe, reset, sizeof(reset)); | ||
224 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | ||
225 | |||
226 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | ||
227 | udelay(2000); | ||
228 | mt352_write(fe, dntv_extra, sizeof(dntv_extra)); | ||
229 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | ||
230 | |||
231 | return 0; | ||
232 | } | ||
233 | |||
211 | static int philips_fmd1216_pll_init(struct dvb_frontend *fe) | 234 | static int philips_fmd1216_pll_init(struct dvb_frontend *fe) |
212 | { | 235 | { |
213 | struct cx8802_dev *dev= fe->dvb->priv; | 236 | struct cx8802_dev *dev= fe->dvb->priv; |
@@ -265,7 +288,7 @@ static int dntv_live_dvbt_pro_pll_set(struct dvb_frontend* fe, | |||
265 | static struct mt352_config dntv_live_dvbt_pro_config = { | 288 | static struct mt352_config dntv_live_dvbt_pro_config = { |
266 | .demod_address = 0x0f, | 289 | .demod_address = 0x0f, |
267 | .no_tuner = 1, | 290 | .no_tuner = 1, |
268 | .demod_init = generic_mt352_demod_init, | 291 | .demod_init = dntv_live_dvbt_pro_demod_init, |
269 | .pll_set = dntv_live_dvbt_pro_pll_set, | 292 | .pll_set = dntv_live_dvbt_pro_pll_set, |
270 | }; | 293 | }; |
271 | #endif | 294 | #endif |