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authorDavid S. Miller <davem@davemloft.net>2006-01-31 21:32:04 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 04:11:19 -0500
commitb70c0fa1613c4f69b4a340a0e2bee387560ebbb1 (patch)
treef7bf22ab75cb9118f5772353fef6efd923faa212
parentbd40791e1d289d807b8580abe1f117e9c62894e4 (diff)
[SPARC64]: Preload TSB entries from update_mmu_cache().
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--arch/sparc64/kernel/tsb.S17
-rw-r--r--arch/sparc64/mm/init.c10
-rw-r--r--include/asm-sparc64/mmu.h2
3 files changed, 29 insertions, 0 deletions
diff --git a/arch/sparc64/kernel/tsb.S b/arch/sparc64/kernel/tsb.S
index fe266bad0a28..08405ed69288 100644
--- a/arch/sparc64/kernel/tsb.S
+++ b/arch/sparc64/kernel/tsb.S
@@ -126,6 +126,23 @@ winfix_trampoline:
126 wrpr %g3, %tnpc ! Write it into TNPC 126 wrpr %g3, %tnpc ! Write it into TNPC
127 done ! Trap return 127 done ! Trap return
128 128
129 /* Insert an entry into the TSB.
130 *
131 * %o0: TSB entry pointer
132 * %o1: tag
133 * %o2: pte
134 */
135 .align 32
136 .globl tsb_insert
137tsb_insert:
138 rdpr %pstate, %o5
139 wrpr %o5, PSTATE_IE, %pstate
140 TSB_LOCK_TAG(%o0, %g2, %g3)
141 TSB_WRITE(%o0, %o2, %o1)
142 wrpr %o5, %pstate
143 retl
144 nop
145
129 /* Reload MMU related context switch state at 146 /* Reload MMU related context switch state at
130 * schedule() time. 147 * schedule() time.
131 * 148 *
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
index a8119cb4fa32..1e8a5a33639d 100644
--- a/arch/sparc64/mm/init.c
+++ b/arch/sparc64/mm/init.c
@@ -277,6 +277,16 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t p
277 mm_rss = get_mm_rss(mm); 277 mm_rss = get_mm_rss(mm);
278 if (mm_rss >= mm->context.tsb_rss_limit) 278 if (mm_rss >= mm->context.tsb_rss_limit)
279 tsb_grow(mm, mm_rss, GFP_ATOMIC); 279 tsb_grow(mm, mm_rss, GFP_ATOMIC);
280
281 if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
282 struct tsb *tsb;
283 unsigned long tag;
284
285 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
286 (mm->context.tsb_nentries - 1UL)];
287 tag = (address >> 22UL) | CTX_HWBITS(mm->context) << 48UL;
288 tsb_insert(tsb, tag, pte_val(pte));
289 }
280} 290}
281 291
282void flush_dcache_page(struct page *page) 292void flush_dcache_page(struct page *page)
diff --git a/include/asm-sparc64/mmu.h b/include/asm-sparc64/mmu.h
index 76008ff6a90b..18f98edfbcda 100644
--- a/include/asm-sparc64/mmu.h
+++ b/include/asm-sparc64/mmu.h
@@ -97,6 +97,8 @@ struct tsb {
97 unsigned long pte; 97 unsigned long pte;
98} __attribute__((aligned(TSB_ENTRY_ALIGNMENT))); 98} __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
99 99
100extern void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte);
101
100typedef struct { 102typedef struct {
101 unsigned long sparc64_ctx_val; 103 unsigned long sparc64_ctx_val;
102 struct tsb *tsb; 104 struct tsb *tsb;