sh: Hook up ERR/PERR/SERR detection for SH7780 PCI host controllers.

These were never handled before, so implement some common infrastructure
to support them, then make use of that in the SH7780-specific code. In
practice there is little here that can not be generalized for SH4 parts,
which will be an incremental change as the 7780/7751 code is gradually
unified.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

5 files changed, 317 insertions, 29 deletions

diff --git a/arch/sh/drivers/pci/common.c b/arch/sh/drivers/pci/common.c
index f67c946a8612..25aec005da18 100644
--- a/arch/sh/drivers/pci/common.c
+++ b/arch/sh/drivers/pci/common.c
@@ -1,4 +1,6 @@
 #include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/timer.h>
 #include <linux/kernel.h>
 
 static int __init
@@ -62,3 +64,80 @@ int __init pci_is_66mhz_capable(struct pci_channel *hose,
 
         return cap66 > 0;
 }
+
+static void pcibios_enable_err(unsigned long __data)
+{
+        struct pci_channel *hose = (struct pci_channel *)__data;
+
+        del_timer(&hose->err_timer);
+        printk(KERN_DEBUG "PCI: re-enabling error IRQ.\n");
+        enable_irq(hose->err_irq);
+}
+
+static void pcibios_enable_serr(unsigned long __data)
+{
+        struct pci_channel *hose = (struct pci_channel *)__data;
+
+        del_timer(&hose->serr_timer);
+        printk(KERN_DEBUG "PCI: re-enabling system error IRQ.\n");
+        enable_irq(hose->serr_irq);
+}
+
+void pcibios_enable_timers(struct pci_channel *hose)
+{
+        if (hose->err_irq) {
+                init_timer(&hose->err_timer);
+                hose->err_timer.data = (unsigned long)hose;
+                hose->err_timer.function = pcibios_enable_err;
+        }
+
+        if (hose->serr_irq) {
+                init_timer(&hose->serr_timer);
+                hose->serr_timer.data = (unsigned long)hose;
+                hose->serr_timer.function = pcibios_enable_serr;
+        }
+}
+
+/*
+ * A simple handler for the regular PCI status errors, called from IRQ
+ * context.
+ */
+unsigned int pcibios_handle_status_errors(unsigned long addr,
+                                          unsigned int status,
+                                          struct pci_channel *hose)
+{
+        unsigned int cmd = 0;
+
+        if (status & PCI_STATUS_REC_MASTER_ABORT) {
+                printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n", addr);
+                cmd |= PCI_STATUS_REC_MASTER_ABORT;
+        }
+
+        if (status & PCI_STATUS_REC_TARGET_ABORT) {
+                printk(KERN_DEBUG "PCI: target abort: ");
+                pcibios_report_status(PCI_STATUS_REC_TARGET_ABORT |
+                                      PCI_STATUS_SIG_TARGET_ABORT |
+                                      PCI_STATUS_REC_MASTER_ABORT, 1);
+                printk("\n");
+
+                cmd |= PCI_STATUS_REC_TARGET_ABORT;
+        }
+
+        if (status & (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY)) {
+                printk(KERN_DEBUG "PCI: parity error detected: ");
+                pcibios_report_status(PCI_STATUS_PARITY |
+                                      PCI_STATUS_DETECTED_PARITY, 1);
+                printk("\n");
+
+                cmd |= PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY;
+
+                /* Now back off of the IRQ for awhile */
+                if (hose->err_irq) {
+                        disable_irq(hose->err_irq);
+                        hose->err_timer.expires = jiffies + HZ;
+                        add_timer(&hose->err_timer);
+                }
+        }
+
+        return cmd;
+}
diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c
index e55e81a71727..0b81999fb88b 100644
--- a/arch/sh/drivers/pci/ops-sh4.c
+++ b/arch/sh/drivers/pci/ops-sh4.c
@@ -16,7 +16,7 @@
  * Direct access to PCI hardware...
  */
 #define CONFIG_CMD(bus, devfn, where) \
-        (P1SEG | (bus->number << 16) | (devfn << 8) | (where & ~3))
+        (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
 
 static DEFINE_SPINLOCK(sh4_pci_lock);
 
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index 0e0ddd67e6e1..86373314f458 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -11,6 +11,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/timer.h>
+#include <linux/irq.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
 #include <linux/log2.h>
@@ -39,8 +42,165 @@ static struct pci_channel sh7780_pci_controller = {
         .io_resource    = &sh7785_io_resource,
         .io_offset      = 0x00000000,
         .io_map_base    = SH7780_PCI_IO_BASE,
+        .serr_irq       = evt2irq(0xa00),
+        .err_irq        = evt2irq(0xaa0),
 };
 
+struct pci_errors {
+        unsigned int    mask;
+        const char      *str;
+} pci_arbiter_errors[] = {
+        { SH4_PCIAINT_MBKN,     "master broken" },
+        { SH4_PCIAINT_TBTO,     "target bus time out" },
+        { SH4_PCIAINT_MBTO,     "master bus time out" },
+        { SH4_PCIAINT_TABT,     "target abort" },
+        { SH4_PCIAINT_MABT,     "master abort" },
+        { SH4_PCIAINT_RDPE,     "read data parity error" },
+        { SH4_PCIAINT_WDPE,     "write data parity error" },
+}, pci_interrupt_errors[] = {
+        { SH4_PCIINT_MLCK,      "master lock error" },
+        { SH4_PCIINT_TABT,      "target-target abort" },
+        { SH4_PCIINT_TRET,      "target retry time out" },
+        { SH4_PCIINT_MFDE,      "master function disable erorr" },
+        { SH4_PCIINT_PRTY,      "address parity error" },
+        { SH4_PCIINT_SERR,      "SERR" },
+        { SH4_PCIINT_TWDP,      "data parity error for target write" },
+        { SH4_PCIINT_TRDP,      "PERR detected for target read" },
+        { SH4_PCIINT_MTABT,     "target abort for master" },
+        { SH4_PCIINT_MMABT,     "master abort for master" },
+        { SH4_PCIINT_MWPD,      "master write data parity error" },
+        { SH4_PCIINT_MRPD,      "master read data parity error" },
+};
+
+static irqreturn_t sh7780_pci_err_irq(int irq, void *dev_id)
+{
+        struct pci_channel *hose = dev_id;
+        unsigned long addr;
+        unsigned int status;
+        unsigned int cmd;
+        int i;
+
+        addr = __raw_readl(hose->reg_base + SH4_PCIALR);
+
+        /*
+         * Handle status errors.
+         */
+        status = __raw_readw(hose->reg_base + PCI_STATUS);
+        if (status & (PCI_STATUS_PARITY |
+                      PCI_STATUS_DETECTED_PARITY |
+                      PCI_STATUS_SIG_TARGET_ABORT |
+                      PCI_STATUS_REC_TARGET_ABORT |
+                      PCI_STATUS_REC_MASTER_ABORT)) {
+                cmd = pcibios_handle_status_errors(addr, status, hose);
+                if (likely(cmd))
+                        __raw_writew(cmd, hose->reg_base + PCI_STATUS);
+        }
+
+        /*
+         * Handle arbiter errors.
+         */
+        status = __raw_readl(hose->reg_base + SH4_PCIAINT);
+        for (i = cmd = 0; i < ARRAY_SIZE(pci_arbiter_errors); i++) {
+                if (status & pci_arbiter_errors[i].mask) {