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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-01-28 08:21:30 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-01-28 08:21:30 -0500
commitc00d4ffdbace1bdc9fdd888e4ba6d207ffa3b679 (patch)
tree2c9ddd5ae9cd899758b0785d4c7eb4bc200d66df
parentd0d42df2a440003d96c8bf29991c2afb691ef720 (diff)
parent8f86dda3ed8f05748f2351ae967926227a91ca2a (diff)
Merge branch 'orion' into devel
* orion: (26 commits) [ARM] Orion: implement power-off method for QNAP TS-109/209 [ARM] Orion: add support for QNAP TS-109/TS-209 [ARM] Orion: I2C support [I2C] i2c-mv64xxx: Don't set i2c_adapter.retries [I2C] Split mv643xx I2C platform support [ARM] Orion: enable CONFIG_RTC_DRV_M41T80 for D-Link DNS-323 [ARM] Orion defconfig [ARM] Orion: add support for Orion/MV88F5181 based D-Link DNS-323 [ARM] Orion: MV88F5181 support bits [ARM] Orion: Buffalo/Revogear Kurobox Pro support [ARM] OrionNAS RD board support [ARM] Orion: support for Marvell Orion-2 (88F5281) Development Board [ARM] Orion: common platform setup for Gigabit Ethernet port [ARM] Orion: platform device registration for UART, USB and NAND [ARM] Orion: system timer support [ARM] Orion edge GPIO IRQ support [ARM] Orion: IRQ support [ARM] Orion: provide GPIO method for enabling hardware assisted blinking [ARM] Orion: GPIO support [ARM] Orion: programable address map support ... Conflicts: arch/arm/Kconfig arch/arm/Makefile Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/Kconfig16
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/compressed/head.S15
-rw-r--r--arch/arm/configs/orion_defconfig1384
-rw-r--r--arch/arm/mach-orion/Kconfig41
-rw-r--r--arch/arm/mach-orion/Makefile6
-rw-r--r--arch/arm/mach-orion/Makefile.boot3
-rw-r--r--arch/arm/mach-orion/addr-map.c484
-rw-r--r--arch/arm/mach-orion/common.c315
-rw-r--r--arch/arm/mach-orion/common.h78
-rw-r--r--arch/arm/mach-orion/db88f5281-setup.c364
-rw-r--r--arch/arm/mach-orion/dns323-setup.c322
-rw-r--r--arch/arm/mach-orion/gpio.c225
-rw-r--r--arch/arm/mach-orion/irq.c241
-rw-r--r--arch/arm/mach-orion/kurobox_pro-setup.c234
-rw-r--r--arch/arm/mach-orion/pci.c557
-rw-r--r--arch/arm/mach-orion/rd88f5182-setup.c306
-rw-r--r--arch/arm/mach-orion/time.c181
-rw-r--r--arch/arm/mach-orion/ts209-setup.c335
-rw-r--r--arch/arm/mm/Kconfig25
-rw-r--r--arch/arm/mm/Makefile1
-rw-r--r--arch/arm/mm/proc-feroceon.S506
-rw-r--r--arch/powerpc/sysdev/mv64x60_dev.c6
-rw-r--r--arch/ppc/syslib/mv64x60.c1
-rw-r--r--drivers/i2c/busses/Kconfig2
-rw-r--r--drivers/i2c/busses/i2c-mv64xxx.c32
-rw-r--r--include/asm-arm/arch-orion/debug-macro.S17
-rw-r--r--include/asm-arm/arch-orion/dma.h1
-rw-r--r--include/asm-arm/arch-orion/entry-macro.S31
-rw-r--r--include/asm-arm/arch-orion/gpio.h28
-rw-r--r--include/asm-arm/arch-orion/hardware.h24
-rw-r--r--include/asm-arm/arch-orion/io.h27
-rw-r--r--include/asm-arm/arch-orion/irqs.h61
-rw-r--r--include/asm-arm/arch-orion/memory.h15
-rw-r--r--include/asm-arm/arch-orion/orion.h143
-rw-r--r--include/asm-arm/arch-orion/platform.h25
-rw-r--r--include/asm-arm/arch-orion/system.h31
-rw-r--r--include/asm-arm/arch-orion/timex.h12
-rw-r--r--include/asm-arm/arch-orion/uncompress.h44
-rw-r--r--include/asm-arm/arch-orion/vmalloc.h5
-rw-r--r--include/asm-arm/cacheflush.h8
-rw-r--r--include/asm-arm/proc-fns.h8
-rw-r--r--include/linux/mv643xx.h10
-rw-r--r--include/linux/mv643xx_i2c.h22
44 files changed, 6156 insertions, 37 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e53b0ed9d00a..6835a4c8affa 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -334,6 +334,16 @@ config ARCH_MXC
334 help 334 help
335 Support for Freescale MXC/iMX-based family of processors 335 Support for Freescale MXC/iMX-based family of processors
336 336
337config ARCH_ORION
338 bool "Marvell Orion"
339 depends on MMU
340 select PCI
341 select GENERIC_GPIO
342 select GENERIC_TIME
343 select GENERIC_CLOCKEVENTS
344 help
345 Support for Marvell Orion System on Chip family.
346
337config ARCH_PNX4008 347config ARCH_PNX4008
338 bool "Philips Nexperia PNX4008 Mobile" 348 bool "Philips Nexperia PNX4008 Mobile"
339 help 349 help
@@ -454,6 +464,8 @@ source "arch/arm/mach-omap1/Kconfig"
454 464
455source "arch/arm/mach-omap2/Kconfig" 465source "arch/arm/mach-omap2/Kconfig"
456 466
467source "arch/arm/mach-orion/Kconfig"
468
457source "arch/arm/plat-s3c24xx/Kconfig" 469source "arch/arm/plat-s3c24xx/Kconfig"
458source "arch/arm/plat-s3c/Kconfig" 470source "arch/arm/plat-s3c/Kconfig"
459 471
@@ -732,7 +744,7 @@ config LEDS
732 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 744 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
733 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ 745 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
734 ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \ 746 ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \
735 ARCH_KS8695 747 ARCH_KS8695 || MACH_RD88F5182
736 help 748 help
737 If you say Y here, the LEDs on your machine will be used 749 If you say Y here, the LEDs on your machine will be used
738 to provide useful information about your current system status. 750 to provide useful information about your current system status.
@@ -967,7 +979,7 @@ config FPE_FASTFPE
967 979
968config VFP 980config VFP
969 bool "VFP-format floating point maths" 981 bool "VFP-format floating point maths"
970 depends on CPU_V6 || CPU_ARM926T || CPU_V7 982 depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
971 help 983 help
972 Say Y to include VFP support code in the kernel. This is needed 984 Say Y to include VFP support code in the kernel. This is needed
973 if your hardware includes a VFP unit. 985 if your hardware includes a VFP unit.
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index dd220d189843..7b8ff66febe1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -139,6 +139,7 @@ endif
139 machine-$(CONFIG_ARCH_KS8695) := ks8695 139 machine-$(CONFIG_ARCH_KS8695) := ks8695
140 incdir-$(CONFIG_ARCH_MXC) := mxc 140 incdir-$(CONFIG_ARCH_MXC) := mxc
141 machine-$(CONFIG_ARCH_MX3) := mx3 141 machine-$(CONFIG_ARCH_MX3) := mx3
142 machine-$(CONFIG_ARCH_ORION) := orion
142 machine-$(CONFIG_ARCH_MSM7X00A) := msm 143 machine-$(CONFIG_ARCH_MSM7X00A) := msm
143 144
144ifeq ($(CONFIG_ARCH_EBSA110),y) 145ifeq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 5cac46a19bb7..3c2c8f2a1dc4 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -623,6 +623,12 @@ proc_types:
623 b __armv4_mmu_cache_off 623 b __armv4_mmu_cache_off
624 b __armv4_mmu_cache_flush 624 b __armv4_mmu_cache_flush
625 625
626 .word 0x56055310 @ Feroceon
627 .word 0xfffffff0
628 b __armv4_mmu_cache_on
629 b __armv4_mmu_cache_off
630 b __armv5tej_mmu_cache_flush
631
626 @ These match on the architecture ID 632 @ These match on the architecture ID
627 633
628 .word 0x00020000 @ ARMv4T 634 .word 0x00020000 @ ARMv4T
@@ -641,7 +647,7 @@ proc_types:
641 .word 0x000f0000 647 .word 0x000f0000
642 b __armv4_mmu_cache_on 648 b __armv4_mmu_cache_on
643 b __armv4_mmu_cache_off 649 b __armv4_mmu_cache_off
644 b __armv4_mmu_cache_flush 650 b __armv5tej_mmu_cache_flush
645 651
646 .word 0x0007b000 @ ARMv6 652 .word 0x0007b000 @ ARMv6
647 .word 0x000ff000 653 .word 0x000ff000
@@ -821,6 +827,13 @@ iflush:
821 mcr p15, 0, r10, c7, c10, 4 @ drain WB 827 mcr p15, 0, r10, c7, c10, 4 @ drain WB
822 mov pc, lr 828 mov pc, lr
823 829
830__armv5tej_mmu_cache_flush:
8311: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
832 bne 1b
833 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
834 mcr p15, 0, r0, c7, c10, 4 @ drain WB
835 mov pc, lr
836
824__armv4_mmu_cache_flush: 837__armv4_mmu_cache_flush:
825 mov r2, #64*1024 @ default: 32K dcache size (*2) 838 mov r2, #64*1024 @ default: 32K dcache size (*2)
826 mov r11, #32 @ default: 32 byte line size 839 mov r11, #32 @ default: 32 byte line size
diff --git a/arch/arm/configs/orion_defconfig b/arch/arm/configs/orion_defconfig
new file mode 100644
index 000000000000..17a55def1103
--- /dev/null
+++ b/arch/arm/configs/orion_defconfig
@@ -0,0 +1,1384 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24-rc3
4# Wed Nov 28 15:13:57 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_LOCK_KERNEL=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35CONFIG_LOCALVERSION=""
36CONFIG_LOCALVERSION_AUTO=y
37CONFIG_SWAP=y
38CONFIG_SYSVIPC=y
39CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_POSIX_MQUEUE is not set
41# CONFIG_BSD_PROCESS_ACCT is not set
42# CONFIG_TASKSTATS is not set
43# CONFIG_USER_NS is not set
44# CONFIG_PID_NS is not set
45# CONFIG_AUDIT is not set
46# CONFIG_IKCONFIG is not set
47CONFIG_LOG_BUF_SHIFT=14
48# CONFIG_CGROUPS is not set
49CONFIG_FAIR_GROUP_SCHED=y
50CONFIG_FAIR_USER_SCHED=y
51# CONFIG_FAIR_CGROUP_SCHED is not set
52CONFIG_SYSFS_DEPRECATED=y
53# CONFIG_RELAY is not set
54# CONFIG_BLK_DEV_INITRD is not set
55CONFIG_CC_OPTIMIZE_FOR_SIZE=y
56CONFIG_SYSCTL=y
57CONFIG_EMBEDDED=y
58CONFIG_UID16=y
59CONFIG_SYSCTL_SYSCALL=y
60CONFIG_KALLSYMS=y
61# CONFIG_KALLSYMS_EXTRA_PASS is not set
62CONFIG_HOTPLUG=y
63CONFIG_PRINTK=y
64CONFIG_BUG=y
65CONFIG_ELF_CORE=y
66CONFIG_BASE_FULL=y
67CONFIG_FUTEX=y
68CONFIG_ANON_INODES=y
69CONFIG_EPOLL=y
70CONFIG_SIGNALFD=y
71CONFIG_EVENTFD=y
72CONFIG_SHMEM=y
73CONFIG_VM_EVENT_COUNTERS=y
74CONFIG_SLAB=y
75# CONFIG_SLUB is not set
76# CONFIG_SLOB is not set
77CONFIG_RT_MUTEXES=y
78# CONFIG_TINY_SHMEM is not set
79CONFIG_BASE_SMALL=0
80CONFIG_MODULES=y
81CONFIG_MODULE_UNLOAD=y
82# CONFIG_MODULE_FORCE_UNLOAD is not set
83# CONFIG_MODVERSIONS is not set
84# CONFIG_MODULE_SRCVERSION_ALL is not set
85# CONFIG_KMOD is not set
86CONFIG_BLOCK=y
87# CONFIG_LBD is not set
88# CONFIG_BLK_DEV_IO_TRACE is not set
89# CONFIG_LSF is not set
90# CONFIG_BLK_DEV_BSG is not set
91
92#
93# IO Schedulers
94#
95CONFIG_IOSCHED_NOOP=y
96CONFIG_IOSCHED_AS=y
97CONFIG_IOSCHED_DEADLINE=y
98CONFIG_IOSCHED_CFQ=y
99# CONFIG_DEFAULT_AS is not set
100# CONFIG_DEFAULT_DEADLINE is not set
101CONFIG_DEFAULT_CFQ=y
102# CONFIG_DEFAULT_NOOP is not set
103CONFIG_DEFAULT_IOSCHED="cfq"
104
105#
106# System Type
107#
108# CONFIG_ARCH_AAEC2000 is not set
109# CONFIG_ARCH_INTEGRATOR is not set
110# CONFIG_ARCH_REALVIEW is not set
111# CONFIG_ARCH_VERSATILE is not set
112# CONFIG_ARCH_AT91 is not set
113# CONFIG_ARCH_CLPS7500 is not set
114# CONFIG_ARCH_CLPS711X is not set
115# CONFIG_ARCH_CO285 is not set
116# CONFIG_ARCH_EBSA110 is not set
117# CONFIG_ARCH_EP93XX is not set
118# CONFIG_ARCH_FOOTBRIDGE is not set
119# CONFIG_ARCH_NETX is not set
120# CONFIG_ARCH_H720X is not set
121# CONFIG_ARCH_IMX is not set
122# CONFIG_ARCH_IOP13XX is not set
123# CONFIG_ARCH_IOP32X is not set
124# CONFIG_ARCH_IOP33X is not set
125# CONFIG_ARCH_IXP23XX is not set
126# CONFIG_ARCH_IXP2000 is not set
127# CONFIG_ARCH_IXP4XX is not set
128# CONFIG_ARCH_L7200 is not set
129# CONFIG_ARCH_KS8695 is not set
130# CONFIG_ARCH_NS9XXX is not set
131# CONFIG_ARCH_MXC is not set
132CONFIG_ARCH_ORION=y
133# CONFIG_ARCH_PNX4008 is not set
134# CONFIG_ARCH_PXA is not set
135# CONFIG_ARCH_RPC is not set
136# CONFIG_ARCH_SA1100 is not set
137# CONFIG_ARCH_S3C2410 is not set
138# CONFIG_ARCH_SHARK is not set
139# CONFIG_ARCH_LH7A40X is not set
140# CONFIG_ARCH_DAVINCI is not set
141# CONFIG_ARCH_OMAP is not set
142
143#
144# Orion Implementations
145#
146CONFIG_MACH_DB88F5281=y
147CONFIG_MACH_RD88F5182=y
148CONFIG_MACH_KUROBOX_PRO=y
149CONFIG_MACH_DNS323=y
150CONFIG_MACH_TS209=y
151
152#
153# Boot options
154#
155
156#
157# Power management
158#
159
160#
161# Processor Type
162#
163CONFIG_CPU_32=y
164CONFIG_CPU_FEROCEON=y
165CONFIG_CPU_FEROCEON_OLD_ID=y
166CONFIG_CPU_32v5=y
167CONFIG_CPU_ABRT_EV5T=y
168CONFIG_CPU_CACHE_VIVT=y
169CONFIG_CPU_COPY_V4WB=y
170CONFIG_CPU_TLB_V4WBI=y
171CONFIG_CPU_CP15=y
172CONFIG_CPU_CP15_MMU=y
173
174#
175# Processor Features
176#
177CONFIG_ARM_THUMB=y
178# CONFIG_CPU_ICACHE_DISABLE is not set
179# CONFIG_CPU_DCACHE_DISABLE is not set
180# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
181# CONFIG_OUTER_CACHE is not set
182
183#
184# Bus support
185#
186CONFIG_PCI=y
187CONFIG_PCI_SYSCALL=y
188# CONFIG_ARCH_SUPPORTS_MSI is not set
189CONFIG_PCI_LEGACY=y
190# CONFIG_PCCARD is not set
191
192#
193# Kernel Features
194#
195CONFIG_TICK_ONESHOT=y
196CONFIG_NO_HZ=y
197CONFIG_HIGH_RES_TIMERS=y
198CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
199CONFIG_PREEMPT=y
200CONFIG_HZ=100
201CONFIG_AEABI=y
202CONFIG_OABI_COMPAT=y
203# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
204CONFIG_SELECT_MEMORY_MODEL=y
205CONFIG_FLATMEM_MANUAL=y
206# CONFIG_DISCONTIGMEM_MANUAL is not set
207# CONFIG_SPARSEMEM_MANUAL is not set
208CONFIG_FLATMEM=y
209CONFIG_FLAT_NODE_MEM_MAP=y
210# CONFIG_SPARSEMEM_STATIC is not set
211# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
212CONFIG_SPLIT_PTLOCK_CPUS=4096
213# CONFIG_RESOURCES_64BIT is not set
214CONFIG_ZONE_DMA_FLAG=1
215CONFIG_BOUNCE=y
216CONFIG_VIRT_TO_BUS=y
217CONFIG_LEDS=y
218CONFIG_LEDS_CPU=y
219CONFIG_ALIGNMENT_TRAP=y
220
221#
222# Boot options
223#
224CONFIG_ZBOOT_ROM_TEXT=0x0
225CONFIG_ZBOOT_ROM_BSS=0x0
226CONFIG_CMDLINE=""
227# CONFIG_XIP_KERNEL is not set
228# CONFIG_KEXEC is not set
229
230#
231# Floating point emulation
232#
233
234#
235# At least one emulation must be selected
236#
237CONFIG_FPE_NWFPE=y
238# CONFIG_FPE_NWFPE_XP is not set
239# CONFIG_FPE_FASTFPE is not set
240CONFIG_VFP=y
241
242#
243# Userspace binary formats
244#
245CONFIG_BINFMT_ELF=y
246# CONFIG_BINFMT_AOUT is not set
247# CONFIG_BINFMT_MISC is not set
248
249#
250# Power management options
251#
252# CONFIG_PM is not set
253CONFIG_SUSPEND_UP_POSSIBLE=y
254
255#
256# Networking
257#
258CONFIG_NET=y
259
260#
261# Networking options
262#
263CONFIG_PACKET=y
264CONFIG_PACKET_MMAP=y
265CONFIG_UNIX=y
266CONFIG_XFRM=y
267# CONFIG_XFRM_USER is not set
268# CONFIG_XFRM_SUB_POLICY is not set
269# CONFIG_XFRM_MIGRATE is not set
270# CONFIG_NET_KEY is not set
271CONFIG_INET=y
272CONFIG_IP_MULTICAST=y
273# CONFIG_IP_ADVANCED_ROUTER is not set
274CONFIG_IP_FIB_HASH=y
275CONFIG_IP_PNP=y
276CONFIG_IP_PNP_DHCP=y
277CONFIG_IP_PNP_BOOTP=y
278# CONFIG_IP_PNP_RARP is not set
279# CONFIG_NET_IPIP is not set
280# CONFIG_NET_IPGRE is not set
281# CONFIG_IP_MROUTE is not set
282# CONFIG_ARPD is not set
283# CONFIG_SYN_COOKIES is not set
284# CONFIG_INET_AH is not set
285# CONFIG_INET_ESP is not set
286# CONFIG_INET_IPCOMP is not set
287# CONFIG_INET_XFRM_TUNNEL is not set
288# CONFIG_INET_TUNNEL is not set
289CONFIG_INET_XFRM_MODE_TRANSPORT=y
290CONFIG_INET_XFRM_MODE_TUNNEL=y
291CONFIG_INET_XFRM_MODE_BEET=y
292# CONFIG_INET_LRO is not set
293CONFIG_INET_DIAG=y
294CONFIG_INET_TCP_DIAG=y
295# CONFIG_TCP_CONG_ADVANCED is not set
296CONFIG_TCP_CONG_CUBIC=y
297CONFIG_DEFAULT_TCP_CONG="cubic"
298# CONFIG_TCP_MD5SIG is not set
299# CONFIG_IPV6 is not set
300# CONFIG_INET6_XFRM_TUNNEL is not set
301# CONFIG_INET6_TUNNEL is not set
302# CONFIG_NETWORK_SECMARK is not set
303# CONFIG_NETFILTER is not set
304# CONFIG_IP_DCCP is not set
305# CONFIG_IP_SCTP is not set
306# CONFIG_TIPC is not set
307# CONFIG_ATM is not set
308# CONFIG_BRIDGE is not set
309# CONFIG_VLAN_8021Q is not set
310# CONFIG_DECNET is not set
311# CONFIG_LLC2 is not set
312# CONFIG_IPX is not set
313# CONFIG_ATALK is not set
314# CONFIG_X25 is not set
315# CONFIG_LAPB is not set
316# CONFIG_ECONET is not set
317# CONFIG_WAN_ROUTER is not set
318# CONFIG_NET_SCHED is not set
319
320#
321# Network testing
322#
323CONFIG_NET_PKTGEN=m
324# CONFIG_HAMRADIO is not set
325# CONFIG_IRDA is not set
326# CONFIG_BT is not set
327# CONFIG_AF_RXRPC is not set
328
329#
330# Wireless
331#
332# CONFIG_CFG80211 is not set
333CONFIG_WIRELESS_EXT=y
334# CONFIG_MAC80211 is not set
335# CONFIG_IEEE80211 is not set
336# CONFIG_RFKILL is not set
337# CONFIG_NET_9P is not set
338
339#
340# Device Drivers
341#
342
343#
344# Generic Driver Options
345#
346CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
347CONFIG_STANDALONE=y
348CONFIG_PREVENT_FIRMWARE_BUILD=y
349CONFIG_FW_LOADER=y
350# CONFIG_SYS_HYPERVISOR is not set
351# CONFIG_CONNECTOR is not set
352CONFIG_MTD=y
353# CONFIG_MTD_DEBUG is not set
354# CONFIG_MTD_CONCAT is not set
355CONFIG_MTD_PARTITIONS=y
356# CONFIG_MTD_REDBOOT_PARTS is not set
357CONFIG_MTD_CMDLINE_PARTS=y
358# CONFIG_MTD_AFS_PARTS is not set
359
360#
361# User Modules And Translation Layers
362#
363CONFIG_MTD_CHAR=y
364CONFIG_MTD_BLKDEVS=y
365CONFIG_MTD_BLOCK=y
366CONFIG_FTL=y
367CONFIG_NFTL=y
368# CONFIG_NFTL_RW is not set
369# CONFIG_INFTL is not set
370# CONFIG_RFD_FTL is not set
371# CONFIG_SSFDC is not set
372# CONFIG_MTD_OOPS is not set
373
374#
375# RAM/ROM/Flash chip drivers
376#
377CONFIG_MTD_CFI=y
378CONFIG_MTD_JEDECPROBE=y
379CONFIG_MTD_GEN_PROBE=y
380CONFIG_MTD_CFI_ADV_OPTIONS=y
381CONFIG_MTD_CFI_NOSWAP=y
382# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
383# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
384CONFIG_MTD_CFI_GEOMETRY=y
385CONFIG_MTD_MAP_BANK_WIDTH_1=y
386CONFIG_MTD_MAP_BANK_WIDTH_2=y
387CONFIG_MTD_MAP_BANK_WIDTH_4=y
388# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
389# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
390# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
391CONFIG_MTD_CFI_I1=y
392CONFIG_MTD_CFI_I2=y
393CONFIG_MTD_CFI_I4=y
394# CONFIG_MTD_CFI_I8 is not set
395# CONFIG_MTD_OTP is not set
396CONFIG_MTD_CFI_INTELEXT=y
397CONFIG_MTD_CFI_AMDSTD=y
398CONFIG_MTD_CFI_STAA=y
399CONFIG_MTD_CFI_UTIL=y
400# CONFIG_MTD_RAM is not set
401# CONFIG_MTD_ROM is not set
402# CONFIG_MTD_ABSENT is not set
403
404#
405# Mapping drivers for chip access
406#
407# CONFIG_MTD_COMPLEX_MAPPINGS is not set
408CONFIG_MTD_PHYSMAP=y
409CONFIG_MTD_PHYSMAP_START=0x0
410CONFIG_MTD_PHYSMAP_LEN=0x0
411CONFIG_MTD_PHYSMAP_BANKWIDTH=0
412# CONFIG_MTD_ARM_INTEGRATOR is not set
413# CONFIG_MTD_IMPA7 is not set
414# CONFIG_MTD_INTEL_VR_NOR is not set
415# CONFIG_MTD_PLATRAM is not set
416
417#
418# Self-contained MTD device drivers
419#
420# CONFIG_MTD_PMC551 is not set
421# CONFIG_MTD_SLRAM is not set
422# CONFIG_MTD_PHRAM is not set
423# CONFIG_MTD_MTDRAM is not set
424# CONFIG_MTD_BLOCK2MTD is not set
425
426#
427# Disk-On-Chip Device Drivers
428#
429# CONFIG_MTD_DOC2000 is not set
430# CONFIG_MTD_DOC2001 is not set
431# CONFIG_MTD_DOC2001PLUS is not set
432CONFIG_MTD_NAND=y
433CONFIG_MTD_NAND_VERIFY_WRITE=y
434# CONFIG_MTD_NAND_ECC_SMC is not set
435# CONFIG_MTD_NAND_MUSEUM_IDS is not set
436CONFIG_MTD_NAND_IDS=y
437# CONFIG_MTD_NAND_DISKONCHIP is not set
438# CONFIG_MTD_NAND_CAFE is not set
439# CONFIG_MTD_NAND_NANDSIM is not set
440# CONFIG_MTD_NAND_PLATFORM is not set
441# CONFIG_MTD_ALAUDA is not set
442CONFIG_MTD_NAND_ORION=y
443# CONFIG_MTD_ONENAND is not set
444
445#
446# UBI - Unsorted block images
447#
448# CONFIG_MTD_UBI is not set
449# CONFIG_PARPORT is not set
450CONFIG_BLK_DEV=y
451# CONFIG_BLK_CPQ_DA is not set
452# CONFIG_BLK_CPQ_CISS_DA is not set
453# CONFIG_BLK_DEV_DAC960 is not set
454# CONFIG_BLK_DEV_UMEM is not set
455# CONFIG_BLK_DEV_COW_COMMON is not set
456CONFIG_BLK_DEV_LOOP=y
457# CONFIG_BLK_DEV_CRYPTOLOOP is not set
458# CONFIG_BLK_DEV_NBD is not set
459# CONFIG_BLK_DEV_SX8 is not set
460# CONFIG_BLK_DEV_UB is not set
461# CONFIG_BLK_DEV_RAM is not set
462# CONFIG_CDROM_PKTCDVD is not set
463# CONFIG_ATA_OVER_ETH is not set
464CONFIG_MISC_DEVICES=y
465# CONFIG_PHANTOM is not set
466# CONFIG_EEPROM_93CX6 is not set
467# CONFIG_SGI_IOC4 is not set
468# CONFIG_TIFM_CORE is not set
469
470#
471# SCSI device support
472#
473# CONFIG_RAID_ATTRS is not set
474CONFIG_SCSI=y
475CONFIG_SCSI_DMA=y
476# CONFIG_SCSI_TGT is not set
477# CONFIG_SCSI_NETLINK is not set
478CONFIG_SCSI_PROC_FS=y
479
480#
481# SCSI support type (disk, tape, CD-ROM)
482#
483CONFIG_BLK_DEV_SD=y
484# CONFIG_CHR_DEV_ST is not set
485# CONFIG_CHR_DEV_OSST is not set
486CONFIG_BLK_DEV_SR=y
487# CONFIG_BLK_DEV_SR_VENDOR is not set
488CONFIG_CHR_DEV_SG=y
489# CONFIG_CHR_DEV_SCH is not set
490
491#
492# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
493#
494CONFIG_SCSI_MULTI_LUN=y
495# CONFIG_SCSI_CONSTANTS is not set
496# CONFIG_SCSI_LOGGING is not set
497# CONFIG_SCSI_SCAN_ASYNC is not set
498CONFIG_SCSI_WAIT_SCAN=m
499
500#
501# SCSI Transports
502#
503# CONFIG_SCSI_SPI_ATTRS is not set
504# CONFIG_SCSI_FC_ATTRS is not set
505# CONFIG_SCSI_ISCSI_ATTRS is not set
506# CONFIG_SCSI_SAS_LIBSAS is not set
507# CONFIG_SCSI_SRP_ATTRS is not set
508CONFIG_SCSI_LOWLEVEL=y
509# CONFIG_ISCSI_TCP is not set
510# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
511# CONFIG_SCSI_3W_9XXX is not set
512# CONFIG_SCSI_ACARD is not set
513# CONFIG_SCSI_AACRAID is not set
514# CONFIG_SCSI_AIC7XXX is not set
515# CONFIG_SCSI_AIC7XXX_OLD is not set
516# CONFIG_SCSI_AIC79XX is not set
517# CONFIG_SCSI_AIC94XX is not set
518# CONFIG_SCSI_DPT_I2O is not set
519# CONFIG_SCSI_ADVANSYS is not set
520# CONFIG_SCSI_ARCMSR is not set
521# CONFIG_MEGARAID_NEWGEN is not set
522# CONFIG_MEGARAID_LEGACY is not set
523# CONFIG_MEGARAID_SAS is not set
524# CONFIG_SCSI_HPTIOP is not set
525# CONFIG_SCSI_DMX3191D is not set
526# CONFIG_SCSI_FUTURE_DOMAIN is not set
527# CONFIG_SCSI_IPS is not set
528# CONFIG_SCSI_INITIO is not set
529# CONFIG_SCSI_INIA100 is not set
530# CONFIG_SCSI_STEX is not set
531CONFIG_SCSI_MVSATA=y
532
533#
534# Sata options
535#
536# CONFIG_MV_SATA_SUPPORT_ATAPI is not set
537# CONFIG_MV_SATA_ENABLE_1MB_IOS is not set
538CONFIG_SATA_NO_DEBUG=y
539# CONFIG_SATA_DEBUG_ON_ERROR is not set
540# CONFIG_SATA_FULL_DEBUG is not set
541# CONFIG_SCSI_SYM53C8XX_2 is not set
542# CONFIG_SCSI_IPR is not set
543# CONFIG_SCSI_QLOGIC_1280 is not set
544# CONFIG_SCSI_QLA_FC is not set
545# CONFIG_SCSI_QLA_ISCSI is not set
546# CONFIG_SCSI_LPFC is not set
547# CONFIG_SCSI_DC395x is not set
548# CONFIG_SCSI_DC390T is not set
549# CONFIG_SCSI_NSP32 is not set
550# CONFIG_SCSI_DEBUG is not set
551# CONFIG_SCSI_SRP is not set
552CONFIG_ATA=m
553# CONFIG_ATA_NONSTANDARD is not set
554# CONFIG_SATA_AHCI is not set
555# CONFIG_SATA_SVW is not set
556# CONFIG_ATA_PIIX is not set
557# CONFIG_SATA_MV is not set
558# CONFIG_SATA_NV is not set
559# CONFIG_PDC_ADMA is not set
560# CONFIG_SATA_QSTOR is not set
561# CONFIG_SATA_PROMISE is not set
562# CONFIG_SATA_SX4 is not set
563# CONFIG_SATA_SIL is not set
564# CONFIG_SATA_SIL24 is not set
565# CONFIG_SATA_SIS is not set
566# CONFIG_SATA_ULI is not set
567# CONFIG_SATA_VIA is not set
568# CONFIG_SATA_VITESSE is not set
569# CONFIG_SATA_INIC162X is not set
570# CONFIG_PATA_ALI is not set
571# CONFIG_PATA_AMD is not set
572# CONFIG_PATA_ARTOP is not set
573# CONFIG_PATA_ATIIXP is not set
574# CONFIG_PATA_CMD640_PCI is not set
575# CONFIG_PATA_CMD64X is not set
576# CONFIG_PATA_CS5520 is not set
577# CONFIG_PATA_CS5530 is not set
578# CONFIG_PATA_CYPRESS is not set
579# CONFIG_PATA_EFAR is not set
580# CONFIG_ATA_GENERIC is not set
581# CONFIG_PATA_HPT366 is not set
582# CONFIG_PATA_HPT37X is not set
583# CONFIG_PATA_HPT3X2N is not set
584# CONFIG_PATA_HPT3X3 is not set
585# CONFIG_PATA_IT821X is not set
586# CONFIG_PATA_IT8213 is not set
587# CONFIG_PATA_JMICRON is not set
588# CONFIG_PATA_TRIFLEX is not set
589# CONFIG_PATA_MARVELL is not set
590# CONFIG_PATA_MPIIX is not set
591# CONFIG_PATA_OLDPIIX is not set
592# CONFIG_PATA_NETCELL is not set
593# CONFIG_PATA_NS87410 is not set
594# CONFIG_PATA_NS87415 is not set
595# CONFIG_PATA_OPTI is not set
596# CONFIG_PATA_OPTIDMA is not set
597# CONFIG_PATA_PDC_OLD is not set
598# CONFIG_PATA_RADISYS is not set
599# CONFIG_PATA_RZ1000 is not set
600# CONFIG_PATA_SC1200 is not set
601# CONFIG_PATA_SERVERWORKS is not set
602# CONFIG_PATA_PDC2027X is not set
603# CONFIG_PATA_SIL680 is not set
604# CONFIG_PATA_SIS is not set
605# CONFIG_PATA_VIA is not set
606# CONFIG_PATA_WINBOND is not set
607# CONFIG_PATA_PLATFORM is not set
608# CONFIG_MD is not set
609# CONFIG_FUSION is not set
610
611#
612# IEEE 1394 (FireWire) support
613#
614# CONFIG_FIREWIRE is not set
615# CONFIG_IEEE1394 is not set
616# CONFIG_I2O is not set
617CONFIG_NETDEVICES=y
618# CONFIG_NETDEVICES_MULTIQUEUE is not set
619# CONFIG_DUMMY is not set
620# CONFIG_BONDING is not set
621# CONFIG_MACVLAN is not set
622# CONFIG_EQUALIZER is not set
623# CONFIG_TUN is not set
624# CONFIG_VETH is not set
625# CONFIG_IP1000 is not set
626# CONFIG_ARCNET is not set
627# CONFIG_PHYLIB is not set
628CONFIG_NET_ETHERNET=y
629CONFIG_MII=y
630# CONFIG_AX88796 is not set
631# CONFIG_HAPPYMEAL is not set
632# CONFIG_SUNGEM is not set
633# CONFIG_CASSINI is not set
634# CONFIG_NET_VENDOR_3COM is not set
635# CONFIG_SMC91X is not set
636# CONFIG_DM9000 is not set
637# CONFIG_NET_TULIP is not set
638# CONFIG_HP100 is not set
639# CONFIG_IBM_NEW_EMAC_ZMII is not set
640# CONFIG_IBM_NEW_EMAC_RGMII is not set
641# CONFIG_IBM_NEW_EMAC_TAH is not set
642# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
643CONFIG_NET_PCI=y
644# CONFIG_PCNET32 is not set
645# CONFIG_AMD8111_ETH is not set
646# CONFIG_ADAPTEC_STARFIRE is not set
647# CONFIG_B44 is not set
648# CONFIG_FORCEDETH is not set
649# CONFIG_EEPRO100 is not set
650CONFIG_E100=y
651# CONFIG_FEALNX is not set
652# CONFIG_NATSEMI is not set
653# CONFIG_NE2K_PCI is not set
654# CONFIG_8139CP is not set
655# CONFIG_8139TOO is not set
656# CONFIG_SIS900 is not set
657# CONFIG_EPIC100 is not set
658# CONFIG_SUNDANCE is not set
659# CONFIG_TLAN is not set
660# CONFIG_VIA_RHINE is not set
661# CONFIG_SC92031 is not set
662CONFIG_NETDEV_1000=y
663# CONFIG_ACENIC is not set
664# CONFIG_DL2K is not set
665CONFIG_E1000=y
666CONFIG_E1000_NAPI=y
667# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
668# CONFIG_E1000E is not set
669# CONFIG_NS83820 is not set
670# CONFIG_HAMACHI is not set
671# CONFIG_YELLOWFIN is not set
672# CONFIG_R8169 is not set
673# CONFIG_SIS190 is not set
674CONFIG_SKGE=y
675CONFIG_SKY2=y
676# CONFIG_SK98LIN is not set
677# CONFIG_VIA_VELOCITY is not set
678CONFIG_TIGON3=y
679# CONFIG_BNX2 is not set
680CONFIG_MV643XX_ETH=y
681# CONFIG_QLA3XXX is not set
682# CONFIG_ATL1 is not set
683CONFIG_NETDEV_10000=y
684# CONFIG_CHELSIO_T1 is not set
685# CONFIG_CHELSIO_T3 is not set
686# CONFIG_IXGBE is not set
687# CONFIG_IXGB is not set
688# CONFIG_S2IO is not set
689# CONFIG_MYRI10GE is not set
690# CONFIG_NETXEN_NIC is not set
691# CONFIG_NIU is not set
692# CONFIG_MLX4_CORE is not set
693# CONFIG_TEHUTI is not set
694# CONFIG_TR is not set
695
696#
697# Wireless LAN
698#
699# CONFIG_WLAN_PRE80211 is not set
700# CONFIG_WLAN_80211 is not set
701
702#
703# USB Network Adapters
704#
705# CONFIG_USB_CATC is not set
706# CONFIG_USB_KAWETH is not set
707# CONFIG_USB_PEGASUS is not set
708# CONFIG_USB_RTL8150 is not set
709# CONFIG_USB_USBNET is not set
710# CONFIG_WAN is not set
711# CONFIG_FDDI is not set
712# CONFIG_HIPPI is not set
713# CONFIG_PPP is not set
714# CONFIG_SLIP is not set
715# CONFIG_NET_FC is not set
716# CONFIG_SHAPER is not set
717# CONFIG_NETCONSOLE is not set
718# CONFIG_NETPOLL is not set
719# CONFIG_NET_POLL_CONTROLLER is not set
720# CONFIG_ISDN is not set
721
722#
723# Input device support
724#
725CONFIG_INPUT=y
726# CONFIG_INPUT_FF_MEMLESS is not set
727# CONFIG_INPUT_POLLDEV is not set
728
729#
730# Userland interfaces
731#
732CONFIG_INPUT_MOUSEDEV=y
733CONFIG_INPUT_MOUSEDEV_PSAUX=y
734CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
735CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
736# CONFIG_INPUT_JOYDEV is not set
737# CONFIG_INPUT_EVDEV is not set
738# CONFIG_INPUT_EVBUG is not set
739
740#
741# Input Device Drivers
742#
743# CONFIG_INPUT_KEYBOARD is not set
744# CONFIG_INPUT_MOUSE is not set
745# CONFIG_INPUT_JOYSTICK is not set
746# CONFIG_INPUT_TABLET is not set
747# CONFIG_INPUT_TOUCHSCREEN is not set
748# CONFIG_INPUT_MISC is not set
749
750#
751# Hardware I/O ports
752#
753# CONFIG_SERIO is not set
754# CONFIG_GAMEPORT is not set
755
756#
757# Character devices
758#
759CONFIG_VT=y
760CONFIG_VT_CONSOLE=y
761CONFIG_HW_CONSOLE=y
762# CONFIG_VT_HW_CONSOLE_BINDING is not set
763# CONFIG_SERIAL_NONSTANDARD is not set
764
765#
766# Serial drivers
767#
768CONFIG_SERIAL_8250=y
769CONFIG_SERIAL_8250_CONSOLE=y
770CONFIG_SERIAL_8250_PCI=y
771CONFIG_SERIAL_8250_NR_UARTS=4
772CONFIG_SERIAL_8250_RUNTIME_UARTS=2
773# CONFIG_SERIAL_8250_EXTENDED is not set
774
775#
776# Non-8250 serial port support
777#
778CONFIG_SERIAL_CORE=y
779CONFIG_SERIAL_CORE_CONSOLE=y
780# CONFIG_SERIAL_JSM is not set
781CONFIG_UNIX98_PTYS=y
782CONFIG_LEGACY_PTYS=y
783CONFIG_LEGACY_PTY_COUNT=16
784# CONFIG_IPMI_HANDLER is not set
785CONFIG_HW_RANDOM=m
786# CONFIG_NVRAM is not set
787# CONFIG_R3964 is not set
788# CONFIG_APPLICOM is not set
789# CONFIG_RAW_DRIVER is not set
790# CONFIG_TCG_TPM is not set
791CONFIG_DEVPORT=y
792CONFIG_I2C=y
793CONFIG_I2C_BOARDINFO=y
794CONFIG_I2C_CHARDEV=y
795
796#
797# I2C Algorithms
798#
799# CONFIG_I2C_ALGOBIT is not set
800# CONFIG_I2C_ALGOPCF is not set
801# CONFIG_I2C_ALGOPCA is not set
802
803#
804# I2C Hardware Bus support
805#
806# CONFIG_I2C_ALI1535 is not set
807# CONFIG_I2C_ALI1563 is not set
808# CONFIG_I2C_ALI15X3 is not set
809# CONFIG_I2C_AMD756 is not set
810# CONFIG_I2C_AMD8111 is not set
811# CONFIG_I2C_GPIO is not set
812# CONFIG_I2C_I801 is not set
813# CONFIG_I2C_I810 is not set
814# CONFIG_I2C_PIIX4 is not set
815# CONFIG_I2C_NFORCE2 is not set
816# CONFIG_I2C_OCORES is not set
817# CONFIG_I2C_PARPORT_LIGHT is not set
818# CONFIG_I2C_PROSAVAGE is not set
819# CONFIG_I2C_SAVAGE4 is not set
820# CONFIG_I2C_SIMTEC is not set
821# CONFIG_I2C_SIS5595 is not set
822# CONFIG_I2C_SIS630 is not set
823# CONFIG_I2C_SIS96X is not set
824# CONFIG_I2C_TAOS_EVM is not set
825# CONFIG_I2C_STUB is not set
826# CONFIG_I2C_TINY_USB is not set
827# CONFIG_I2C_VIA is not set
828# CONFIG_I2C_VIAPRO is not set
829# CONFIG_I2C_VOODOO3 is not set
830CONFIG_I2C_MV64XXX=y
831
832#
833# Miscellaneous I2C Chip support
834#
835# CONFIG_SENSORS_DS1337 is not set
836# CONFIG_SENSORS_DS1374 is not set
837# CONFIG_DS1682 is not set
838# CONFIG_SENSORS_EEPROM is not set
839# CONFIG_SENSORS_PCF8574 is not set
840# CONFIG_SENSORS_PCA9539 is not set
841# CONFIG_SENSORS_PCF8591 is not set
842# CONFIG_SENSORS_MAX6875 is not set
843# CONFIG_SENSORS_TSL2550 is not set
844# CONFIG_I2C_DEBUG_CORE is not set
845# CONFIG_I2C_DEBUG_ALGO is not set
846# CONFIG_I2C_DEBUG_BUS is not set
847# CONFIG_I2C_DEBUG_CHIP is not set
848
849#
850# SPI support
851#
852# CONFIG_SPI is not set
853# CONFIG_SPI_MASTER is not set
854# CONFIG_W1 is not set
855# CONFIG_POWER_SUPPLY is not set
856CONFIG_HWMON=y
857# CONFIG_HWMON_VID is not set
858# CONFIG_SENSORS_AD7418 is not set
859# CONFIG_SENSORS_ADM1021 is not set
860# CONFIG_SENSORS_ADM1025 is not set
861# CONFIG_SENSORS_ADM1026 is not set
862# CONFIG_SENSORS_ADM1029 is not set
863# CONFIG_SENSORS_ADM1031 is not set
864# CONFIG_SENSORS_ADM9240 is not set
865# CONFIG_SENSORS_ADT7470 is not set
866# CONFIG_SENSORS_ATXP1 is not set
867# CONFIG_SENSORS_DS1621 is not set
868# CONFIG_SENSORS_I5K_AMB is not set
869# CONFIG_SENSORS_F71805F is not set
870# CONFIG_SENSORS_F71882FG is not set
871# CONFIG_SENSORS_F75375S is not set
872# CONFIG_SENSORS_GL518SM is not set
873# CONFIG_SENSORS_GL520SM is not set
874# CONFIG_SENSORS_IT87 is not set
875# CONFIG_SENSORS_LM63 is not set
876# CONFIG_SENSORS_LM75 is not set
877# CONFIG_SENSORS_LM77 is not set
878# CONFIG_SENSORS_LM78 is not set
879# CONFIG_SENSORS_LM80 is not set
880# CONFIG_SENSORS_LM83 is not set
881# CONFIG_SENSORS_LM85 is not set
882# CONFIG_SENSORS_LM87 is not set
883# CONFIG_SENSORS_LM90 is not set
884# CONFIG_SENSORS_LM92 is not set
885# CONFIG_SENSORS_LM93 is not set
886# CONFIG_SENSORS_MAX1619 is not set
887# CONFIG_SENSORS_MAX6650 is not set
888# CONFIG_SENSORS_PC87360 is not set
889# CONFIG_SENSORS_PC87427 is not set
890# CONFIG_SENSORS_SIS5595 is not set
891# CONFIG_SENSORS_DME1737 is not set
892# CONFIG_SENSORS_SMSC47M1 is not set
893# CONFIG_SENSORS_SMSC47M192 is not set
894# CONFIG_SENSORS_SMSC47B397 is not set
895# CONFIG_SENSORS_THMC50 is not set
896# CONFIG_SENSORS_VIA686A is not set
897# CONFIG_SENSORS_VT1211 is not set
898# CONFIG_SENSORS_VT8231 is not set
899# CONFIG_SENSORS_W83781D is not set
900# CONFIG_SENSORS_W83791D is not set
901# CONFIG_SENSORS_W83792D is not set
902# CONFIG_SENSORS_W83793 is not set
903# CONFIG_SENSORS_W83L785TS is not set
904# CONFIG_SENSORS_W83627HF is not set
905# CONFIG_SENSORS_W83627EHF is not set
906# CONFIG_HWMON_DEBUG_CHIP is not set
907# CONFIG_WATCHDOG is not set
908
909#
910# Sonics Silicon Backplane
911#
912CONFIG_SSB_POSSIBLE=y
913# CONFIG_SSB is not set
914
915#
916# Multifunction device drivers
917#
918# CONFIG_MFD_SM501 is not set
919
920#
921# Multimedia devices
922#
923# CONFIG_VIDEO_DEV is not set
924# CONFIG_DVB_CORE is not set
925CONFIG_DAB=y
926# CONFIG_USB_DABUSB is not set
927
928#
929# Graphics support
930#
931# CONFIG_DRM is not set
932# CONFIG_VGASTATE is not set
933# CONFIG_VIDEO_OUTPUT_CONTROL is not set
934# CONFIG_FB is not set
935# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
936
937#
938# Display device support
939#
940# CONFIG_DISPLAY_SUPPORT is not set
941
942#
943# Console display driver support
944#
945# CONFIG_VGA_CONSOLE is not set
946CONFIG_DUMMY_CONSOLE=y
947
948#
949# Sound
950#
951# CONFIG_SOUND is not set
952CONFIG_HID_SUPPORT=y
953CONFIG_HID=y
954# CONFIG_HID_DEBUG is not set
955# CONFIG_HIDRAW is not set
956
957#
958# USB Input Devices
959#
960CONFIG_USB_HID=y
961# CONFIG_USB_HIDINPUT_POWERBOOK is not set
962# CONFIG_HID_FF is not set
963# CONFIG_USB_HIDDEV is not set
964CONFIG_USB_SUPPORT=y
965CONFIG_USB_ARCH_HAS_HCD=y
966CONFIG_USB_ARCH_HAS_OHCI=y
967CONFIG_USB_ARCH_HAS_EHCI=y
968CONFIG_USB=y
969# CONFIG_USB_DEBUG is not set
970
971#
972# Miscellaneous USB options
973#
974CONFIG_USB_DEVICEFS=y
975CONFIG_USB_DEVICE_CLASS=y
976# CONFIG_USB_DYNAMIC_MINORS is not set
977# CONFIG_USB_OTG is not set
978
979#
980# USB Host Controller Drivers
981#
982CONFIG_USB_EHCI_HCD=y
983CONFIG_USB_EHCI_SPLIT_ISO=y
984CONFIG_USB_EHCI_ROOT_HUB_TT=y
985CONFIG_USB_EHCI_TT_NEWSCHED=y
986# CONFIG_USB_ISP116X_HCD is not set
987CONFIG_USB_OHCI_HCD=y
988# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
989# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
990CONFIG_USB_OHCI_LITTLE_ENDIAN=y
991CONFIG_USB_UHCI_HCD=y
992CONFIG_USB_SL811_HCD=y
993# CONFIG_USB_R8A66597_HCD is not set
994
995#
996# USB Device Class drivers
997#
998# CONFIG_USB_ACM is not set
999CONFIG_USB_PRINTER=y
1000
1001#
1002# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1003#
1004
1005#
1006# may also be needed; see USB_STORAGE Help for more information
1007#
1008CONFIG_USB_STORAGE=y
1009# CONFIG_USB_STORAGE_DEBUG is not set
1010CONFIG_USB_STORAGE_DATAFAB=y
1011CONFIG_USB_STORAGE_FREECOM=y
1012# CONFIG_USB_STORAGE_ISD200 is not set
1013CONFIG_USB_STORAGE_DPCM=y
1014# CONFIG_USB_STORAGE_USBAT is not set
1015CONFIG_USB_STORAGE_SDDR09=y
1016CONFIG_USB_STORAGE_SDDR55=y
1017CONFIG_USB_STORAGE_JUMPSHOT=y
1018# CONFIG_USB_STORAGE_ALAUDA is not set
1019# CONFIG_USB_STORAGE_KARMA is not set
1020# CONFIG_USB_LIBUSUAL is not set
1021
1022#
1023# USB Imaging devices
1024#
1025# CONFIG_USB_MDC800 is not set
1026# CONFIG_USB_MICROTEK is not set
1027# CONFIG_USB_MON is not set
1028
1029#
1030# USB port drivers
1031#
1032
1033#
1034# USB Serial Converter support
1035#
1036# CONFIG_USB_SERIAL is not set
1037
1038#
1039# USB Miscellaneous drivers
1040#
1041# CONFIG_USB_EMI62 is not set
1042# CONFIG_USB_EMI26 is not set
1043# CONFIG_USB_ADUTUX is not set
1044# CONFIG_USB_AUERSWALD is not set
1045# CONFIG_USB_RIO500 is not set
1046# CONFIG_USB_LEGOTOWER is not set
1047# CONFIG_USB_LCD is not set
1048# CONFIG_USB_BERRY_CHARGE is not set
1049# CONFIG_USB_LED is not set
1050# CONFIG_USB_CYPRESS_CY7C63 is not set
1051# CONFIG_USB_CYTHERM is not set
1052# CONFIG_USB_PHIDGET is not set
1053# CONFIG_USB_IDMOUSE is not set
1054# CONFIG_USB_FTDI_ELAN is not set
1055# CONFIG_USB_APPLEDISPLAY is not set
1056# CONFIG_USB_SISUSBVGA is not set
1057# CONFIG_USB_LD is not set
1058# CONFIG_USB_TRANCEVIBRATOR is not set
1059# CONFIG_USB_IOWARRIOR is not set
1060# CONFIG_USB_TEST is not set
1061
1062#
1063# USB DSL modem support
1064#
1065
1066#
1067# USB Gadget Support
1068#
1069# CONFIG_USB_GADGET is not set
1070# CONFIG_MMC is not set
1071CONFIG_NEW_LEDS=y
1072CONFIG_LEDS_CLASS=y
1073
1074#
1075# LED drivers
1076#
1077# CONFIG_LEDS_GPIO is not set
1078
1079#
1080# LED Triggers
1081#
1082CONFIG_LEDS_TRIGGERS=y
1083CONFIG_LEDS_TRIGGER_TIMER=y
1084CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1085CONFIG_RTC_LIB=y
1086CONFIG_RTC_CLASS=y
1087CONFIG_RTC_HCTOSYS=y
1088CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1089# CONFIG_RTC_DEBUG is not set
1090
1091#
1092# RTC interfaces
1093#
1094CONFIG_RTC_INTF_SYSFS=y
1095CONFIG_RTC_INTF_PROC=y
1096CONFIG_RTC_INTF_DEV=y
1097# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1098# CONFIG_RTC_DRV_TEST is not set
1099
1100#
1101# I2C RTC drivers
1102#
1103CONFIG_RTC_DRV_DS1307=y
1104# CONFIG_RTC_DRV_DS1374 is not set
1105# CONFIG_RTC_DRV_DS1672 is not set
1106# CONFIG_RTC_DRV_MAX6900 is not set
1107CONFIG_RTC_DRV_RS5C372=y
1108# CONFIG_RTC_DRV_ISL1208 is not set
1109# CONFIG_RTC_DRV_X1205 is not set
1110# CONFIG_RTC_DRV_PCF8563 is not set
1111# CONFIG_RTC_DRV_PCF8583 is not set
1112CONFIG_RTC_DRV_M41T80=y
1113# CONFIG_RTC_DRV_M41T80_WDT is not set
1114
1115#
1116# SPI RTC drivers
1117#
1118
1119#
1120# Platform RTC drivers
1121#
1122# CONFIG_RTC_DRV_CMOS is not set
1123# CONFIG_RTC_DRV_DS1553 is not set
1124# CONFIG_RTC_DRV_STK17TA8 is not set
1125# CONFIG_RTC_DRV_DS1742 is not set
1126# CONFIG_RTC_DRV_M48T86 is not set
1127# CONFIG_RTC_DRV_M48T59 is not set
1128# CONFIG_RTC_DRV_V3020 is not set
1129
1130#
1131# on-CPU RTC drivers
1132#
1133
1134#
1135# File systems
1136#
1137CONFIG_EXT2_FS=y
1138# CONFIG_EXT2_FS_XATTR is not set
1139# CONFIG_EXT2_FS_XIP is not set
1140CONFIG_EXT3_FS=y
1141# CONFIG_EXT3_FS_XATTR is not set
1142# CONFIG_EXT4DEV_FS is not set
1143CONFIG_JBD=y
1144# CONFIG_REISERFS_FS is not set
1145# CONFIG_JFS_FS is not set
1146# CONFIG_FS_POSIX_ACL is not set
1147# CONFIG_XFS_FS is not set
1148# CONFIG_GFS2_FS is not set
1149# CONFIG_OCFS2_FS is not set
1150# CONFIG_MINIX_FS is not set
1151# CONFIG_ROMFS_FS is not set
1152CONFIG_INOTIFY=y
1153CONFIG_INOTIFY_USER=y
1154# CONFIG_QUOTA is not set
1155CONFIG_DNOTIFY=y
1156# CONFIG_AUTOFS_FS is not set
1157# CONFIG_AUTOFS4_FS is not set
1158# CONFIG_FUSE_FS is not set
1159
1160#
1161# CD-ROM/DVD Filesystems
1162#
1163CONFIG_ISO9660_FS=y
1164# CONFIG_JOLIET is not set
1165# CONFIG_ZISOFS is not set
1166CONFIG_UDF_FS=m
1167CONFIG_UDF_NLS=y
1168
1169#
1170# DOS/FAT/NT Filesystems
1171#
1172CONFIG_FAT_FS=y
1173CONFIG_MSDOS_FS=y
1174CONFIG_VFAT_FS=y
1175CONFIG_FAT_DEFAULT_CODEPAGE=437
1176CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1177# CONFIG_NTFS_FS is not set
1178
1179#
1180# Pseudo filesystems
1181#
1182CONFIG_PROC_FS=y
1183CONFIG_PROC_SYSCTL=y
1184CONFIG_SYSFS=y
1185CONFIG_TMPFS=y
1186# CONFIG_TMPFS_POSIX_ACL is not set
1187# CONFIG_HUGETLB_PAGE is not set
1188# CONFIG_CONFIGFS_FS is not set
1189
1190#
1191# Miscellaneous filesystems
1192#
1193# CONFIG_ADFS_FS is not set
1194# CONFIG_AFFS_FS is not set
1195# CONFIG_HFS_FS is not set
1196# CONFIG_HFSPLUS_FS is not set
1197# CONFIG_BEFS_FS is not set
1198# CONFIG_BFS_FS is not set
1199# CONFIG_EFS_FS is not set
1200CONFIG_JFFS2_FS=y
1201CONFIG_JFFS2_FS_DEBUG=0
1202CONFIG_JFFS2_FS_WRITEBUFFER=y
1203# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1204# CONFIG_JFFS2_SUMMARY is not set
1205# CONFIG_JFFS2_FS_XATTR is not set
1206# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1207CONFIG_JFFS2_ZLIB=y
1208# CONFIG_JFFS2_LZO is not set
1209CONFIG_JFFS2_RTIME=y
1210# CONFIG_JFFS2_RUBIN is not set
1211CONFIG_CRAMFS=y
1212# CONFIG_VXFS_FS is not set
1213# CONFIG_HPFS_FS is not set
1214# CONFIG_QNX4FS_FS is not set
1215# CONFIG_SYSV_FS is not set
1216# CONFIG_UFS_FS is not set
1217CONFIG_NETWORK_FILESYSTEMS=y
1218CONFIG_NFS_FS=y
1219CONFIG_NFS_V3=y
1220# CONFIG_NFS_V3_ACL is not set
1221# CONFIG_NFS_V4 is not set
1222# CONFIG_NFS_DIRECTIO is not set
1223# CONFIG_NFSD is not set
1224CONFIG_ROOT_NFS=y
1225CONFIG_LOCKD=y
1226CONFIG_LOCKD_V4=y
1227CONFIG_NFS_COMMON=y
1228CONFIG_SUNRPC=y
1229# CONFIG_SUNRPC_BIND34 is not set
1230# CONFIG_RPCSEC_GSS_KRB5 is not set
1231# CONFIG_RPCSEC_GSS_SPKM3 is not set
1232# CONFIG_SMB_FS is not set
1233# CONFIG_CIFS is not set
1234# CONFIG_NCP_FS is not set
1235# CONFIG_CODA_FS is not set
1236# CONFIG_AFS_FS is not set
1237
1238#
1239# Partition Types
1240#
1241CONFIG_PARTITION_ADVANCED=y
1242# CONFIG_ACORN_PARTITION is not set
1243# CONFIG_OSF_PARTITION is not set
1244# CONFIG_AMIGA_PARTITION is not set
1245# CONFIG_ATARI_PARTITION is not set
1246# CONFIG_MAC_PARTITION is not set
1247CONFIG_MSDOS_PARTITION=y
1248CONFIG_BSD_DISKLABEL=y
1249CONFIG_MINIX_SUBPARTITION=y
1250CONFIG_SOLARIS_X86_PARTITION=y
1251CONFIG_UNIXWARE_DISKLABEL=y
1252CONFIG_LDM_PARTITION=y
1253CONFIG_LDM_DEBUG=y
1254# CONFIG_SGI_PARTITION is not set
1255# CONFIG_ULTRIX_PARTITION is not set
1256CONFIG_SUN_PARTITION=y
1257# CONFIG_KARMA_PARTITION is not set
1258# CONFIG_EFI_PARTITION is not set
1259# CONFIG_SYSV68_PARTITION is not set
1260CONFIG_NLS=y
1261CONFIG_NLS_DEFAULT="iso8859-1"
1262CONFIG_NLS_CODEPAGE_437=y
1263# CONFIG_NLS_CODEPAGE_737 is not set
1264# CONFIG_NLS_CODEPAGE_775 is not set
1265CONFIG_NLS_CODEPAGE_850=y
1266# CONFIG_NLS_CODEPAGE_852 is not set
1267# CONFIG_NLS_CODEPAGE_855 is not set
1268# CONFIG_NLS_CODEPAGE_857 is not set
1269# CONFIG_NLS_CODEPAGE_860 is not set
1270# CONFIG_NLS_CODEPAGE_861 is not set
1271# CONFIG_NLS_CODEPAGE_862 is not set
1272# CONFIG_NLS_CODEPAGE_863 is not set
1273# CONFIG_NLS_CODEPAGE_864 is not set
1274# CONFIG_NLS_CODEPAGE_865 is not set
1275# CONFIG_NLS_CODEPAGE_866 is not set
1276# CONFIG_NLS_CODEPAGE_869 is not set
1277# CONFIG_NLS_CODEPAGE_936 is not set
1278# CONFIG_NLS_CODEPAGE_950 is not set
1279# CONFIG_NLS_CODEPAGE_932 is not set
1280# CONFIG_NLS_CODEPAGE_949 is not set
1281# CONFIG_NLS_CODEPAGE_874 is not set
1282# CONFIG_NLS_ISO8859_8 is not set
1283# CONFIG_NLS_CODEPAGE_1250 is not set
1284# CONFIG_NLS_CODEPAGE_1251 is not set
1285# CONFIG_NLS_ASCII is not set
1286CONFIG_NLS_ISO8859_1=y
1287CONFIG_NLS_ISO8859_2=y
1288# CONFIG_NLS_ISO8859_3 is not set
1289# CONFIG_NLS_ISO8859_4 is not set
1290# CONFIG_NLS_ISO8859_5 is not set
1291# CONFIG_NLS_ISO8859_6 is not set
1292# CONFIG_NLS_ISO8859_7 is not set
1293# CONFIG_NLS_ISO8859_9 is not set
1294# CONFIG_NLS_ISO8859_13 is not set
1295# CONFIG_NLS_ISO8859_14 is not set
1296# CONFIG_NLS_ISO8859_15 is not set
1297# CONFIG_NLS_KOI8_R is not set
1298# CONFIG_NLS_KOI8_U is not set
1299# CONFIG_NLS_UTF8 is not set
1300# CONFIG_DLM is not set
1301CONFIG_INSTRUMENTATION=y
1302# CONFIG_PROFILING is not set
1303# CONFIG_MARKERS is not set
1304
1305#
1306# Kernel hacking
1307#
1308# CONFIG_PRINTK_TIME is not set
1309CONFIG_ENABLE_WARN_DEPRECATED=y
1310CONFIG_ENABLE_MUST_CHECK=y
1311# CONFIG_MAGIC_SYSRQ is not set
1312# CONFIG_UNUSED_SYMBOLS is not set
1313# CONFIG_DEBUG_FS is not set
1314# CONFIG_HEADERS_CHECK is not set
1315# CONFIG_DEBUG_KERNEL is not set
1316# CONFIG_DEBUG_BUGVERBOSE is not set
1317CONFIG_FRAME_POINTER=y
1318# CONFIG_SAMPLES is not set
1319CONFIG_DEBUG_USER=y
1320
1321#
1322# Security options
1323#
1324# CONFIG_KEYS is not set
1325# CONFIG_SECURITY is not set
1326# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1327CONFIG_CRYPTO=y
1328CONFIG_CRYPTO_ALGAPI=m
1329CONFIG_CRYPTO_BLKCIPHER=m
1330CONFIG_CRYPTO_MANAGER=m
1331# CONFIG_CRYPTO_HMAC is not set
1332# CONFIG_CRYPTO_XCBC is not set
1333# CONFIG_CRYPTO_NULL is not set
1334# CONFIG_CRYPTO_MD4 is not set
1335# CONFIG_CRYPTO_MD5 is not set
1336# CONFIG_CRYPTO_SHA1 is not set
1337# CONFIG_CRYPTO_SHA256 is not set
1338# CONFIG_CRYPTO_SHA512 is not set
1339# CONFIG_CRYPTO_WP512 is not set
1340# CONFIG_CRYPTO_TGR192 is not set
1341# CONFIG_CRYPTO_GF128MUL is not set
1342CONFIG_CRYPTO_ECB=m
1343CONFIG_CRYPTO_CBC=m
1344CONFIG_CRYPTO_PCBC=m
1345# CONFIG_CRYPTO_LRW is not set
1346# CONFIG_CRYPTO_XTS is not set
1347# CONFIG_CRYPTO_CRYPTD is not set
1348# CONFIG_CRYPTO_DES is not set
1349# CONFIG_CRYPTO_FCRYPT is not set
1350# CONFIG_CRYPTO_BLOWFISH is not set
1351# CONFIG_CRYPTO_TWOFISH is not set
1352# CONFIG_CRYPTO_SERPENT is not set
1353# CONFIG_CRYPTO_AES is not set
1354# CONFIG_CRYPTO_CAST5 is not set
1355# CONFIG_CRYPTO_CAST6 is not set
1356# CONFIG_CRYPTO_TEA is not set
1357# CONFIG_CRYPTO_ARC4 is not set
1358# CONFIG_CRYPTO_KHAZAD is not set
1359# CONFIG_CRYPTO_ANUBIS is not set
1360# CONFIG_CRYPTO_SEED is not set
1361# CONFIG_CRYPTO_DEFLATE is not set
1362# CONFIG_CRYPTO_MICHAEL_MIC is not set
1363# CONFIG_CRYPTO_CRC32C is not set
1364# CONFIG_CRYPTO_CAMELLIA is not set
1365# CONFIG_CRYPTO_TEST is not set
1366# CONFIG_CRYPTO_AUTHENC is not set
1367CONFIG_CRYPTO_HW=y
1368
1369#
1370# Library routines
1371#
1372CONFIG_BITREVERSE=y
1373CONFIG_CRC_CCITT=y
1374CONFIG_CRC16=y
1375# CONFIG_CRC_ITU_T is not set
1376CONFIG_CRC32=y
1377# CONFIG_CRC7 is not set
1378CONFIG_LIBCRC32C=y
1379CONFIG_ZLIB_INFLATE=y
1380CONFIG_ZLIB_DEFLATE=y
1381CONFIG_PLIST=y
1382CONFIG_HAS_IOMEM=y
1383CONFIG_HAS_IOPORT=y
1384CONFIG_HAS_DMA=y
diff --git a/arch/arm/mach-orion/Kconfig b/arch/arm/mach-orion/Kconfig
new file mode 100644
index 000000000000..1dcbb6ac5a30
--- /dev/null
+++ b/arch/arm/mach-orion/Kconfig
@@ -0,0 +1,41 @@
1if ARCH_ORION
2
3menu "Orion Implementations"
4
5config MACH_DB88F5281
6 bool "Marvell Orion-2 Development Board"
7 select I2C_BOARDINFO
8 help
9 Say 'Y' here if you want your kernel to support the
10 Marvell Orion-2 (88F5281) Development Board
11
12config MACH_RD88F5182
13 bool "Marvell Orion-NAS Reference Design"
14 select I2C_BOARDINFO
15 help
16 Say 'Y' here if you want your kernel to support the
17 Marvell Orion-NAS (88F5182) RD2
18
19config MACH_KUROBOX_PRO
20 bool "KuroBox Pro"
21 select I2C_BOARDINFO
22 help
23 Say 'Y' here if you want your kernel to support the
24 KuroBox Pro platform.
25
26config MACH_DNS323
27 bool "D-Link DNS-323"
28 select I2C_BOARDINFO
29 help
30 Say 'Y' here if you want your kernel to support the
31 D-Link DNS-323 platform.
32
33config MACH_TS209
34 bool "QNAP TS-109/TS-209"
35 help
36 Say 'Y' here if you want your kernel to support the
37 QNAP TS-109/TS-209 platform.
38
39endmenu
40
41endif
diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion/Makefile
new file mode 100644
index 000000000000..f91d937a73e8
--- /dev/null
+++ b/arch/arm/mach-orion/Makefile
@@ -0,0 +1,6 @@
1obj-y += common.o addr-map.o pci.o gpio.o irq.o time.o
2obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o
3obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o
4obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
5obj-$(CONFIG_MACH_DNS323) += dns323-setup.o
6obj-$(CONFIG_MACH_TS209) += ts209-setup.o
diff --git a/arch/arm/mach-orion/Makefile.boot b/arch/arm/mach-orion/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-orion/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c
new file mode 100644
index 000000000000..488da3811a68
--- /dev/null
+++ b/arch/arm/mach-orion/addr-map.c
@@ -0,0 +1,484 @@
1/*
2 * arch/arm/mach-orion/addr-map.c
3 *
4 * Address map functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <asm/hardware.h>
16#include "common.h"
17
18/*
19 * The Orion has fully programable address map. There's a separate address
20 * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
21 * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
22 * address decode windows that allow it to access any of the Orion resources.
23 *
24 * CPU address decoding --
25 * Linux assumes that it is the boot loader that already setup the access to
26 * DDR and internal registers.
27 * Setup access to PCI and PCI-E IO/MEM space is issued by core.c.
28 * Setup access to various devices located on the device bus interface (e.g.
29 * flashes, RTC, etc) should be issued by machine-setup.c according to
30 * specific board population (by using orion_setup_cpu_win()).
31 *
32 * Non-CPU Masters address decoding --
33 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
34 * banks only (the typical use case).
35 * Setup access for each master to DDR is issued by common.c.
36 *
37 * Note: although orion_setbits() and orion_clrbits() are not atomic
38 * no locking is necessary here since code in this file is only called
39 * at boot time when there is no concurrency issues.
40 */
41
42/*
43 * Generic Address Decode Windows bit settings
44 */
45#define TARGET_DDR 0
46#define TARGET_PCI 3
47#define TARGET_PCIE 4
48#define TARGET_DEV_BUS 1
49#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
50 ((n) == 1) ? 0xd : \
51 ((n) == 2) ? 0xb : \
52 ((n) == 3) ? 0x7 : 0xf)
53#define ATTR_PCIE_MEM 0x59
54#define ATTR_PCIE_IO 0x51
55#define ATTR_PCI_MEM 0x59
56#define ATTR_PCI_IO 0x51
57#define ATTR_DEV_CS0 0x1e
58#define ATTR_DEV_CS1 0x1d
59#define ATTR_DEV_CS2 0x1b
60#define ATTR_DEV_BOOT 0xf
61#define WIN_EN 1
62
63/*
64 * Helpers to get DDR banks info
65 */
66#define DDR_BASE_CS(n) ORION_DDR_REG(0x1500 + ((n) * 8))
67#define DDR_SIZE_CS(n) ORION_DDR_REG(0x1504 + ((n) * 8))
68#define DDR_MAX_CS 4
69#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
70#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
71#define DDR_BANK_EN 1
72
73/*
74 * CPU Address Decode Windows registers
75 */
76#define CPU_WIN_CTRL(n) ORION_BRIDGE_REG(0x000 | ((n) << 4))
77#define CPU_WIN_BASE(n) ORION_BRIDGE_REG(0x004 | ((n) << 4))
78#define CPU_WIN_REMAP_LO(n) ORION_BRIDGE_REG(0x008 | ((n) << 4))
79#define CPU_WIN_REMAP_HI(n) ORION_BRIDGE_REG(0x00c | ((n) << 4))
80#define CPU_MAX_WIN 8
81
82/*
83 * Use this CPU address decode windows allocation
84 */
85#define CPU_WIN_PCIE_IO 0
86#define CPU_WIN_PCI_IO 1
87#define CPU_WIN_PCIE_MEM 2
88#define CPU_WIN_PCI_MEM 3
89#define CPU_WIN_DEV_BOOT 4
90#define CPU_WIN_DEV_CS0 5
91#define CPU_WIN_DEV_CS1 6
92#define CPU_WIN_DEV_CS2 7
93
94/*
95 * PCIE Address Decode Windows registers
96 */
97#define PCIE_BAR_CTRL(n) ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
98#define PCIE_BAR_LO(n) ORION_PCIE_REG(0x0010 + ((n) * 8))
99#define PCIE_BAR_HI(n) ORION_PCIE_REG(0x0014 + ((n) * 8))
100#define PCIE_WIN_CTRL(n) ORION_PCIE_REG(0x1820 + ((n) << 4))
101#define PCIE_WIN_BASE(n) ORION_PCIE_REG(0x1824 + ((n) << 4))
102#define PCIE_WIN_REMAP(n) ORION_PCIE_REG(0x182c + ((n) << 4))
103#define PCIE_DEFWIN_CTRL ORION_PCIE_REG(0x18b0)
104#define PCIE_EXPROM_WIN_CTRL ORION_PCIE_REG(0x18c0)
105#define PCIE_EXPROM_WIN_REMP ORION_PCIE_REG(0x18c4)
106#define PCIE_MAX_BARS 3
107#define PCIE_MAX_WINS 5
108
109/*
110 * Use PCIE BAR '1' for all DDR banks
111 */
112#define PCIE_DRAM_BAR 1
113
114/*
115 * PCI Address Decode Windows registers
116 */
117#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION_PCI_REG(0xc08) : \
118 ((n) == 1) ? ORION_PCI_REG(0xd08) : \
119 ((n) == 2) ? ORION_PCI_REG(0xc0c) : \
120 ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
121#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \
122 ((n) == 1) ? ORION_PCI_REG(0xd48) : \
123 ((n) == 2) ? ORION_PCI_REG(0xc4c) : \
124 ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
125#define PCI_BAR_ENABLE ORION_PCI_REG(0xc3c)
126#define PCI_CTRL_BASE_LO(n) ORION_PCI_REG(0x1e00 | ((n) << 4))
127#define PCI_CTRL_BASE_HI(n) ORION_PCI_REG(0x1e04 | ((n) << 4))
128#define PCI_CTRL_SIZE(n) ORION_PCI_REG(0x1e08 | ((n) << 4))
129#define PCI_ADDR_DECODE_CTRL ORION_PCI_REG(0xd3c)
130
131/*
132 * PCI configuration heleprs for BAR settings
133 */
134#define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
135#define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
136#define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
137
138/*
139 * Gigabit Ethernet Address Decode Windows registers
140 */
141#define ETH_WIN_BASE(win) ORION_ETH_REG(0x200 + ((win) * 8))
142#define ETH_WIN_SIZE(win) ORION_ETH_REG(0x204 + ((win) * 8))
143#define ETH_WIN_REMAP(win) ORION_ETH_REG(0x280 + ((win) * 4))
144#define ETH_WIN_EN ORION_ETH_REG(0x290)
145#define ETH_WIN_PROT ORION_ETH_REG(0x294)
146#define ETH_MAX_WIN 6
147#define ETH_MAX_REMAP_WIN 4
148
149/*
150 * USB Address Decode Windows registers
151 */
152#define USB_WIN_CTRL(i, w) ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \
153 : ORION_USB1_REG(0x320 + ((w) << 4)))
154#define USB_WIN_BASE(i, w) ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \
155 : ORION_USB1_REG(0x324 + ((w) << 4)))
156#define USB_MAX_WIN 4
157
158/*
159 * SATA Address Decode Windows registers
160 */
161#define SATA_WIN_CTRL(win) ORION_SATA_REG(0x30 + ((win) * 0x10))
162#define SATA_WIN_BASE(win) ORION_SATA_REG(0x34 + ((win) * 0x10))
163#define SATA_MAX_WIN 4
164
165static int __init orion_cpu_win_can_remap(u32 win)
166{
167 u32 dev, rev;
168
169 orion_pcie_id(&dev, &rev);
170 if ((dev == MV88F5281_DEV_ID && win < 4)
171 || (dev == MV88F5182_DEV_ID && win < 2)
172 || (dev == MV88F5181_DEV_ID && win < 2))
173 return 1;
174
175 return 0;
176}
177
178void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap)
179{
180 u32 win, attr, ctrl;
181
182 switch (target) {
183 case ORION_PCIE_IO:
184 target = TARGET_PCIE;
185 attr = ATTR_PCIE_IO;
186 win = CPU_WIN_PCIE_IO;
187 break;
188 case ORION_PCI_IO:
189 target = TARGET_PCI;
190 attr = ATTR_PCI_IO;
191 win = CPU_WIN_PCI_IO;
192 break;
193 case ORION_PCIE_MEM:
194 target = TARGET_PCIE;
195 attr = ATTR_PCIE_MEM;
196 win = CPU_WIN_PCIE_MEM;
197 break;
198 case ORION_PCI_MEM:
199 target = TARGET_PCI;
200 attr = ATTR_PCI_MEM;
201 win = CPU_WIN_PCI_MEM;
202 break;
203 case ORION_DEV_BOOT:
204 target = TARGET_DEV_BUS;
205 attr = ATTR_DEV_BOOT;
206 win = CPU_WIN_DEV_BOOT;
207 break;
208 case ORION_DEV0:
209 target = TARGET_DEV_BUS;
210 attr = ATTR_DEV_CS0;
211 win = CPU_WIN_DEV_CS0;
212 break;
213 case ORION_DEV1:
214 target = TARGET_DEV_BUS;
215 attr = ATTR_DEV_CS1;
216 win = CPU_WIN_DEV_CS1;
217 break;
218 case ORION_DEV2:
219 target = TARGET_DEV_BUS;
220 attr = ATTR_DEV_CS2;
221 win = CPU_WIN_DEV_CS2;
222 break;
223 case ORION_DDR:
224 case ORION_REGS:
225 /*
226 * Must be mapped by bootloader.
227 */
228 default:
229 target = attr = win = -1;
230 BUG();
231 }
232
233 base &= 0xffff0000;
234 ctrl = (((size - 1) & 0xffff0000) | (attr << 8) |
235 (target << 4) | WIN_EN);
236
237 orion_write(CPU_WIN_BASE(win), base);
238 orion_write(CPU_WIN_CTRL(win), ctrl);
239
240 if (orion_cpu_win_can_remap(win)) {
241 if (remap >= 0) {
242 orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
243 orion_write(CPU_WIN_REMAP_HI(win), 0);
244 } else {
245 orion_write(CPU_WIN_REMAP_LO(win), base);
246 orion_write(CPU_WIN_REMAP_HI(win), 0);
247 }
248 }
249}
250
251void __init orion_setup_cpu_wins(void)
252{
253 int i;
254
255 /*
256 * First, disable and clear windows
257 */
258 for (i = 0; i < CPU_MAX_WIN; i++) {
259 orion_write(CPU_WIN_BASE(i), 0);
260 orion_write(CPU_WIN_CTRL(i), 0);
261 if (orion_cpu_win_can_remap(i)) {
262 orion_write(CPU_WIN_REMAP_LO(i), 0);
263 orion_write(CPU_WIN_REMAP_HI(i), 0);
264 }
265 }
266
267 /*
268 * Setup windows for PCI+PCIE IO+MAM space
269 */
270 orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE,
271 ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP);
272 orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE,
273 ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP);
274 orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE,
275 ORION_PCIE_MEM_SIZE, -1);
276 orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE,
277 ORION_PCI_MEM_SIZE, -1);
278}
279
280/*
281 * Setup PCIE BARs and Address Decode Wins:
282 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
283 * WIN[0-3] -> DRAM bank[0-3]
284 */
285void __init orion_setup_pcie_wins(void)
286{
287 u32 base, size, i;
288
289 /*
290 * First, disable and clear BARs and windows
291 */
292 for (i = 1; i < PCIE_MAX_BARS; i++) {
293 orion_write(PCIE_BAR_CTRL(i), 0);
294 orion_write(PCIE_BAR_LO(i), 0);
295 orion_write(PCIE_BAR_HI(i), 0);
296 }
297
298 for (i = 0; i < PCIE_MAX_WINS; i++) {
299 orion_write(PCIE_WIN_CTRL(i), 0);
300 orion_write(PCIE_WIN_BASE(i), 0);
301 orion_write(PCIE_WIN_REMAP(i), 0);
302 }
303
304 /*
305 * Setup windows for DDR banks. Count total DDR size on the fly.
306 */
307 base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0)));
308 size = 0;
309 for (i = 0; i < DDR_MAX_CS; i++) {
310 u32 bank_base, bank_size;
311 bank_size = orion_read(DDR_SIZE_CS(i));
312 bank_base = orion_read(DDR_BASE_CS(i));
313 if (bank_size & DDR_BANK_EN) {
314 bank_size = DDR_REG_TO_SIZE(bank_size);
315 bank_base = DDR_REG_TO_BASE(bank_base);
316 orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000);
317 orion_write(PCIE_WIN_REMAP(i), 0);
318 orion_write(PCIE_WIN_CTRL(i),
319 ((bank_size-1) & 0xffff0000) |
320 (ATTR_DDR_CS(i) << 8) |
321 (TARGET_DDR << 4) |
322 (PCIE_DRAM_BAR << 1) | WIN_EN);
323 size += bank_size;
324 }
325 }
326
327 /*
328 * Setup BAR[1] to all DRAM banks
329 */
330 orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000);
331 orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0);
332 orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR),
333 ((size - 1) & 0xffff0000) | WIN_EN);
334}
335
336void __init orion_setup_pci_wins(void)
337{
338 u32 base, size, i;
339
340 /*
341 * First, disable windows
342 */
343 orion_write(PCI_BAR_ENABLE, 0xffffffff);
344
345 /*
346 * Setup windows for DDR banks.
347 */
348 for (i = 0; i < DDR_MAX_CS; i++) {
349 base = orion_read(DDR_BASE_CS(i));
350 size = orion_read(DDR_SIZE_CS(i));
351 if (size & DDR_BANK_EN) {
352 u32 bus, dev, func, reg, val;
353 size = DDR_REG_TO_SIZE(size);
354 base = DDR_REG_TO_BASE(base);
355 bus = orion_pci_local_bus_nr();
356 dev = orion_pci_local_dev_nr();
357 func = PCI_CONF_FUNC_BAR_CS(i);
358 reg = PCI_CONF_REG_BAR_LO_CS(i);
359 orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
360 orion_pci_hw_wr_conf(bus, dev, func, reg, 4,
361 (base & 0xfffff000) | (val & 0xfff));
362 reg = PCI_CONF_REG_BAR_HI_CS(i);
363 orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
364 orion_write(PCI_BAR_SIZE_DDR_CS(i),
365 (size - 1) & 0xfffff000);
366 orion_write(PCI_BAR_REMAP_DDR_CS(i),
367 base & 0xfffff000);
368 orion_clrbits(PCI_BAR_ENABLE, (1 << i));
369 }
370 }
371
372 /*
373 * Disable automatic update of address remaping when writing to BARs
374 */
375 orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
376}
377
378void __init orion_setup_usb_wins(void)
379{
380 int i;
381 u32 usb_if, dev, rev;
382 u32 max_usb_if = 1;
383
384 orion_pcie_id(&dev, &rev);
385 if (dev == MV88F5182_DEV_ID)
386 max_usb_if = 2;
387
388 for (usb_if = 0; usb_if < max_usb_if; usb_if++) {
389 /*
390 * First, disable and clear windows
391 */
392 for (i = 0; i < USB_MAX_WIN; i++) {
393 orion_write(USB_WIN_BASE(usb_if, i), 0);
394 orion_write(USB_WIN_CTRL(usb_if, i), 0);
395 }
396
397 /*
398 * Setup windows for DDR banks.
399 */
400 for (i = 0; i < DDR_MAX_CS; i++) {
401 u32 base, size;
402 size = orion_read(DDR_SIZE_CS(i));
403 base = orion_read(DDR_BASE_CS(i));
404 if (size & DDR_BANK_EN) {
405 base = DDR_REG_TO_BASE(base);
406 size = DDR_REG_TO_SIZE(size);
407 orion_write(USB_WIN_CTRL(usb_if, i),
408 ((size-1) & 0xffff0000) |
409 (ATTR_DDR_CS(i) << 8) |
410 (TARGET_DDR << 4) | WIN_EN);
411 orion_write(USB_WIN_BASE(usb_if, i),
412 base & 0xffff0000);
413 }
414 }
415 }
416}
417
418void __init orion_setup_eth_wins(void)
419{
420 int i;
421
422 /*
423 * First, disable and clear windows
424 */
425 for (i = 0; i < ETH_MAX_WIN; i++) {
426 orion_write(ETH_WIN_BASE(i), 0);
427 orion_write(ETH_WIN_SIZE(i), 0);
428 orion_setbits(ETH_WIN_EN, 1 << i);
429 orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
430 if (i < ETH_MAX_REMAP_WIN)
431 orion_write(ETH_WIN_REMAP(i), 0);
432 }
433
434 /*
435 * Setup windows for DDR banks.
436 */
437 for (i = 0; i < DDR_MAX_CS; i++) {
438 u32 base, size;
439 size = orion_read(DDR_SIZE_CS(i));
440 base = orion_read(DDR_BASE_CS(i));
441 if (size & DDR_BANK_EN) {
442 base = DDR_REG_TO_BASE(base);
443 size = DDR_REG_TO_SIZE(size);
444 orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
445 orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
446 (ATTR_DDR_CS(i) << 8) |
447 TARGET_DDR);
448 orion_clrbits(ETH_WIN_EN, 1 << i);
449 orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
450 }
451 }
452}
453
454void __init orion_setup_sata_wins(void)
455{
456 int i;
457
458 /*
459 * First, disable and clear windows
460 */
461 for (i = 0; i < SATA_MAX_WIN; i++) {
462 orion_write(SATA_WIN_BASE(i), 0);
463 orion_write(SATA_WIN_CTRL(i), 0);
464 }
465
466 /*
467 * Setup windows for DDR banks.
468 */
469 for (i = 0; i < DDR_MAX_CS; i++) {
470 u32 base, size;
471 size = orion_read(DDR_SIZE_CS(i));
472 base = orion_read(DDR_BASE_CS(i));
473 if (size & DDR_BANK_EN) {
474 base = DDR_REG_TO_BASE(base);
475 size = DDR_REG_TO_SIZE(size);
476 orion_write(SATA_WIN_CTRL(i),
477 ((size-1) & 0xffff0000) |
478 (ATTR_DDR_CS(i) << 8) |
479 (TARGET_DDR << 4) | WIN_EN);
480 orion_write(SATA_WIN_BASE(i),
481 base & 0xffff0000);
482 }
483 }
484}
diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c
new file mode 100644
index 000000000000..5e20b6b32508
--- /dev/null
+++ b/arch/arm/mach-orion/common.c
@@ -0,0 +1,315 @@
1/*
2 * arch/arm/mach-orion/common.c
3 *
4 * Core functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/serial_8250.h>
17#include <linux/mv643xx_eth.h>
18#include <linux/mv643xx_i2c.h>
19#include <asm/page.h>
20#include <asm/timex.h>
21#include <asm/mach/map.h>
22#include <asm/arch/orion.h>
23#include "common.h"
24
25/*****************************************************************************
26 * I/O Address Mapping
27 ****************************************************************************/
28static struct map_desc orion_io_desc[] __initdata = {
29 {
30 .virtual = ORION_REGS_BASE,
31 .pfn = __phys_to_pfn(ORION_REGS_BASE),
32 .length = ORION_REGS_SIZE,
33 .type = MT_DEVICE
34 },
35 {
36 .virtual = ORION_PCIE_IO_BASE,
37 .pfn = __phys_to_pfn(ORION_PCIE_IO_BASE),
38 .length = ORION_PCIE_IO_SIZE,
39 .type = MT_DEVICE
40 },
41 {
42 .virtual = ORION_PCI_IO_BASE,
43 .pfn = __phys_to_pfn(ORION_PCI_IO_BASE),
44 .length = ORION_PCI_IO_SIZE,
45 .type = MT_DEVICE
46 },
47 {
48 .virtual = ORION_PCIE_WA_BASE,
49 .pfn = __phys_to_pfn(ORION_PCIE_WA_BASE),
50 .length = ORION_PCIE_WA_SIZE,
51 .type = MT_DEVICE
52 },
53};
54
55void __init orion_map_io(void)
56{
57 iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc));
58}
59
60/*****************************************************************************
61 * UART
62 ****************************************************************************/
63
64static struct resource orion_uart_resources[] = {
65 {
66 .start = UART0_BASE,
67 .end = UART0_BASE + 0xff,
68 .flags = IORESOURCE_MEM,
69 },
70 {
71 .start = IRQ_ORION_UART0,
72 .end = IRQ_ORION_UART0,
73 .flags = IORESOURCE_IRQ,
74 },
75 {
76 .start = UART1_BASE,
77 .end = UART1_BASE + 0xff,
78 .flags = IORESOURCE_MEM,
79 },
80 {
81 .start = IRQ_ORION_UART1,
82 .end = IRQ_ORION_UART1,
83 .flags = IORESOURCE_IRQ,
84 },
85};
86
87static struct plat_serial8250_port orion_uart_data[] = {
88 {
89 .mapbase = UART0_BASE,
90 .membase = (char *)UART0_BASE,
91 .irq = IRQ_ORION_UART0,
92 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
93 .iotype = UPIO_MEM,
94 .regshift = 2,
95 .uartclk = ORION_TCLK,
96 },
97 {
98 .mapbase = UART1_BASE,
99 .membase = (char *)UART1_BASE,
100 .irq = IRQ_ORION_UART1,
101 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
102 .iotype = UPIO_MEM,
103 .regshift = 2,
104 .uartclk = ORION_TCLK,
105 },
106 { },
107};
108
109static struct platform_device orion_uart = {
110 .name = "serial8250",
111 .id = PLAT8250_DEV_PLATFORM,
112 .dev = {
113 .platform_data = orion_uart_data,
114 },
115 .resource = orion_uart_resources,
116 .num_resources = ARRAY_SIZE(orion_uart_resources),
117};
118
119/*******************************************************************************
120 * USB Controller - 2 interfaces
121 ******************************************************************************/
122
123static struct resource orion_ehci0_resources[] = {
124 {
125 .start = ORION_USB0_REG_BASE,
126 .end = ORION_USB0_REG_BASE + SZ_4K,
127 .flags = IORESOURCE_MEM,
128 },
129 {
130 .start = IRQ_ORION_USB0_CTRL,
131 .end = IRQ_ORION_USB0_CTRL,
132 .flags = IORESOURCE_IRQ,
133 },
134};
135
136static struct resource orion_ehci1_resources[] = {
137 {
138 .start = ORION_USB1_REG_BASE,
139 .end = ORION_USB1_REG_BASE + SZ_4K,
140 .flags = IORESOURCE_MEM,
141 },
142 {
143 .start = IRQ_ORION_USB1_CTRL,
144 .end = IRQ_ORION_USB1_CTRL,
145 .flags = IORESOURCE_IRQ,
146 },
147};
148
149static u64 ehci_dmamask = 0xffffffffUL;
150
151static struct platform_device orion_ehci0 = {
152 .name = "orion-ehci",
153 .id = 0,
154 .dev = {
155 .dma_mask = &ehci_dmamask,
156 .coherent_dma_mask = 0xffffffff,
157 },
158 .resource = orion_ehci0_resources,
159 .num_resources = ARRAY_SIZE(orion_ehci0_resources),
160};
161
162static struct platform_device orion_ehci1 = {
163 .name = "orion-ehci",
164 .id = 1,
165 .dev = {
166 .dma_mask = &ehci_dmamask,
167 .coherent_dma_mask = 0xffffffff,
168 },
169 .resource = orion_ehci1_resources,
170 .num_resources = ARRAY_SIZE(orion_ehci1_resources),
171};
172
173/*****************************************************************************
174 * Gigabit Ethernet port
175 * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
176 ****************************************************************************/
177
178static struct resource orion_eth_shared_resources[] = {
179 {
180 .start = ORION_ETH_REG_BASE,
181 .end = ORION_ETH_REG_BASE + 0xffff,
182 .flags = IORESOURCE_MEM,
183 },
184};
185
186static struct platform_device orion_eth_shared = {
187 .name = MV643XX_ETH_SHARED_NAME,
188 .id = 0,
189 .num_resources = 1,
190 .resource = orion_eth_shared_resources,
191};
192
193static struct resource orion_eth_resources[] = {
194 {
195 .name = "eth irq",
196 .start = IRQ_ORION_ETH_SUM,
197 .end = IRQ_ORION_ETH_SUM,
198 .flags = IORESOURCE_IRQ,
199 }
200};
201
202static struct platform_device orion_eth = {
203 .name = MV643XX_ETH_NAME,
204 .id = 0,
205 .num_resources = 1,
206 .resource = orion_eth_resources,
207};
208
209void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data)
210{
211 orion_eth.dev.platform_data = eth_data;
212 platform_device_register(&orion_eth_shared);
213 platform_device_register(&orion_eth);
214}
215
216/*****************************************************************************
217 * I2C controller
218 * (The Orion and Discovery (MV643xx) families share the same I2C controller)
219 ****************************************************************************/
220
221static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
222 .freq_m = 8, /* assumes 166 MHz TCLK */
223 .freq_n = 3,
224 .timeout = 1000, /* Default timeout of 1 second */
225};
226
227static struct resource orion_i2c_resources[] = {
228 {
229 .name = "i2c base",
230 .start = I2C_BASE,
231 .end = I2C_BASE + 0x20 -1,
232 .flags = IORESOURCE_MEM,
233 },
234 {
235 .name = "i2c irq",
236 .start = IRQ_ORION_I2C,
237 .end = IRQ_ORION_I2C,
238 .flags = IORESOURCE_IRQ,
239 },
240};
241
242static struct platform_device orion_i2c = {
243 .name = MV64XXX_I2C_CTLR_NAME,
244 .id = 0,
245 .num_resources = ARRAY_SIZE(orion_i2c_resources),
246 .resource = orion_i2c_resources,
247 .dev = {
248 .platform_data = &orion_i2c_pdata,
249 },
250};
251
252/*****************************************************************************
253 * General
254 ****************************************************************************/
255
256/*
257 * Identify device ID and rev from PCIE configuration header space '0'.
258 */
259static void orion_id(u32 *dev, u32 *rev, char **dev_name)
260{
261 orion_pcie_id(dev, rev);
262
263 if (*dev == MV88F5281_DEV_ID) {
264 if (*rev == MV88F5281_REV_D2) {
265 *dev_name = "MV88F5281-D2";
266 } else if (*rev == MV88F5281_REV_D1) {
267 *dev_name = "MV88F5281-D1";
268 } else {
269 *dev_name = "MV88F5281-Rev-Unsupported";
270 }
271 } else if (*dev == MV88F5182_DEV_ID) {
272 if (*rev == MV88F5182_REV_A2) {
273 *dev_name = "MV88F5182-A2";
274 } else {
275 *dev_name = "MV88F5182-Rev-Unsupported";
276 }
277 } else if (*dev == MV88F5181_DEV_ID) {
278 if (*rev == MV88F5181_REV_B1) {
279 *dev_name = "MV88F5181-Rev-B1";
280 } else {
281 *dev_name = "MV88F5181-Rev-Unsupported";
282 }
283 } else {
284 *dev_name = "Device-Unknown";
285 }
286}
287
288void __init orion_init(void)
289{
290 char *dev_name;
291 u32 dev, rev;
292
293 orion_id(&dev, &rev, &dev_name);
294 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK);
295
296 /*
297 * Setup Orion address map
298 */
299 orion_setup_cpu_wins();
300 orion_setup_usb_wins();
301 orion_setup_eth_wins();
302 orion_setup_pci_wins();
303 orion_setup_pcie_wins();
304 if (dev == MV88F5182_DEV_ID)
305 orion_setup_sata_wins();
306
307 /*
308 * REgister devices
309 */
310 platform_device_register(&orion_uart);
311 platform_device_register(&orion_ehci0);
312 if (dev == MV88F5182_DEV_ID)
313 platform_device_register(&orion_ehci1);
314 platform_device_register(&orion_i2c);
315}
diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h
new file mode 100644
index 000000000000..06c10c06f03e
--- /dev/null
+++ b/arch/arm/mach-orion/common.h
@@ -0,0 +1,78 @@
1#ifndef __ARCH_ORION_COMMON_H__
2#define __ARCH_ORION_COMMON_H__
3
4/*
5 * Basic Orion init functions used early by machine-setup.
6 */
7
8void __init orion_map_io(void);
9void __init orion_init_irq(void);
10void __init orion_init(void);
11
12/*
13 * Enumerations and functions for Orion windows mapping. Used by Orion core
14 * functions to map its interfaces and by the machine-setup to map its on-
15 * board devices. Details in /mach-orion/addr-map.c
16 */
17
18enum orion_target {
19 ORION_DEV_BOOT = 0,
20 ORION_DEV0,
21 ORION_DEV1,
22 ORION_DEV2,
23 ORION_PCIE_MEM,
24 ORION_PCIE_IO,
25 ORION_PCI_MEM,
26 ORION_PCI_IO,
27 ORION_DDR,
28 ORION_REGS,
29 ORION_MAX_TARGETS
30};
31
32void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap);
33void orion_setup_cpu_wins(void);
34void orion_setup_eth_wins(void);
35void orion_setup_usb_wins(void);
36void orion_setup_pci_wins(void);
37void orion_setup_pcie_wins(void);
38void orion_setup_sata_wins(void);
39
40/*
41 * Shared code used internally by other Orion core functions.
42 * (/mach-orion/pci.c)
43 */
44
45struct pci_sys_data;
46struct pci_bus;
47
48void orion_pcie_id(u32 *dev, u32 *rev);
49u32 orion_pcie_local_bus_nr(void);
50u32 orion_pci_local_bus_nr(void);
51u32 orion_pci_local_dev_nr(void);
52int orion_pci_sys_setup(int nr, struct pci_sys_data *sys);
53struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
54int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val);
55int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val);
56
57/*
58 * Valid GPIO pins according to MPP setup, used by machine-setup.
59 * (/mach-orion/gpio.c).
60 */
61
62void __init orion_gpio_set_valid_pins(u32 pins);
63void gpio_display(void); /* debug */
64
65/*
66 * Orion system timer (clocksource + clockevnt, /mach-orion/time.c)
67 */
68extern struct sys_timer orion_timer;
69
70/*
71 * Pull in Orion Ethernet platform_data, used by machine-setup
72 */
73
74struct mv643xx_eth_platform_data;
75
76void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
77
78#endif /* __ARCH_ORION_COMMON_H__ */
diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion/db88f5281-setup.c
new file mode 100644
index 000000000000..cb2a95ce5b57
--- /dev/null
+++ b/arch/arm/mach-orion/db88f5281-setup.c
@@ -0,0 +1,364 @@
1/*
2 * arch/arm/mach-orion/db88f5281-setup.c
3 *
4 * Marvell Orion-2 Development Board Setup
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/pci.h>
17#include <linux/irq.h>
18#include <linux/mtd/physmap.h>
19#include <linux/mtd/nand.h>
20#include <linux/timer.h>
21#include <linux/mv643xx_eth.h>
22#include <linux/i2c.h>
23#include <asm/mach-types.h>
24#include <asm/gpio.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/pci.h>
27#include <asm/arch/orion.h>
28#include <asm/arch/platform.h>
29#include "common.h"
30
31/*****************************************************************************
32 * DB-88F5281 on board devices
33 ****************************************************************************/
34
35/*
36 * 512K NOR flash Device bus boot chip select
37 */
38
39#define DB88F5281_NOR_BOOT_BASE 0xf4000000
40#define DB88F5281_NOR_BOOT_SIZE SZ_512K
41
42/*
43 * 7-Segment on Device bus chip select 0
44 */
45
46#define DB88F5281_7SEG_BASE 0xfa000000
47#define DB88F5281_7SEG_SIZE SZ_1K
48
49/*
50 * 32M NOR flash on Device bus chip select 1
51 */
52
53#define DB88F5281_NOR_BASE 0xfc000000
54#define DB88F5281_NOR_SIZE SZ_32M
55
56/*
57 * 32M NAND flash on Device bus chip select 2
58 */
59
60#define DB88F5281_NAND_BASE 0xfa800000
61#define DB88F5281_NAND_SIZE SZ_1K
62
63/*
64 * PCI
65 */
66
67#define DB88F5281_PCI_SLOT0_OFFS 7
68#define DB88F5281_PCI_SLOT0_IRQ_PIN 12
69#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13
70
71/*****************************************************************************
72 * 512M NOR Flash on Device bus Boot CS
73 ****************************************************************************/
74
75static struct physmap_flash_data db88f5281_boot_flash_data = {
76 .width = 1, /* 8 bit bus width */
77};
78
79static struct resource db88f5281_boot_flash_resource = {
80 .flags = IORESOURCE_MEM,
81 .start = DB88F5281_NOR_BOOT_BASE,
82 .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1,
83};
84
85static struct platform_device db88f5281_boot_flash = {
86 .name = "physmap-flash",
87 .id = 0,
88 .dev = {
89 .platform_data = &db88f5281_boot_flash_data,
90 },
91 .num_resources = 1,
92 .resource = &db88f5281_boot_flash_resource,
93};
94
95/*****************************************************************************
96 * 32M NOR Flash on Device bus CS1
97 ****************************************************************************/
98
99static struct physmap_flash_data db88f5281_nor_flash_data = {
100 .width = 4, /* 32 bit bus width */
101};
102
103static struct resource db88f5281_nor_flash_resource = {
104 .flags = IORESOURCE_MEM,
105 .start = DB88F5281_NOR_BASE,
106 .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1,
107};
108
109static struct platform_device db88f5281_nor_flash = {
110 .name = "physmap-flash",
111 .id = 1,
112 .dev = {
113 .platform_data = &db88f5281_nor_flash_data,
114 },
115 .num_resources = 1,
116 .resource = &db88f5281_nor_flash_resource,
117};
118
119/*****************************************************************************
120 * 32M NAND Flash on Device bus CS2
121 ****************************************************************************/
122
123static struct mtd_partition db88f5281_nand_parts[] = {
124 {
125 .name = "kernel",
126 .offset = 0,
127 .size = SZ_2M,
128 },
129 {
130 .name = "root",
131 .offset = SZ_2M,
132 .size = (SZ_16M - SZ_2M),
133 },
134 {
135 .name = "user",
136 .offset = SZ_16M,
137 .size = SZ_8M,
138 },
139 {
140 .name = "recovery",
141 .offset = (SZ_16M + SZ_8M),
142 .size = SZ_8M,
143 },
144};
145
146static struct resource db88f5281_nand_resource = {
147 .flags = IORESOURCE_MEM,
148 .start = DB88F5281_NAND_BASE,
149 .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1,
150};
151
152static struct orion_nand_data db88f5281_nand_data = {
153 .parts = db88f5281_nand_parts,
154 .nr_parts = ARRAY_SIZE(db88f5281_nand_parts),
155 .cle = 0,
156 .ale = 1,
157 .width = 8,
158};
159
160static struct platform_device db88f5281_nand_flash = {
161 .name = "orion_nand",
162 .id = -1,
163 .dev = {
164 .platform_data = &db88f5281_nand_data,
165 },
166 .resource = &db88f5281_nand_resource,
167 .num_resources = 1,
168};
169
170/*****************************************************************************
171 * 7-Segment on Device bus CS0
172 * Dummy counter every 2 sec
173 ****************************************************************************/
174
175static void __iomem *db88f5281_7seg;
176static struct timer_list db88f5281_timer;
177
178static void db88f5281_7seg_event(unsigned long data)
179{
180 static int count = 0;
181 writel(0, db88f5281_7seg + (count << 4));
182 count = (count + 1) & 7;
183 mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
184}
185
186static int __init db88f5281_7seg_init(void)
187{
188 if (machine_is_db88f5281()) {
189 db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE,
190 DB88F5281_7SEG_SIZE);
191 if (!db88f5281_7seg) {
192 printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n");
193 return -EIO;
194 }
195 setup_timer(&db88f5281_timer, db88f5281_7seg_event, 0);
196 mod_timer(&db88f5281_timer, jiffies + 2 * HZ);
197 }
198
199 return 0;
200}
201
202__initcall(db88f5281_7seg_init);
203
204/*****************************************************************************
205 * PCI
206 ****************************************************************************/
207
208void __init db88f5281_pci_preinit(void)
209{
210 int pin;
211
212 /*
213 * Configure PCI GPIO IRQ pins
214 */
215 pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
216 if (gpio_request(pin, "PCI Int1") == 0) {
217 if (gpio_direction_input(pin) == 0) {
218 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
219 } else {
220 printk(KERN_ERR "db88f5281_pci_preinit faield to "
221 "set_irq_type pin %d\n", pin);
222 gpio_free(pin);
223 }
224 } else {
225 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
226 }
227
228 pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
229 if (gpio_request(pin, "PCI Int2") == 0) {
230 if (gpio_direction_input(pin) == 0) {
231 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
232 } else {
233 printk(KERN_ERR "db88f5281_pci_preinit faield "
234 "to set_irq_type pin %d\n", pin);
235 gpio_free(pin);
236 }
237 } else {
238 printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin);
239 }
240}
241
242static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
243{
244 /*
245 * PCIE IRQ is connected internally (not GPIO)
246 */
247 if (dev->bus->number == orion_pcie_local_bus_nr())
248 return IRQ_ORION_PCIE0_INT;
249
250 /*
251 * PCI IRQs are connected via GPIOs
252 */
253 switch (slot - DB88F5281_PCI_SLOT0_OFFS) {
254 case 0:
255 return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN);
256 case 1:
257 case 2:
258 return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN);
259 default:
260 return -1;
261 }
262}
263
264static struct hw_pci db88f5281_pci __initdata = {
265 .nr_controllers = 2,
266 .preinit = db88f5281_pci_preinit,
267 .swizzle = pci_std_swizzle,
268 .setup = orion_pci_sys_setup,
269 .scan = orion_pci_sys_scan_bus,
270 .map_irq = db88f5281_pci_map_irq,
271};
272
273static int __init db88f5281_pci_init(void)
274{
275 if (machine_is_db88f5281())
276 pci_common_init(&db88f5281_pci);
277
278 return 0;
279}
280
281subsys_initcall(db88f5281_pci_init);
282
283/*****************************************************************************
284 * Ethernet
285 ****************************************************************************/
286static struct mv643xx_eth_platform_data db88f5281_eth_data = {
287 .phy_addr = 8,
288 .force_phy_addr = 1,
289};
290
291/*****************************************************************************
292 * RTC DS1339 on I2C bus
293 ****************************************************************************/
294static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
295 .driver_name = "rtc-ds1307",
296 .type = "ds1339",
297 .addr = 0x68,
298};
299
300/*****************************************************************************
301 * General Setup
302 ****************************************************************************/
303
304static struct platform_device *db88f5281_devs[] __initdata = {
305 &db88f5281_boot_flash,
306 &db88f5281_nor_flash,
307 &db88f5281_nand_flash,
308};
309
310static void __init db88f5281_init(void)
311{
312 /*
313 * Basic Orion setup. Need to be called early.
314 */
315 orion_init();
316
317 /*
318 * Setup the CPU address decode windows for our on-board devices
319 */
320 orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE,
321 DB88F5281_NOR_BOOT_SIZE, -1);
322 orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE,
323 DB88F5281_7SEG_SIZE, -1);
324 orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE,
325 DB88F5281_NOR_SIZE, -1);
326 orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE,
327 DB88F5281_NAND_SIZE, -1);
328
329 /*
330 * Setup Multiplexing Pins:
331 * MPP0: GPIO (USB Over Current) MPP1: GPIO (USB Vbat input)
332 * MPP2: PCI_REQn[2] MPP3: PCI_GNTn[2]
333 * MPP4: PCI_REQn[3] MPP5: PCI_GNTn[3]
334 * MPP6: GPIO (JP0, CON17.2) MPP7: GPIO (JP1, CON17.1)
335 * MPP8: GPIO (JP2, CON11.2) MPP9: GPIO (JP3, CON11.3)
336 * MPP10: GPIO (RTC int) MPP11: GPIO (Baud Rate Generator)
337 * MPP12: GPIO (PCI int 1) MPP13: GPIO (PCI int 2)
338 * MPP14: NAND_REn[2] MPP15: NAND_WEn[2]
339 * MPP16: UART1_RX MPP17: UART1_TX
340 * MPP18: UART1_CTS MPP19: UART1_RTS
341 * MPP-DEV: DEV_D[16:31]
342 */
343 orion_write(MPP_0_7_CTRL, 0x00222203);
344 orion_write(MPP_8_15_CTRL, 0x44000000);
345 orion_write(MPP_16_19_CTRL, 0);
346 orion_write(MPP_DEV_CTRL, 0);
347
348 orion_gpio_set_valid_pins(0x00003fc3);
349
350 platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
351 i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
352 orion_eth_init(&db88f5281_eth_data);
353}
354
355MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
356 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
357 .phys_io = ORION_REGS_BASE,
358 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc,
359 .boot_params = 0x00000100,
360 .init_machine = db88f5281_init,
361 .map_io = orion_map_io,
362 .init_irq = orion_init_irq,
363 .timer = &orion_timer,
364MACHINE_END
diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion/dns323-setup.c
new file mode 100644
index 000000000000..c8a806f249c6
--- /dev/null
+++ b/arch/arm/mach-orion/dns323-setup.c
@@ -0,0 +1,322 @@
1/*
2 * arch/arm/mach-orion/dns323-setup.c
3 *
4 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/pci.h>
17#include <linux/irq.h>
18#include <linux/mtd/physmap.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/leds.h>
21#include <linux/gpio_keys.h>
22#include <linux/input.h>
23#include <linux/i2c.h>
24#include <asm/mach-types.h>
25#include <asm/gpio.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/pci.h>
28#include <asm/arch/orion.h>
29#include <asm/arch/platform.h>
30#include "common.h"
31
32#define DNS323_GPIO_LED_RIGHT_AMBER 1
33#define DNS323_GPIO_LED_LEFT_AMBER 2
34#define DNS323_GPIO_LED_POWER 5
35#define DNS323_GPIO_OVERTEMP 6
36#define DNS323_GPIO_RTC 7
37#define DNS323_GPIO_POWER_OFF 8
38#define DNS323_GPIO_KEY_POWER 9
39#define DNS323_GPIO_KEY_RESET 10
40
41/****************************************************************************
42 * PCI setup
43 */
44
45static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
46{
47 /* PCI-E */
48 if (dev->bus->number == orion_pcie_local_bus_nr())
49 return IRQ_ORION_PCIE0_INT;
50
51 pr_err("%s: requested mapping for unknown bus\n", __func__);
52
53 return -1;
54}
55
56static struct hw_pci dns323_pci __initdata = {
57 .nr_controllers = 1,
58 .swizzle = pci_std_swizzle,
59 .setup = orion_pci_sys_setup,
60 .scan = orion_pci_sys_scan_bus,
61 .map_irq = dns323_pci_map_irq,
62};
63
64static int __init dns323_pci_init(void)
65{
66 if (machine_is_dns323())
67 pci_common_init(&dns323_pci);
68
69 return 0;
70}
71
72subsys_initcall(dns323_pci_init);
73
74/****************************************************************************
75 * Ethernet
76 */
77
78static struct mv643xx_eth_platform_data dns323_eth_data = {
79 .phy_addr = 8,
80 .force_phy_addr = 1,
81};
82
83/****************************************************************************
84 * 8MiB NOR flash (Spansion S29GL064M90TFIR4)
85 *
86 * Layout as used by D-Link:
87 * 0x00000000-0x00010000 : "MTD1"
88 * 0x00010000-0x00020000 : "MTD2"
89 * 0x00020000-0x001a0000 : "Linux Kernel"
90 * 0x001a0000-0x007d0000 : "File System"
91 * 0x007d0000-0x00800000 : "u-boot"
92 */
93
94#define DNS323_NOR_BOOT_BASE 0xf4000000
95#define DNS323_NOR_BOOT_SIZE SZ_8M
96
97static struct mtd_partition dns323_partitions[] = {
98 {
99 .name = "MTD1",
100 .size = 0x00010000,
101 .offset = 0,
102 }, {
103 .name = "MTD2",
104 .size = 0x00010000,
105 .offset = 0x00010000,
106 }, {
107 .name = "Linux Kernel",
108 .size = 0x00180000,
109 .offset = 0x00020000,
110 }, {
111 .name = "File System",
112 .size = 0x00630000,
113 .offset = 0x001A0000,
114 }, {
115 .name = "u-boot",
116 .size = 0x00030000,
117 .offset = 0x007d0000,
118 }
119};
120
121static struct physmap_flash_data dns323_nor_flash_data = {
122 .width = 1,
123 .parts = dns323_partitions,
124 .nr_parts = ARRAY_SIZE(dns323_partitions)
125};
126
127static struct resource dns323_nor_flash_resource = {
128 .flags = IORESOURCE_MEM,
129 .start = DNS323_NOR_BOOT_BASE,
130 .end = DNS323_NOR_BOOT_BASE + DNS323_NOR_BOOT_SIZE - 1,
131};
132
133static struct platform_device dns323_nor_flash = {
134 .name = "physmap-flash",
135 .id = 0,
136 .dev = { .platform_data = &dns323_nor_flash_data, },
137 .resource = &dns323_nor_flash_resource,
138 .num_resources = 1,
139};
140
141/****************************************************************************
142 * GPIO LEDs (simple - doesn't use hardware blinking support)
143 */
144
145static struct gpio_led dns323_leds[] = {
146 {
147 .name = "power:blue",
148 .gpio = DNS323_GPIO_LED_POWER,
149 .active_low = 1,
150 }, {
151 .name = "right:amber",
152 .gpio = DNS323_GPIO_LED_RIGHT_AMBER,
153 .active_low = 1,
154 }, {
155 .name = "left:amber",
156 .gpio = DNS323_GPIO_LED_LEFT_AMBER,
157 .active_low = 1,
158 },
159};
160
161static struct gpio_led_platform_data dns323_led_data = {
162 .num_leds = ARRAY_SIZE(dns323_leds),
163 .leds = dns323_leds,
164};
165
166static struct platform_device dns323_gpio_leds = {
167 .name = "leds-gpio",
168 .id = -1,
169 .dev = { .platform_data = &dns323_led_data, },
170};
171
172/****************************************************************************
173 * GPIO Attached Keys
174 */
175
176static struct gpio_keys_button dns323_buttons[] = {
177 {
178 .code = KEY_RESTART,
179 .gpio = DNS323_GPIO_KEY_RESET,
180 .desc = "Reset Button",
181 .active_low = 1,
182 },
183 {
184 .code = KEY_POWER,
185 .gpio = DNS323_GPIO_KEY_POWER,
186 .desc = "Power Button",
187 .active_low = 1,
188 }
189};
190
191static struct gpio_keys_platform_data dns323_button_data = {
192 .buttons = dns323_buttons,
193 .nbuttons = ARRAY_SIZE(dns323_buttons),
194};
195
196static struct platform_device dns323_button_device = {
197 .name = "gpio-keys",
198 .id = -1,
199 .num_resources = 0,
200 .dev = { .platform_data = &dns323_button_data, },
201};
202
203/****************************************************************************
204 * General Setup
205 */
206
207static struct platform_device *dns323_plat_devices[] __initdata = {
208 &dns323_nor_flash,
209 &dns323_gpio_leds,
210 &dns323_button_device,
211};
212
213/*
214 * On the DNS-323 the following devices are attached via I2C:
215 *
216 * i2c addr | chip | description
217 * 0x3e | GMT G760Af | fan speed PWM controller
218 * 0x48 | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
219 * 0x68 | ST M41T80 | RTC w/ alarm
220 */
221static struct i2c_board_info __initdata dns323_i2c_devices[] = {
222 {
223 I2C_BOARD_INFO("g760a", 0x3e),
224 .type = "g760a",
225 },
226#if 0
227 /* this entry requires the new-style driver model lm75 driver,
228 * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */
229 {
230 I2C_BOARD_INFO("lm75", 0x48),
231 .type = "g751",
232 },
233#endif
234 {
235 I2C_BOARD_INFO("rtc-m41t80", 0x68),
236 .type = "m41t80",
237 }
238};
239
240/* DNS-323 specific power off method */
241static void dns323_power_off(void)
242{
243 pr_info("%s: triggering power-off...\n", __func__);
244 gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
245}
246
247static void __init dns323_init(void)
248{
249 /* Setup basic Orion functions. Need to be called early. */
250 orion_init();
251
252 /* setup flash mapping
253 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
254 */
255 orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE,
256 DNS323_NOR_BOOT_SIZE, -1);
257
258 /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE
259 *
260 * Open a special address decode windows for the PCIE WA.
261 */
262 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
263 orion_write(ORION_REGS_BASE | 0x20070,
264 (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
265
266 /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
267 orion_write(MPP_0_7_CTRL, 0);
268 orion_write(MPP_8_15_CTRL, 0);
269 orion_write(MPP_16_19_CTRL, 0);
270 orion_write(MPP_DEV_CTRL, 0);
271
272 /* Define used GPIO pins
273
274 GPIO Map:
275
276 | 0 | | PEX_RST_OUT (not controlled by GPIO)
277 | 1 | Out | right amber LED (= sata ch0 LED) (low-active)
278 | 2 | Out | left amber LED (= sata ch1 LED) (low-active)
279 | 3 | Out | //unknown//
280 | 4 | Out | power button LED (low-active, together with pin #5)
281 | 5 | Out | power button LED (low-active, together with pin #4)
282 | 6 | In | GMT G751-2f overtemp. shutdown signal (low-active)
283 | 7 | In | M41T80 nIRQ/OUT/SQW signal
284 | 8 | Out | triggers power off (high-active)
285 | 9 | In | power button switch (low-active)
286 | 10 | In | reset button switch (low-active)
287 | 11 | Out | //unknown//
288 | 12 | Out | //unknown//
289 | 13 | Out | //unknown//
290 | 14 | Out | //unknown//
291 | 15 | Out | //unknown//
292 */
293 orion_gpio_set_valid_pins(0x07f6);
294
295 /* register dns323 specific power-off method */
296 if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0)
297 || (gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0))
298 pr_err("DNS323: failed to setup power-off GPIO\n");
299
300 pm_power_off = dns323_power_off;
301
302 /* register flash and other platform devices */
303 platform_add_devices(dns323_plat_devices,
304 ARRAY_SIZE(dns323_plat_devices));
305
306 i2c_register_board_info(0, dns323_i2c_devices,
307 ARRAY_SIZE(dns323_i2c_devices));
308
309 orion_eth_init(&dns323_eth_data);
310}
311
312/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
313MACHINE_START(DNS323, "D-Link DNS-323")
314 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
315 .phys_io = ORION_REGS_BASE,
316 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
317 .boot_params = 0x00000100,
318 .init_machine = dns323_init,
319 .map_io = orion_map_io,
320 .init_irq = orion_init_irq,
321 .timer = &orion_timer,
322MACHINE_END
diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion/gpio.c
new file mode 100644
index 000000000000..d5f00c86d616
--- /dev/null
+++ b/arch/arm/mach-orion/gpio.c
@@ -0,0 +1,225 @@
1/*
2 * arch/arm/mach-orion/gpio.c
3 *
4 * GPIO functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/spinlock.h>
17#include <linux/bitops.h>
18#include <asm/gpio.h>
19#include <asm/arch/orion.h>
20#include "common.h"
21
22static DEFINE_SPINLOCK(gpio_lock);
23static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
24static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */
25
26void __init orion_gpio_set_valid_pins(u32 pins)
27{
28 gpio_valid[0] = pins;
29}
30
31/*
32 * GENERIC_GPIO primitives
33 */
34int gpio_direction_input(unsigned pin)
35{
36 unsigned long flags;
37
38 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
39 pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
40 return -EINVAL;
41 }
42
43 spin_lock_irqsave(&gpio_lock, flags);
44
45 /*
46 * Some callers might have not used the gpio_request(),
47 * so flag this pin as requested now.
48 */
49 if (!gpio_label[pin])
50 gpio_label[pin] = "?";
51
52 orion_setbits(GPIO_IO_CONF, 1 << pin);
53
54 spin_unlock_irqrestore(&gpio_lock, flags);
55 return 0;
56}
57EXPORT_SYMBOL(gpio_direction_input);
58
59int gpio_direction_output(unsigned pin, int value)
60{
61 unsigned long flags;
62 int mask;
63
64 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
65 pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
66 return -EINVAL;
67 }
68
69 spin_lock_irqsave(&gpio_lock, flags);
70
71 /*
72 * Some callers might have not used the gpio_request(),
73 * so flag this pin as requested now.
74 */
75 if (!gpio_label[pin])
76 gpio_label[pin] = "?";
77
78 mask = 1 << pin;
79 orion_clrbits(GPIO_BLINK_EN, mask);
80 if (value)
81 orion_setbits(GPIO_OUT, mask);
82 else
83 orion_clrbits(GPIO_OUT, mask);
84 orion_clrbits(GPIO_IO_CONF, mask);
85
86 spin_unlock_irqrestore(&gpio_lock, flags);
87 return 0;
88}
89EXPORT_SYMBOL(gpio_direction_output);
90
91int gpio_get_value(unsigned pin)
92{
93 int val, mask = 1 << pin;
94
95 if (orion_read(GPIO_IO_CONF) & mask)
96 val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL);
97 else
98 val = orion_read(GPIO_OUT);
99
100 return val & mask;
101}
102EXPORT_SYMBOL(gpio_get_value);
103
104void gpio_set_value(unsigned pin, int value)
105{
106 unsigned long flags;
107 int mask = 1 << pin;
108
109 spin_lock_irqsave(&gpio_lock, flags);
110
111 orion_clrbits(GPIO_BLINK_EN, mask);
112 if (value)
113 orion_setbits(GPIO_OUT, mask);
114 else
115 orion_clrbits(GPIO_OUT, mask);
116
117 spin_unlock_irqrestore(&gpio_lock, flags);
118}
119EXPORT_SYMBOL(gpio_set_value);
120
121void orion_gpio_set_blink(unsigned pin, int blink)
122{
123 unsigned long flags;
124 int mask = 1 << pin;
125
126 spin_lock_irqsave(&gpio_lock, flags);
127
128 orion_clrbits(GPIO_OUT, mask);
129 if (blink)
130 orion_setbits(GPIO_BLINK_EN, mask);
131 else
132 orion_clrbits(GPIO_BLINK_EN, mask);
133
134 spin_unlock_irqrestore(&gpio_lock, flags);
135}
136EXPORT_SYMBOL(orion_gpio_set_blink);
137
138int gpio_request(unsigned pin, const char *label)
139{
140 int ret = 0;
141 unsigned long flags;
142
143 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
144 pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
145 return -EINVAL;
146 }
147
148 spin_lock_irqsave(&gpio_lock, flags);
149
150 if (gpio_label[pin]) {
151 pr_debug("%s: GPIO %d already used as %s\n",
152 __FUNCTION__, pin, gpio_label[pin]);
153 ret = -EBUSY;
154 } else
155 gpio_label[pin] = label ? label : "?";
156
157 spin_unlock_irqrestore(&gpio_lock, flags);
158 return ret;
159}
160EXPORT_SYMBOL(gpio_request);
161
162void gpio_free(unsigned pin)
163{
164 if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
165 pr_debug("%s: invalid GPIO %d\n", __FUNCTION__, pin);
166 return;
167 }
168
169 if (!gpio_label[pin])
170 pr_warning("%s: GPIO %d already freed\n", __FUNCTION__, pin);
171 else
172 gpio_label[pin] = NULL;
173}
174EXPORT_SYMBOL(gpio_free);
175
176/* Debug helper */
177void gpio_display(void)
178{
179 int i;
180
181 for (i = 0; i < GPIO_MAX; i++) {
182 printk(KERN_DEBUG "Pin-%d: ", i);
183
184 if (!test_bit(i, gpio_valid)) {
185 printk("non-GPIO\n");
186 } else if (!gpio_label[i]) {
187 printk("GPIO, free\n");
188 } else {
189 printk("GPIO, used by %s, ", gpio_label[i]);
190 if (orion_read(GPIO_IO_CONF) & (1 << i)) {
191 printk("input, active %s, level %s, edge %s\n",
192 ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
193 ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
194 ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
195 } else {
196 printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1);
197 }
198 }
199 }
200
201 printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n",
202 MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL));
203 printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n",
204 MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL));
205 printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n",
206 MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL));
207 printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n",
208 MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL));
209 printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n",
210 GPIO_OUT, orion_read(GPIO_OUT));
211 printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n",
212 GPIO_IO_CONF, orion_read(GPIO_IO_CONF));
213 printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n",
214 GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN));
215 printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n",
216 GPIO_IN_POL, orion_read(GPIO_IN_POL));
217 printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n",
218 GPIO_DATA_IN, orion_read(GPIO_DATA_IN));
219 printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n",
220 GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK));
221 printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n",
222 GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE));
223 printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n",
224 GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK));
225}
diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion/irq.c
new file mode 100644
index 000000000000..df7e12ad378b
--- /dev/null
+++ b/arch/arm/mach-orion/irq.c
@@ -0,0 +1,241 @@
1/*
2 * arch/arm/mach-orion/irq.c
3 *
4 * Core IRQ functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <asm/gpio.h>
17#include <asm/arch/orion.h>
18#include "common.h"
19
20/*****************************************************************************
21 * Orion GPIO IRQ
22 *
23 * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same
24 * value of the line or the opposite value.
25 *
26 * Level IRQ handlers: DATA_IN is used directly as cause register.
27 * Interrupt are masked by LEVEL_MASK registers.
28 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
29 * Interrupt are masked by EDGE_MASK registers.
30 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
31 * the polarity to catch the next line transaction.
32 * This is a race condition that might not perfectly
33 * work on some use cases.
34 *
35 * Every eight GPIO lines are grouped (OR'ed) before going up to main
36 * cause register.
37 *
38 * EDGE cause mask
39 * data-in /--------| |-----| |----\
40 * -----| |----- ---- to main cause reg
41 * X \----------------| |----/
42 * polarity LEVEL mask
43 *
44 ****************************************************************************/
45static void orion_gpio_irq_ack(u32 irq)
46{
47 int pin = irq_to_gpio(irq);
48 if (irq_desc[irq].status & IRQ_LEVEL)
49 /*
50 * Mask bit for level interrupt
51 */
52 orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
53 else
54 /*
55 * Clear casue bit for egde interrupt
56 */
57 orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
58}
59
60static void orion_gpio_irq_mask(u32 irq)
61{
62 int pin = irq_to_gpio(irq);
63 if (irq_desc[irq].status & IRQ_LEVEL)
64 orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
65 else
66 orion_clrbits(GPIO_EDGE_MASK, 1 << pin);
67}
68
69static void orion_gpio_irq_unmask(u32 irq)
70{
71 int pin = irq_to_gpio(irq);
72 if (irq_desc[irq].status & IRQ_LEVEL)
73 orion_setbits(GPIO_LEVEL_MASK, 1 << pin);
74 else
75 orion_setbits(GPIO_EDGE_MASK, 1 << pin);
76}
77
78static int orion_gpio_set_irq_type(u32 irq, u32 type)
79{
80 int pin = irq_to_gpio(irq);
81 struct irq_desc *desc;
82
83 if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
84 printk(KERN_ERR "orion_gpio_set_irq_type failed "
85 "(irq %d, pin %d).\n", irq, pin);
86 return -EINVAL;
87 }
88
89 desc = irq_desc + irq;
90
91 switch (type) {
92 case IRQT_HIGH:
93 desc->handle_irq = handle_level_irq;
94 desc->status |= IRQ_LEVEL;
95 orion_clrbits(GPIO_IN_POL, (1 << pin));
96 break;
97 case IRQT_LOW:
98 desc->handle_irq = handle_level_irq;
99 desc->status |= IRQ_LEVEL;
100 orion_setbits(GPIO_IN_POL, (1 << pin));
101 break;
102 case IRQT_RISING:
103 desc->handle_irq = handle_edge_irq;
104 desc->status &= ~IRQ_LEVEL;
105 orion_clrbits(GPIO_IN_POL, (1 << pin));
106 break;
107 case IRQT_FALLING:
108 desc->handle_irq = handle_edge_irq;
109 desc->status &= ~IRQ_LEVEL;
110 orion_setbits(GPIO_IN_POL, (1 << pin));
111 break;
112 case IRQT_BOTHEDGE:
113 desc->handle_irq = handle_edge_irq;
114 desc->status &= ~IRQ_LEVEL;
115 /*
116 * set initial polarity based on current input level
117 */
118 if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN))
119 & (1 << pin))
120 orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
121 else
122 orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
123
124 break;
125 default:
126 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
127 return -EINVAL;
128 }
129
130 desc->status &= ~IRQ_TYPE_SENSE_MASK;
131 desc->status |= type & IRQ_TYPE_SENSE_MASK;
132
133 return 0;
134}
135
136static struct irq_chip orion_gpio_irq_chip = {
137 .name = "Orion-IRQ-GPIO",
138 .ack = orion_gpio_irq_ack,
139 .mask = orion_gpio_irq_mask,
140 .unmask = orion_gpio_irq_unmask,
141 .set_type = orion_gpio_set_irq_type,
142};
143
144static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
145{
146 u32 cause, offs, pin;
147
148 BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31);
149 offs = (irq - IRQ_ORION_GPIO_0_7) * 8;
150 cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) |
151 (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK));
152
153 for (pin = offs; pin < offs + 8; pin++) {
154 if (cause & (1 << pin)) {
155 irq = gpio_to_irq(pin);
156 desc = irq_desc + irq;
157 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
158 /* Swap polarity (race with GPIO line) */
159 u32 polarity = orion_read(GPIO_IN_POL);
160 polarity ^= 1 << pin;
161 orion_write(GPIO_IN_POL, polarity);
162 }
163 desc_handle_irq(irq, desc);
164 }
165 }
166}
167
168static void __init orion_init_gpio_irq(void)
169{
170 int i;
171 struct irq_desc *desc;
172
173 /*
174 * Mask and clear GPIO IRQ interrupts
175 */
176 orion_write(GPIO_LEVEL_MASK, 0x0);
177 orion_write(GPIO_EDGE_MASK, 0x0);
178 orion_write(GPIO_EDGE_CAUSE, 0x0);
179
180 /*
181 * Register chained level handlers for GPIO IRQs by default.
182 * User can use set_type() if he wants to use edge types handlers.
183 */
184 for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) {
185 set_irq_chip(i, &orion_gpio_irq_chip);
186 set_irq_handler(i, handle_level_irq);
187 desc = irq_desc + i;
188 desc->status |= IRQ_LEVEL;
189 set_irq_flags(i, IRQF_VALID);
190 }
191 set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler);
192 set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler);
193 set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler);
194 set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler);
195}
196
197/*****************************************************************************
198 * Orion Main IRQ
199 ****************************************************************************/
200static void orion_main_irq_mask(u32 irq)
201{
202 orion_clrbits(MAIN_IRQ_MASK, 1 << irq);
203}
204
205static void orion_main_irq_unmask(u32 irq)
206{
207 orion_setbits(MAIN_IRQ_MASK, 1 << irq);
208}
209
210static struct irq_chip orion_main_irq_chip = {
211 .name = "Orion-IRQ-Main",
212 .ack = orion_main_irq_mask,
213 .mask = orion_main_irq_mask,
214 .unmask = orion_main_irq_unmask,
215};
216
217static void __init orion_init_main_irq(void)
218{
219 int i;
220
221 /*
222 * Mask and clear Main IRQ interrupts
223 */
224 orion_write(MAIN_IRQ_MASK, 0x0);
225 orion_write(MAIN_IRQ_CAUSE, 0x0);
226
227 /*
228 * Register level handler for Main IRQs
229 */
230 for (i = 0; i < IRQ_ORION_GPIO_START; i++) {
231 set_irq_chip(i, &orion_main_irq_chip);
232 set_irq_handler(i, handle_level_irq);
233 set_irq_flags(i, IRQF_VALID);
234 }
235}
236
237void __init orion_init_irq(void)
238{
239 orion_init_main_irq();
240 orion_init_gpio_irq();
241}
diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion/kurobox_pro-setup.c
new file mode 100644
index 000000000000..2d812ed6b5c7
--- /dev/null
+++ b/arch/arm/mach-orion/kurobox_pro-setup.c
@@ -0,0 +1,234 @@
1/*
2 * arch/arm/mach-orion/kurobox_pro-setup.c
3 *
4 * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/pci.h>
15#include <linux/irq.h>
16#include <linux/mtd/physmap.h>
17#include <linux/mtd/nand.h>
18#include <linux/mv643xx_eth.h>
19#include <linux/i2c.h>
20#include <asm/mach-types.h>
21#include <asm/gpio.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/pci.h>
24#include <asm/arch/orion.h>
25#include <asm/arch/platform.h>
26#include "common.h"
27
28/*****************************************************************************
29 * KUROBOX-PRO Info
30 ****************************************************************************/
31
32/*
33 * 256K NOR flash Device bus boot chip select
34 */
35
36#define KUROBOX_PRO_NOR_BOOT_BASE 0xf4000000
37#define KUROBOX_PRO_NOR_BOOT_SIZE SZ_256K
38
39/*
40 * 256M NAND flash on Device bus chip select 1
41 */
42
43#define KUROBOX_PRO_NAND_BASE 0xfc000000
44#define KUROBOX_PRO_NAND_SIZE SZ_2M
45
46/*****************************************************************************
47 * 256MB NAND Flash on Device bus CS0
48 ****************************************************************************/
49
50static struct mtd_partition kurobox_pro_nand_parts[] = {
51 {
52 .name = "uImage",
53 .offset = 0,
54 .size = SZ_4M,
55 },
56 {
57 .name = "rootfs",
58 .offset = SZ_4M,
59 .size = SZ_64M,
60 },
61 {
62 .name = "extra",
63 .offset = SZ_4M + SZ_64M,
64 .size = SZ_256M - (SZ_4M + SZ_64M),
65 },
66};
67
68static struct resource kurobox_pro_nand_resource = {
69 .flags = IORESOURCE_MEM,
70 .start = KUROBOX_PRO_NAND_BASE,
71 .end = KUROBOX_PRO_NAND_BASE + KUROBOX_PRO_NAND_SIZE - 1,
72};
73
74static struct orion_nand_data kurobox_pro_nand_data = {
75 .parts = kurobox_pro_nand_parts,
76 .nr_parts = ARRAY_SIZE(kurobox_pro_nand_parts),
77 .cle = 0,
78 .ale = 1,
79 .width = 8,
80};
81
82static struct platform_device kurobox_pro_nand_flash = {
83 .name = "orion_nand",
84 .id = -1,
85 .dev = {
86 .platform_data = &kurobox_pro_nand_data,
87 },
88 .resource = &kurobox_pro_nand_resource,
89 .num_resources = 1,
90};
91
92/*****************************************************************************
93 * 256KB NOR Flash on BOOT Device
94 ****************************************************************************/
95
96static struct physmap_flash_data kurobox_pro_nor_flash_data = {
97 .width = 1,
98};
99
100static struct resource kurobox_pro_nor_flash_resource = {
101 .flags = IORESOURCE_MEM,
102 .start = KUROBOX_PRO_NOR_BOOT_BASE,
103 .end = KUROBOX_PRO_NOR_BOOT_BASE + KUROBOX_PRO_NOR_BOOT_SIZE - 1,
104};
105
106static struct platform_device kurobox_pro_nor_flash = {
107 .name = "physmap-flash",
108 .id = 0,
109 .dev = {
110 .platform_data = &kurobox_pro_nor_flash_data,
111 },
112 .num_resources = 1,
113 .resource = &kurobox_pro_nor_flash_resource,
114};
115
116/*****************************************************************************
117 * PCI
118 ****************************************************************************/
119
120static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
121{
122 /*
123 * PCI isn't used on the Kuro
124 */
125 if (dev->bus->number == orion_pcie_local_bus_nr())
126 return IRQ_ORION_PCIE0_INT;
127 else
128 printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n");
129
130 return -1;
131}
132
133static struct hw_pci kurobox_pro_pci __initdata = {
134 .nr_controllers = 1,
135 .swizzle = pci_std_swizzle,
136 .setup = orion_pci_sys_setup,
137 .scan = orion_pci_sys_scan_bus,
138 .map_irq = kurobox_pro_pci_map_irq,
139};
140
141static int __init kurobox_pro_pci_init(void)
142{
143 if (machine_is_kurobox_pro())
144 pci_common_init(&kurobox_pro_pci);
145
146 return 0;
147}
148
149subsys_initcall(kurobox_pro_pci_init);
150
151/*****************************************************************************
152 * Ethernet
153 ****************************************************************************/
154
155static struct mv643xx_eth_platform_data kurobox_pro_eth_data = {
156 .phy_addr = 8,
157 .force_phy_addr = 1,
158};
159
160/*****************************************************************************
161 * RTC 5C372a on I2C bus
162 ****************************************************************************/
163static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = {
164 .driver_name = "rtc-rs5c372",
165 .type = "rs5c372a",
166 .addr = 0x32,
167};
168
169/*****************************************************************************
170 * General Setup
171 ****************************************************************************/
172
173static struct platform_device *kurobox_pro_devices[] __initdata = {
174 &kurobox_pro_nor_flash,
175 &kurobox_pro_nand_flash,
176};
177
178static void __init kurobox_pro_init(void)
179{
180 /*
181 * Setup basic Orion functions. Need to be called early.
182 */
183 orion_init();
184
185 /*
186 * Setup the CPU address decode windows for our devices
187 */
188 orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE,
189 KUROBOX_PRO_NOR_BOOT_SIZE, -1);
190 orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE,
191 KUROBOX_PRO_NAND_SIZE, -1);
192 /*
193 * Open a special address decode windows for the PCIE WA.
194 */
195 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
196 orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
197 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
198
199 /*
200 * Setup Multiplexing Pins --
201 * MPP[0-1] Not used
202 * MPP[2] GPIO Micon
203 * MPP[3] GPIO RTC
204 * MPP[4-5] Not used
205 * MPP[6] Nand Flash REn
206 * MPP[7] Nand Flash WEn
207 * MPP[8-11] Not used
208 * MPP[12] SATA 0 presence Indication
209 * MPP[13] SATA 1 presence Indication
210 * MPP[14] SATA 0 active Indication
211 * MPP[15] SATA 1 active indication
212 * MPP[16-19] Not used
213 */
214 orion_write(MPP_0_7_CTRL, 0x44220003);
215 orion_write(MPP_8_15_CTRL, 0x55550000);
216 orion_write(MPP_16_19_CTRL, 0x0);
217
218 orion_gpio_set_valid_pins(0x0000000c);
219
220 platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices));
221 i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
222 orion_eth_init(&kurobox_pro_eth_data);
223}
224
225MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
226 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
227 .phys_io = ORION_REGS_BASE,
228 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
229 .boot_params = 0x00000100,
230 .init_machine = kurobox_pro_init,
231 .map_io = orion_map_io,
232 .init_irq = orion_init_irq,
233 .timer = &orion_timer,
234MACHINE_END
diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c
new file mode 100644
index 000000000000..0498d7c69b30
--- /dev/null
+++ b/arch/arm/mach-orion/pci.c
@@ -0,0 +1,557 @@
1/*
2 * arch/arm/mach-orion/pci.c
3 *
4 * PCI and PCIE functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <asm/mach/pci.h>
16#include "common.h"
17
18/*****************************************************************************
19 * Orion has one PCIE controller and one PCI controller.
20 *
21 * Note1: The local PCIE bus number is '0'. The local PCI bus number
22 * follows the scanned PCIE bridged busses, if any.
23 *
24 * Note2: It is possible for PCI/PCIE agents to access many subsystem's
25 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
26 * device bus, Orion registers, etc. However this code only enable the
27 * access to DDR banks.
28 ****************************************************************************/
29
30
31/*****************************************************************************
32 * PCIE controller
33 ****************************************************************************/
34#define PCIE_CTRL ORION_PCIE_REG(0x1a00)
35#define PCIE_STAT ORION_PCIE_REG(0x1a04)
36#define PCIE_DEV_ID ORION_PCIE_REG(0x0000)
37#define PCIE_CMD_STAT ORION_PCIE_REG(0x0004)
38#define PCIE_DEV_REV ORION_PCIE_REG(0x0008)
39#define PCIE_MASK ORION_PCIE_REG(0x1910)
40#define PCIE_CONF_ADDR ORION_PCIE_REG(0x18f8)
41#define PCIE_CONF_DATA ORION_PCIE_REG(0x18fc)
42
43/*
44 * PCIE_STAT bits
45 */
46#define PCIE_STAT_LINK_DOWN 1
47#define PCIE_STAT_BUS_OFFS 8
48#define PCIE_STAT_BUS_MASK (0xff << PCIE_STAT_BUS_OFFS)
49#define PCIE_STAT_DEV_OFFS 20
50#define PCIE_STAT_DEV_MASK (0x1f << PCIE_STAT_DEV_OFFS)
51
52/*
53 * PCIE_CONF_ADDR bits
54 */
55#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 24) | ((r) & 0xfc))
56#define PCIE_CONF_FUNC(f) (((f) & 0x3) << 8)
57#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
58#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
59#define PCIE_CONF_ADDR_EN (1 << 31)
60
61/*
62 * PCIE config cycles are done by programming the PCIE_CONF_ADDR register
63 * and then reading the PCIE_CONF_DATA register. Need to make sure these
64 * transactions are atomic.
65 */
66static DEFINE_SPINLOCK(orion_pcie_lock);
67
68void orion_pcie_id(u32 *dev, u32 *rev)
69{
70 *dev = orion_read(PCIE_DEV_ID) >> 16;
71 *rev = orion_read(PCIE_DEV_REV) & 0xff;
72}
73
74u32 orion_pcie_local_bus_nr(void)
75{
76 u32 stat = orion_read(PCIE_STAT);
77 return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS);
78}
79
80static u32 orion_pcie_local_dev_nr(void)
81{
82 u32 stat = orion_read(PCIE_STAT);
83 return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS);
84}
85
86static u32 orion_pcie_no_link(void)
87{
88 u32 stat = orion_read(PCIE_STAT);
89 return(stat & PCIE_STAT_LINK_DOWN);
90}
91
92static void orion_pcie_set_bus_nr(int nr)
93{
94 orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK);
95 orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS);
96}
97
98static void orion_pcie_master_slave_enable(void)
99{
100 orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER |
101 PCI_COMMAND_IO |
102 PCI_COMMAND_MEMORY);
103}
104
105static void orion_pcie_enable_interrupts(void)
106{
107 /*
108 * Enable interrupts lines
109 * INTA[24] INTB[25] INTC[26] INTD[27]
110 */
111 orion_setbits(PCIE_MASK, 0xf<<24);
112}
113
114static int orion_pcie_valid_config(u32 bus, u32 dev)
115{
116 /*
117 * Don't go out when trying to access --
118 * 1. our own device
119 * 2. where there's no device connected (no link)
120 * 3. nonexisting devices on local bus
121 */
122
123 if ((orion_pcie_local_bus_nr() == bus) &&
124 (orion_pcie_local_dev_nr() == dev))
125 return 0;
126
127 if (orion_pcie_no_link())
128 return 0;
129
130 if (bus == orion_pcie_local_bus_nr())
131 if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) ||
132 ((orion_pcie_local_dev_nr() != 0) && (dev != 0)))
133 return 0;
134
135 return 1;
136}
137
138static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
139 int size, u32 *val)
140{
141 unsigned long flags;
142 unsigned int dev, rev, pcie_addr;
143
144 if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
145 *val = 0xffffffff;
146 return PCIBIOS_DEVICE_NOT_FOUND;
147 }
148
149 spin_lock_irqsave(&orion_pcie_lock, flags);
150
151 orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
152 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
153 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
154 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
155
156 orion_pcie_id(&dev, &rev);
157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 /* extended register space */
159 pcie_addr = ORION_PCIE_WA_BASE;
160 pcie_addr |= PCIE_CONF_BUS(bus->number) |
161 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
162 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
163 PCIE_CONF_REG(where);
164 *val = orion_read(pcie_addr);
165 } else
166 *val = orion_read(PCIE_CONF_DATA);
167
168 if (size == 1)
169 *val = (*val >> (8*(where & 0x3))) & 0xff;
170 else if (size == 2)
171 *val = (*val >> (8*(where & 0x3))) & 0xffff;
172
173 spin_unlock_irqrestore(&orion_pcie_lock, flags);
174
175 return PCIBIOS_SUCCESSFUL;
176}
177
178
179static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where,
180 int size, u32 val)
181{
182 unsigned long flags;
183 int ret;
184
185 if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
186 return PCIBIOS_DEVICE_NOT_FOUND;
187
188 spin_lock_irqsave(&orion_pcie_lock, flags);
189
190 ret = PCIBIOS_SUCCESSFUL;
191
192 orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
193 PCIE_CONF_DEV(PCI_SLOT(devfn)) |
194 PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
195 PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
196
197 if (size == 4) {
198 __raw_writel(val, PCIE_CONF_DATA);
199 } else if (size == 2) {
200 __raw_writew(val, PCIE_CONF_DATA + (where & 0x3));
201 } else if (size == 1) {
202 __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3));
203 } else {
204 ret = PCIBIOS_BAD_REGISTER_NUMBER;
205 }
206
207 spin_unlock_irqrestore(&orion_pcie_lock, flags);
208
209 return ret;
210}
211
212struct pci_ops orion_pcie_ops = {
213 .read = orion_pcie_rd_conf,
214 .write = orion_pcie_wr_conf,
215};
216
217
218static int orion_pcie_setup(struct pci_sys_data *sys)
219{
220 struct resource *res;
221
222 /*
223 * Master + Slave enable
224 */
225 orion_pcie_master_slave_enable();
226
227 /*
228 * Enable interrupts lines A-D
229 */
230 orion_pcie_enable_interrupts();
231
232 /*
233 * Request resource
234 */
235 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
236 if (!res)
237 panic("orion_pci_setup unable to alloc resources");
238
239 /*
240 * IORESOURCE_IO
241 */
242 res[0].name = "PCI-EX I/O Space";
243 res[0].flags = IORESOURCE_IO;
244 res[0].start = ORION_PCIE_IO_REMAP;
245 res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
246 if (request_resource(&ioport_resource, &res[0]))
247 panic("Request PCIE IO resource failed\n");
248 sys->resource[0] = &res[0];
249
250 /*
251 * IORESOURCE_MEM
252 */
253 res[1].name = "PCI-EX Memory Space";
254 res[1].flags = IORESOURCE_MEM;
255 res[1].start = ORION_PCIE_MEM_BASE;
256 res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
257 if (request_resource(&iomem_resource, &res[1]))
258 panic("Request PCIE Memory resource failed\n");
259 sys->resource[1] = &res[1];
260
261 sys->resource[2] = NULL;
262 sys->io_offset = 0;
263
264 return 1;
265}
266
267/*****************************************************************************
268 * PCI controller
269 ****************************************************************************/
270#define PCI_MODE ORION_PCI_REG(0xd00)
271#define PCI_CMD ORION_PCI_REG(0xc00)
272#define PCI_P2P_CONF ORION_PCI_REG(0x1d14)
273#define PCI_CONF_ADDR ORION_PCI_REG(0xc78)
274#define PCI_CONF_DATA ORION_PCI_REG(0xc7c)
275
276/*
277 * PCI_MODE bits
278 */
279#define PCI_MODE_64BIT (1 << 2)
280#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
281
282/*
283 * PCI_CMD bits
284 */
285#define PCI_CMD_HOST_REORDER (1 << 29)
286
287/*
288 * PCI_P2P_CONF bits
289 */
290#define PCI_P2P_BUS_OFFS 16
291#define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
292#define PCI_P2P_DEV_OFFS 24
293#define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
294
295/*
296 * PCI_CONF_ADDR bits
297 */
298#define PCI_CONF_REG(reg) ((reg) & 0xfc)
299#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
300#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
301#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
302#define PCI_CONF_ADDR_EN (1 << 31)
303
304/*
305 * Internal configuration space
306 */
307#define PCI_CONF_FUNC_STAT_CMD 0
308#define PCI_CONF_REG_STAT_CMD 4
309#define PCIX_STAT 0x64
310#define PCIX_STAT_BUS_OFFS 8
311#define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
312
313/*
314 * PCI config cycles are done by programming the PCI_CONF_ADDR register
315 * and then reading the PCI_CONF_DATA register. Need to make sure these
316 * transactions are atomic.
317 */
318static DEFINE_SPINLOCK(orion_pci_lock);
319
320u32 orion_pci_local_bus_nr(void)
321{
322 u32 conf = orion_read(PCI_P2P_CONF);
323 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
324}
325
326u32 orion_pci_local_dev_nr(void)
327{
328 u32 conf = orion_read(PCI_P2P_CONF);
329 return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS);
330}
331
332int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
333 u32 where, u32 size, u32 *val)
334{
335 unsigned long flags;
336 spin_lock_irqsave(&orion_pci_lock, flags);
337
338 orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
339 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
340 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
341
342 *val = orion_read(PCI_CONF_DATA);
343
344 if (size == 1)
345 *val = (*val >> (8*(where & 0x3))) & 0xff;
346 else if (size == 2)
347 *val = (*val >> (8*(where & 0x3))) & 0xffff;
348
349 spin_unlock_irqrestore(&orion_pci_lock, flags);
350
351 return PCIBIOS_SUCCESSFUL;
352}
353
354int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
355 u32 where, u32 size, u32 val)
356{
357 unsigned long flags;
358 int ret = PCIBIOS_SUCCESSFUL;
359
360 spin_lock_irqsave(&orion_pci_lock, flags);
361
362 orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
363 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
364 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
365
366 if (size == 4) {
367 __raw_writel(val, PCI_CONF_DATA);
368 } else if (size == 2) {
369 __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
370 } else if (size == 1) {
371 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
372 } else {
373 ret = PCIBIOS_BAD_REGISTER_NUMBER;
374 }
375
376 spin_unlock_irqrestore(&orion_pci_lock, flags);
377
378 return ret;
379}
380
381static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn,
382 int where, int size, u32 *val)
383{
384 /*
385 * Don't go out for local device
386 */
387 if ((orion_pci_local_bus_nr() == bus->number) &&
388 (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) {
389 *val = 0xffffffff;
390 return PCIBIOS_DEVICE_NOT_FOUND;
391 }
392
393 return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
394 PCI_FUNC(devfn), where, size, val);
395}
396
397static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
398 int where, int size, u32 val)
399{
400 /*
401 * Don't go out for local device
402 */
403 if ((orion_pci_local_bus_nr() == bus->number) &&
404 (orion_pci_local_dev_nr() == PCI_SLOT(devfn)))
405 return PCIBIOS_DEVICE_NOT_FOUND;
406
407 return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
408 PCI_FUNC(devfn), where, size, val);
409}
410
411struct pci_ops orion_pci_ops = {
412 .read = orion_pci_rd_conf,
413 .write = orion_pci_wr_conf,
414};
415
416static void orion_pci_set_bus_nr(int nr)
417{
418 u32 p2p = orion_read(PCI_P2P_CONF);
419
420 if (orion_read(PCI_MODE) & PCI_MODE_PCIX) {
421 /*
422 * PCI-X mode
423 */
424 u32 pcix_status, bus, dev;
425 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
426 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
427 orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
428 pcix_status &= ~PCIX_STAT_BUS_MASK;
429 pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
430 orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
431 } else {
432 /*
433 * PCI Conventional mode
434 */
435 p2p &= ~PCI_P2P_BUS_MASK;
436 p2p |= (nr << PCI_P2P_BUS_OFFS);
437 orion_write(PCI_P2P_CONF, p2p);
438 }
439}
440
441static void orion_pci_master_slave_enable(void)
442{
443 u32 bus_nr, dev_nr, func, reg, val;
444
445 bus_nr = orion_pci_local_bus_nr();
446 dev_nr = orion_pci_local_dev_nr();
447 func = PCI_CONF_FUNC_STAT_CMD;
448 reg = PCI_CONF_REG_STAT_CMD;
449 orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val);
450 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
451 orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7);
452}
453
454static int orion_pci_setup(struct pci_sys_data *sys)
455{
456 struct resource *res;
457
458 /*
459 * Master + Slave enable
460 */
461 orion_pci_master_slave_enable();
462
463 /*
464 * Force ordering
465 */
466 orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
467
468 /*
469 * Request resources
470 */
471 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
472 if (!res)
473 panic("orion_pci_setup unable to alloc resources");
474
475 /*
476 * IORESOURCE_IO
477 */
478 res[0].name = "PCI I/O Space";
479 res[0].flags = IORESOURCE_IO;
480 res[0].start = ORION_PCI_IO_REMAP;
481 res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
482 if (request_resource(&ioport_resource, &res[0]))
483 panic("Request PCI IO resource failed\n");
484 sys->resource[0] = &res[0];
485
486 /*
487 * IORESOURCE_MEM
488 */
489 res[1].name = "PCI Memory Space";
490 res[1].flags = IORESOURCE_MEM;
491 res[1].start = ORION_PCI_MEM_BASE;
492 res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
493 if (request_resource(&iomem_resource, &res[1]))
494 panic("Request PCI Memory resource failed\n");
495 sys->resource[1] = &res[1];
496
497 sys->resource[2] = NULL;
498 sys->io_offset = 0;
499
500 return 1;
501}
502
503
504/*****************************************************************************
505 * General PCIE + PCI
506 ****************************************************************************/
507int orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
508{
509 int ret = 0;
510
511 if (nr == 0) {
512 /*
513 * PCIE setup
514 */
515 orion_pcie_set_bus_nr(0);
516 ret = orion_pcie_setup(sys);
517 } else if (nr == 1) {
518 /*
519 * PCI setup
520 */
521 ret = orion_pci_setup(sys);
522 }
523
524 return ret;
525}
526
527struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
528{
529 struct pci_ops *ops;
530 struct pci_bus *bus;
531
532
533 if (nr == 0) {
534 u32 pci_bus;
535 /*
536 * PCIE scan
537 */
538 ops = &orion_pcie_ops;
539 bus = pci_scan_bus(sys->busnr, ops, sys);
540 /*
541 * Set local PCI bus number to follow PCIE bridges (if any)
542 */
543 pci_bus = bus->number + bus->subordinate - bus->secondary + 1;
544 orion_pci_set_bus_nr(pci_bus);
545 } else if (nr == 1) {
546 /*
547 * PCI scan
548 */
549 ops = &orion_pci_ops;
550 bus = pci_scan_bus(sys->busnr, ops, sys);
551 } else {
552 BUG();
553 bus = NULL;
554 }
555
556 return bus;
557}
diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion/rd88f5182-setup.c
new file mode 100644
index 000000000000..026d74325d01
--- /dev/null
+++ b/arch/arm/mach-orion/rd88f5182-setup.c
@@ -0,0 +1,306 @@
1/*
2 * arch/arm/mach-orion/rd88f5182-setup.c
3 *
4 * Marvell Orion-NAS Reference Design Setup
5 *
6 * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/pci.h>
17#include <linux/irq.h>
18#include <linux/mtd/physmap.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/i2c.h>
21#include <asm/mach-types.h>
22#include <asm/gpio.h>
23#include <asm/leds.h>
24#include <asm/mach/arch.h>
25#include <asm/mach/pci.h>
26#include <asm/arch/orion.h>
27#include <asm/arch/platform.h>
28#include "common.h"
29
30/*****************************************************************************
31 * RD-88F5182 Info
32 ****************************************************************************/
33
34/*
35 * 512K NOR flash Device bus boot chip select
36 */
37
38#define RD88F5182_NOR_BOOT_BASE 0xf4000000
39#define RD88F5182_NOR_BOOT_SIZE SZ_512K
40
41/*
42 * 16M NOR flash on Device bus chip select 1
43 */
44
45#define RD88F5182_NOR_BASE 0xfc000000
46#define RD88F5182_NOR_SIZE SZ_16M
47
48/*
49 * PCI
50 */
51
52#define RD88F5182_PCI_SLOT0_OFFS 7
53#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
54#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
55
56/*
57 * GPIO Debug LED
58 */
59
60#define RD88F5182_GPIO_DBG_LED 0
61
62/*****************************************************************************
63 * 16M NOR Flash on Device bus CS1
64 ****************************************************************************/
65
66static struct physmap_flash_data rd88f5182_nor_flash_data = {
67 .width = 1,
68};
69
70static struct resource rd88f5182_nor_flash_resource = {
71 .flags = IORESOURCE_MEM,
72 .start = RD88F5182_NOR_BASE,
73 .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
74};
75
76static struct platform_device rd88f5182_nor_flash = {
77 .name = "physmap-flash",
78 .id = 0,
79 .dev = {
80 .platform_data = &rd88f5182_nor_flash_data,
81 },
82 .num_resources = 1,
83 .resource = &rd88f5182_nor_flash_resource,
84};
85
86#ifdef CONFIG_LEDS
87
88/*****************************************************************************
89 * Use GPIO debug led as CPU active indication
90 ****************************************************************************/
91
92static void rd88f5182_dbgled_event(led_event_t evt)
93{
94 int val;
95
96 if (evt == led_idle_end)
97 val = 1;
98 else if (evt == led_idle_start)
99 val = 0;
100 else
101 return;
102
103 gpio_set_value(RD88F5182_GPIO_DBG_LED, val);
104}
105
106static int __init rd88f5182_dbgled_init(void)
107{
108 int pin;
109
110 if (machine_is_rd88f5182()) {
111 pin = RD88F5182_GPIO_DBG_LED;
112
113 if (gpio_request(pin, "DBGLED") == 0) {
114 if (gpio_direction_output(pin, 0) != 0) {
115 printk(KERN_ERR "rd88f5182_dbgled_init failed "
116 "to set output pin %d\n", pin);
117 gpio_free(pin);
118 return 0;
119 }
120 } else {
121 printk(KERN_ERR "rd88f5182_dbgled_init failed "
122 "to request gpio %d\n", pin);
123 return 0;
124 }
125
126 leds_event = rd88f5182_dbgled_event;
127 }
128 return 0;
129}
130
131__initcall(rd88f5182_dbgled_init);
132
133#endif
134
135/*****************************************************************************
136 * PCI
137 ****************************************************************************/
138
139void __init rd88f5182_pci_preinit(void)
140{
141 int pin;
142
143 /*
144 * Configure PCI GPIO IRQ pins
145 */
146 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
147 if (gpio_request(pin, "PCI IntA") == 0) {
148 if (gpio_direction_input(pin) == 0) {
149 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
150 } else {
151 printk(KERN_ERR "rd88f5182_pci_preinit faield to "
152 "set_irq_type pin %d\n", pin);
153 gpio_free(pin);
154 }
155 } else {
156 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
157 }
158
159 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
160 if (gpio_request(pin, "PCI IntB") == 0) {
161 if (gpio_direction_input(pin) == 0) {
162 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
163 } else {
164 printk(KERN_ERR "rd88f5182_pci_preinit faield to "
165 "set_irq_type pin %d\n", pin);
166 gpio_free(pin);
167 }
168 } else {
169 printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
170 }
171}
172
173static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
174{
175 /*
176 * PCI-E isn't used on the RD2
177 */
178 if (dev->bus->number == orion_pcie_local_bus_nr())
179 return IRQ_ORION_PCIE0_INT;
180
181 /*
182 * PCI IRQs are connected via GPIOs
183 */
184 switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
185 case 0:
186 if (pin == 1)
187 return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
188 else
189 return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
190 default:
191 return -1;
192 }
193}
194
195static struct hw_pci rd88f5182_pci __initdata = {
196 .nr_controllers = 2,
197 .preinit = rd88f5182_pci_preinit,
198 .swizzle = pci_std_swizzle,
199 .setup = orion_pci_sys_setup,
200 .scan = orion_pci_sys_scan_bus,
201 .map_irq = rd88f5182_pci_map_irq,
202};
203
204static int __init rd88f5182_pci_init(void)
205{
206 if (machine_is_rd88f5182())
207 pci_common_init(&rd88f5182_pci);
208
209 return 0;
210}
211
212subsys_initcall(rd88f5182_pci_init);
213
214/*****************************************************************************
215 * Ethernet
216 ****************************************************************************/
217
218static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
219 .phy_addr = 8,
220 .force_phy_addr = 1,
221};
222
223/*****************************************************************************
224 * RTC DS1338 on I2C bus
225 ****************************************************************************/
226static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
227 .driver_name = "rtc-ds1307",
228 .type = "ds1338",
229 .addr = 0x68,
230};
231
232/*****************************************************************************
233 * General Setup
234 ****************************************************************************/
235
236static struct platform_device *rd88f5182_devices[] __initdata = {
237 &rd88f5182_nor_flash,
238};
239
240static void __init rd88f5182_init(void)
241{
242 /*
243 * Setup basic Orion functions. Need to be called early.
244 */
245 orion_init();
246
247 /*
248 * Setup the CPU address decode windows for our devices
249 */
250 orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE,
251 RD88F5182_NOR_BOOT_SIZE, -1);
252 orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE,
253 RD88F5182_NOR_SIZE, -1);
254
255 /*
256 * Open a special address decode windows for the PCIE WA.
257 */
258 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
259 orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
260 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
261
262 /*
263 * Setup Multiplexing Pins --
264 * MPP[0] Debug Led (GPIO - Out)
265 * MPP[1] Debug Led (GPIO - Out)
266 * MPP[2] N/A
267 * MPP[3] RTC_Int (GPIO - In)
268 * MPP[4] GPIO
269 * MPP[5] GPIO
270 * MPP[6] PCI_intA (GPIO - In)
271 * MPP[7] PCI_intB (GPIO - In)
272 * MPP[8-11] N/A
273 * MPP[12] SATA 0 presence Indication
274 * MPP[13] SATA 1 presence Indication
275 * MPP[14] SATA 0 active Indication
276 * MPP[15] SATA 1 active indication
277 * MPP[16-19] Not used
278 * MPP[20] PCI Clock to MV88F5182
279 * MPP[21] PCI Clock to mini PCI CON11
280 * MPP[22] USB 0 over current indication
281 * MPP[23] USB 1 over current indication
282 * MPP[24] USB 1 over current enable
283 * MPP[25] USB 0 over current enable
284 */
285
286 orion_write(MPP_0_7_CTRL, 0x00000003);
287 orion_write(MPP_8_15_CTRL, 0x55550000);
288 orion_write(MPP_16_19_CTRL, 0x5555);
289
290 orion_gpio_set_valid_pins(0x000000fb);
291
292 platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
293 i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
294 orion_eth_init(&rd88f5182_eth_data);
295}
296
297MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
298 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
299 .phys_io = ORION_REGS_BASE,
300 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
301 .boot_params = 0x00000100,
302 .init_machine = rd88f5182_init,
303 .map_io = orion_map_io,
304 .init_irq = orion_init_irq,
305 .timer = &orion_timer,
306MACHINE_END
diff --git a/arch/arm/mach-orion/time.c b/arch/arm/mach-orion/time.c
new file mode 100644
index 000000000000..bd4262da4f40
--- /dev/null
+++ b/arch/arm/mach-orion/time.c
@@ -0,0 +1,181 @@
1/*
2 * arch/arm/mach-orion/time.c
3 *
4 * Core time functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/clockchips.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <asm/mach/time.h>
18#include <asm/arch/orion.h>
19#include "common.h"
20
21/*
22 * Timer0: clock_event_device, Tick.
23 * Timer1: clocksource, Free running.
24 * WatchDog: Not used.
25 *
26 * Timers are counting down.
27 */
28#define CLOCKEVENT 0
29#define CLOCKSOURCE 1
30
31/*
32 * Timers bits
33 */
34#define BRIDGE_INT_TIMER(x) (1 << ((x) + 1))
35#define TIMER_EN(x) (1 << ((x) * 2))
36#define TIMER_RELOAD_EN(x) (1 << (((x) * 2) + 1))
37#define BRIDGE_INT_TIMER_WD (1 << 3)
38#define TIMER_WD_EN (1 << 4)
39#define TIMER_WD_RELOAD_EN (1 << 5)
40
41static cycle_t orion_clksrc_read(void)
42{
43 return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE)));
44}
45
46static struct clocksource orion_clksrc = {
47 .name = "orion_clocksource",
48 .shift = 20,
49 .rating = 300,
50 .read = orion_clksrc_read,
51 .mask = CLOCKSOURCE_MASK(32),
52 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
53};
54
55static int
56orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
57{
58 unsigned long flags;
59
60 if (delta == 0)
61 return -ETIME;
62
63 local_irq_save(flags);
64
65 /*
66 * Clear and enable timer interrupt bit
67 */
68 orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
69 orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
70
71 /*
72 * Setup new timer value
73 */
74 orion_write(TIMER_VAL(CLOCKEVENT), delta);
75
76 /*
77 * Disable auto reload and kickoff the timer
78 */
79 orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT));
80 orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT));
81
82 local_irq_restore(flags);
83
84 return 0;
85}
86
87static void
88orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
89{
90 unsigned long flags;
91
92 local_irq_save(flags);
93
94 if (mode == CLOCK_EVT_MODE_PERIODIC) {
95 /*
96 * Setup latch cycles in timer and enable reload interrupt.
97 */
98 orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH);
99 orion_write(TIMER_VAL(CLOCKEVENT), LATCH);
100 orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
101 orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
102 TIMER_EN(CLOCKEVENT));
103 } else {
104 /*
105 * Disable timer and interrupt
106 */
107 orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
108 orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
109 orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
110 TIMER_EN(CLOCKEVENT));
111 }
112
113 local_irq_restore(flags);
114}
115
116static struct clock_event_device orion_clkevt = {
117 .name = "orion_tick",
118 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
119 .shift = 32,
120 .rating = 300,
121 .cpumask = CPU_MASK_CPU0,
122 .set_next_event = orion_clkevt_next_event,
123 .set_mode = orion_clkevt_mode,
124};
125
126static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
127{
128 /*
129 * Clear cause bit and do event
130 */
131 orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
132 orion_clkevt.event_handler(&orion_clkevt);
133 return IRQ_HANDLED;
134}
135
136static struct irqaction orion_timer_irq = {
137 .name = "orion_tick",
138 .flags = IRQF_DISABLED | IRQF_TIMER,
139 .handler = orion_timer_interrupt
140};
141
142static void orion_timer_init(void)
143{
144 /*
145 * Setup clocksource free running timer (no interrupt on reload)
146 */
147 orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff);
148 orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff);
149 orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE));
150 orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) |
151 TIMER_EN(CLOCKSOURCE));
152
153 /*
154 * Register clocksource
155 */
156 orion_clksrc.mult =
157 clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift);
158
159 clocksource_register(&orion_clksrc);
160
161 /*
162 * Connect and enable tick handler
163 */
164 setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq);
165
166 /*
167 * Register clockevent
168 */
169 orion_clkevt.mult =
170 div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift);
171 orion_clkevt.max_delta_ns =
172 clockevent_delta2ns(0xfffffffe, &orion_clkevt);
173 orion_clkevt.min_delta_ns =
174 clockevent_delta2ns(1, &orion_clkevt);
175
176 clockevents_register_device(&orion_clkevt);
177}
178
179struct sys_timer orion_timer = {
180 .init = orion_timer_init,
181};
diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion/ts209-setup.c
new file mode 100644
index 000000000000..e3e930efd155
--- /dev/null
+++ b/arch/arm/mach-orion/ts209-setup.c
@@ -0,0 +1,335 @@
1/*
2 * QNAP TS-109/TS-209 Board Setup
3 *
4 * Maintainer: Byron Bradley <byron.bbradley@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/pci.h>
16#include <linux/irq.h>
17#include <linux/mtd/physmap.h>
18#include <linux/mtd/nand.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/gpio_keys.h>
21#include <linux/input.h>
22#include <linux/i2c.h>
23#include <linux/serial_reg.h>
24#include <asm/mach-types.h>
25#include <asm/gpio.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/pci.h>
28#include <asm/arch/orion.h>
29#include <asm/arch/platform.h>
30#include "common.h"
31
32#define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
33#define QNAP_TS209_NOR_BOOT_SIZE SZ_8M
34
35/****************************************************************************
36 * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
37 * partitions on the device because we want to keep compatability with
38 * existing QNAP firmware.
39 *
40 * Layout as used by QNAP:
41 * [2] 0x00000000-0x00200000 : "Kernel"
42 * [3] 0x00200000-0x00600000 : "RootFS1"
43 * [4] 0x00600000-0x00700000 : "RootFS2"
44 * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
45 * [5] 0x00760000-0x00780000 : "U-Boot Config"
46 * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
47 ***************************************************************************/
48static struct mtd_partition qnap_ts209_partitions[] = {
49 {
50 .name = "U-Boot",
51 .size = 0x00080000,
52 .offset = 0x00780000,
53 .mask_flags = MTD_WRITEABLE,
54 }, {
55 .name = "Kernel",
56 .size = 0x00200000,
57 .offset = 0,
58 }, {
59 .name = "RootFS1",
60 .size = 0x00400000,
61 .offset = 0x00200000,
62 }, {
63 .name = "RootFS2",
64 .size = 0x00100000,
65 .offset = 0x00600000,
66 }, {
67 .name = "U-Boot Config",
68 .size = 0x00020000,
69 .offset = 0x00760000,
70 }, {
71 .name = "NAS Config",
72 .size = 0x00060000,
73 .offset = 0x00700000,
74 .mask_flags = MTD_WRITEABLE,
75 }
76};
77
78static struct physmap_flash_data qnap_ts209_nor_flash_data = {
79 .width = 1,
80 .parts = qnap_ts209_partitions,
81 .nr_parts = ARRAY_SIZE(qnap_ts209_partitions)
82};
83
84static struct resource qnap_ts209_nor_flash_resource = {
85 .flags = IORESOURCE_MEM,
86 .start = QNAP_TS209_NOR_BOOT_BASE,
87 .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
88};
89
90static struct platform_device qnap_ts209_nor_flash = {
91 .name = "physmap-flash",
92 .id = 0,
93 .dev = { .platform_data = &qnap_ts209_nor_flash_data, },
94 .resource = &qnap_ts209_nor_flash_resource,
95 .num_resources = 1,
96};
97
98/*****************************************************************************
99 * PCI
100 ****************************************************************************/
101
102#define QNAP_TS209_PCI_SLOT0_OFFS 7
103#define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6
104#define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7
105
106void __init qnap_ts209_pci_preinit(void)
107{
108 int pin;
109
110 /*
111 * Configure PCI GPIO IRQ pins
112 */
113 pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
114 if (gpio_request(pin, "PCI Int1") == 0) {
115 if (gpio_direction_input(pin) == 0) {
116 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
117 } else {
118 printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
119 "set_irq_type pin %d\n", pin);
120 gpio_free(pin);
121 }
122 } else {
123 printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request "
124 "%d\n", pin);
125 }
126
127 pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
128 if (gpio_request(pin, "PCI Int2") == 0) {
129 if (gpio_direction_input(pin) == 0) {
130 set_irq_type(gpio_to_irq(pin), IRQT_LOW);
131 } else {
132 printk(KERN_ERR "qnap_ts209_pci_preinit failed "
133 "to set_irq_type pin %d\n", pin);
134 gpio_free(pin);
135 }
136 } else {
137 printk(KERN_ERR "qnap_ts209_pci_preinit failed to gpio_request "
138 "%d\n", pin);
139 }
140}
141
142static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
143{
144 /*
145 * PCIE IRQ is connected internally (not GPIO)
146 */
147 if (dev->bus->number == orion_pcie_local_bus_nr())
148 return IRQ_ORION_PCIE0_INT;
149
150 /*
151 * PCI IRQs are connected via GPIOs
152 */
153 switch (slot - QNAP_TS209_PCI_SLOT0_OFFS) {
154 case 0:
155 return gpio_to_irq(QNAP_TS209_PCI_SLOT0_IRQ_PIN);
156 case 1:
157 return gpio_to_irq(QNAP_TS209_PCI_SLOT1_IRQ_PIN);
158 default:
159 return -1;
160 }
161}
162
163static struct hw_pci qnap_ts209_pci __initdata = {
164 .nr_controllers = 2,
165 .preinit = qnap_ts209_pci_preinit,
166 .swizzle = pci_std_swizzle,
167 .setup = orion_pci_sys_setup,
168 .scan = orion_pci_sys_scan_bus,
169 .map_irq = qnap_ts209_pci_map_irq,
170};
171
172static int __init qnap_ts209_pci_init(void)
173{
174 if (machine_is_ts_x09())
175 pci_common_init(&qnap_ts209_pci);
176
177 return 0;
178}
179
180subsys_initcall(qnap_ts209_pci_init);
181
182/*****************************************************************************
183 * Ethernet
184 ****************************************************************************/
185
186static struct mv643xx_eth_platform_data qnap_ts209_eth_data = {
187 .phy_addr = 8,
188 .force_phy_addr = 1,
189};
190
191/*****************************************************************************
192 * RTC S35390A on I2C bus
193 ****************************************************************************/
194static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = {
195 .driver_name = "rtc-s35390a",
196 .addr = 0x30,
197};
198
199/****************************************************************************
200 * GPIO Attached Keys
201 * Power button is attached to the PIC microcontroller
202 ****************************************************************************/
203
204#define QNAP_TS209_GPIO_KEY_MEDIA 1
205#define QNAP_TS209_GPIO_KEY_RESET 2
206
207static struct gpio_keys_button qnap_ts209_buttons[] = {
208 {
209 .code = KEY_RESTART,
210 .gpio = QNAP_TS209_GPIO_KEY_MEDIA,
211 .desc = "USB Copy Button",
212 .active_low = 1,
213 },
214 {
215 .code = KEY_POWER,
216 .gpio = QNAP_TS209_GPIO_KEY_RESET,
217 .desc = "Reset Button",
218 .active_low = 1,
219 }
220};
221
222static struct gpio_keys_platform_data qnap_ts209_button_data = {
223 .buttons = qnap_ts209_buttons,
224 .nbuttons = ARRAY_SIZE(qnap_ts209_buttons),
225};
226
227static struct platform_device qnap_ts209_button_device = {
228 .name = "gpio-keys",
229 .id = -1,
230 .num_resources = 0,
231 .dev = { .platform_data = &qnap_ts209_button_data, },
232};
233
234/*****************************************************************************
235 * General Setup
236 ****************************************************************************/
237
238static struct platform_device *qnap_ts209_devices[] __initdata = {
239 &qnap_ts209_nor_flash,
240 &qnap_ts209_button_device,
241};
242
243/*
244 * QNAP TS-[12]09 specific power off method via UART1-attached PIC
245 */
246
247#define UART1_REG(x) (UART1_BASE + ((UART_##x) << 2))
248
249static void qnap_ts209_power_off(void)
250{
251 /* 19200 baud divisor */
252 const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200));
253
254 pr_info("%s: triggering power-off...\n", __func__);
255
256 /* hijack uart1 and reset into sane state (19200,8n1) */
257 orion_write(UART1_REG(LCR), 0x83);
258 orion_write(UART1_REG(DLL), divisor & 0xff);
259 orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff);
260 orion_write(UART1_REG(LCR), 0x03);
261 orion_write(UART1_REG(IER), 0x00);
262 orion_write(UART1_REG(FCR), 0x00);
263 orion_write(UART1_REG(MCR), 0x00);
264
265 /* send the power-off command 'A' to PIC */
266 orion_write(UART1_REG(TX), 'A');
267}
268
269static void __init qnap_ts209_init(void)
270{
271 /*
272 * Setup basic Orion functions. Need to be called early.
273 */
274 orion_init();
275
276 /*
277 * Setup flash mapping
278 */
279 orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE,
280 QNAP_TS209_NOR_BOOT_SIZE, -1);
281
282 /*
283 * Open a special address decode windows for the PCIE WA.
284 */
285 orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
286 orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
287 (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
288
289 /*
290 * Setup Multiplexing Pins --
291 * MPP[0] Reserved
292 * MPP[1] USB copy button (0 active)
293 * MPP[2] Load defaults button (0 active)
294 * MPP[3] GPIO RTC
295 * MPP[4-5] Reserved
296 * MPP[6] PCI Int A
297 * MPP[7] PCI Int B
298 * MPP[8-11] Reserved
299 * MPP[12] SATA 0 presence
300 * MPP[13] SATA 1 presence
301 * MPP[14] SATA 0 active
302 * MPP[15] SATA 1 active
303 * MPP[16] UART1 RXD
304 * MPP[17] UART1 TXD
305 * MPP[18] SW_RST (0 active)
306 * MPP[19] Reserved
307 * MPP[20] PCI clock 0
308 * MPP[21] PCI clock 1
309 * MPP[22] USB 0 over current
310 * MPP[23-25] Reserved
311 */
312 orion_write(MPP_0_7_CTRL, 0x3);
313 orion_write(MPP_8_15_CTRL, 0x55550000);
314 orion_write(MPP_16_19_CTRL, 0x5500);
315 orion_gpio_set_valid_pins(0x3cc0fff);
316
317 /* register ts209 specific power-off method */
318 pm_power_off = qnap_ts209_power_off;
319
320 platform_add_devices(qnap_ts209_devices,
321 ARRAY_SIZE(qnap_ts209_devices));
322 i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
323 orion_eth_init(&qnap_ts209_eth_data);
324}
325
326MACHINE_START(TS209, "QNAP TS-109/TS-209")
327 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
328 .phys_io = ORION_REGS_BASE,
329 .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
330 .boot_params = 0x00000100,
331 .init_machine = qnap_ts209_init,
332 .map_io = orion_map_io,
333 .init_irq = orion_init_irq,
334 .timer = &orion_timer,
335MACHINE_END
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index cb104c2a7329..76348f060f27 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -342,6 +342,27 @@ config CPU_XSC3
342 select CPU_TLB_V4WBI if MMU 342 select CPU_TLB_V4WBI if MMU
343 select IO_36 343 select IO_36
344 344
345# Feroceon
346config CPU_FEROCEON
347 bool
348 depends on ARCH_ORION
349 default y
350 select CPU_32v5
351 select CPU_ABRT_EV5T
352 select CPU_CACHE_VIVT
353 select CPU_CP15_MMU
354 select CPU_COPY_V4WB if MMU
355 select CPU_TLB_V4WBI if MMU
356
357config CPU_FEROCEON_OLD_ID
358 bool "Accept early Feroceon cores with an ARM926 ID"
359 depends on CPU_FEROCEON && !CPU_ARM926T
360 default y
361 help
362 This enables the usage of some old Feroceon cores
363 for which the CPU ID is equal to the ARM926 ID.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
365
345# ARMv6 366# ARMv6
346config CPU_V6 367config CPU_V6
347 bool "Support ARM V6 processor" 368 bool "Support ARM V6 processor"
@@ -539,7 +560,7 @@ comment "Processor Features"
539 560
540config ARM_THUMB 561config ARM_THUMB
541 bool "Support Thumb user binaries" 562 bool "Support Thumb user binaries"
542 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 563 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
543 default y 564 default y
544 help 565 help
545 Say Y if you want to include kernel support for running user space 566 Say Y if you want to include kernel support for running user space
@@ -601,7 +622,7 @@ config CPU_DCACHE_SIZE
601 622
602config CPU_DCACHE_WRITETHROUGH 623config CPU_DCACHE_WRITETHROUGH
603 bool "Force write through D-cache" 624 bool "Force write through D-cache"
604 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE 625 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE
605 default y if CPU_ARM925T 626 default y if CPU_ARM925T
606 help 627 help
607 Say Y here to use the data cache in writethrough mode. Unless you 628 Say Y here to use the data cache in writethrough mode. Unless you
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 762702765fc3..44536a0b995a 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -68,6 +68,7 @@ obj-$(CONFIG_CPU_SA110) += proc-sa110.o
68obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o 68obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o
69obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o 69obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o
70obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o 70obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o
71obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o
71obj-$(CONFIG_CPU_V6) += proc-v6.o 72obj-$(CONFIG_CPU_V6) += proc-v6.o
72obj-$(CONFIG_CPU_V7) += proc-v7.o 73obj-$(CONFIG_CPU_V7) += proc-v7.o
73 74
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
new file mode 100644
index 000000000000..fa0dc7e6f0ea
--- /dev/null
+++ b/arch/arm/mm/proc-feroceon.S
@@ -0,0 +1,506 @@
1/*
2 * linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
3 *
4 * Heavily based on proc-arm926.S
5 * Maintainer: Assaf Hoffman <hoffman@marvell.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/linkage.h>
23#include <linux/init.h>
24#include <asm/assembler.h>
25#include <asm/elf.h>
26#include <asm/pgtable-hwdef.h>
27#include <asm/pgtable.h>
28#include <asm/page.h>
29#include <asm/ptrace.h>
30#include "proc-macros.S"
31
32/*
33 * This is the maximum size of an area which will be invalidated
34 * using the single invalidate entry instructions. Anything larger
35 * than this, and we go for the whole cache.
36 *
37 * This value should be chosen such that we choose the cheapest
38 * alternative.
39 */
40#define CACHE_DLIMIT 16384
41
42/*
43 * the cache line size of the I and D cache
44 */
45#define CACHE_DLINESIZE 32
46
47 .text
48/*
49 * cpu_feroceon_proc_init()
50 */
51ENTRY(cpu_feroceon_proc_init)
52 mov pc, lr
53
54/*
55 * cpu_feroceon_proc_fin()
56 */
57ENTRY(cpu_feroceon_proc_fin)
58 stmfd sp!, {lr}
59 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
60 msr cpsr_c, ip
61 bl feroceon_flush_kern_cache_all
62 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
63 bic r0, r0, #0x1000 @ ...i............
64 bic r0, r0, #0x000e @ ............wca.
65 mcr p15, 0, r0, c1, c0, 0 @ disable caches
66 ldmfd sp!, {pc}
67
68/*
69 * cpu_feroceon_reset(loc)
70 *
71 * Perform a soft reset of the system. Put the CPU into the
72 * same state as it would be if it had been reset, and branch
73 * to what would be the reset vector.
74 *
75 * loc: location to jump to for soft reset
76 */
77 .align 5
78ENTRY(cpu_feroceon_reset)
79 mov ip, #0
80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
81 mcr p15, 0, ip, c7, c10, 4 @ drain WB
82#ifdef CONFIG_MMU
83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
84#endif
85 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
86 bic ip, ip, #0x000f @ ............wcam
87 bic ip, ip, #0x1100 @ ...i...s........
88 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
89 mov pc, r0
90
91/*
92 * cpu_feroceon_do_idle()
93 *
94 * Called with IRQs disabled
95 */
96 .align 10
97ENTRY(cpu_feroceon_do_idle)
98 mov r0, #0
99 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
101 mov pc, lr
102
103/*
104 * flush_user_cache_all()
105 *
106 * Clean and invalidate all cache entries in a particular
107 * address space.
108 */
109ENTRY(feroceon_flush_user_cache_all)
110 /* FALLTHROUGH */
111
112/*
113 * flush_kern_cache_all()
114 *
115 * Clean and invalidate the entire cache.
116 */
117ENTRY(feroceon_flush_kern_cache_all)
118 mov r2, #VM_EXEC
119 mov ip, #0
120__flush_whole_cache:
121#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
122 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
123#else
1241: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
125 bne 1b
126#endif
127 tst r2, #VM_EXEC
128 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
129 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
130 mov pc, lr
131
132/*
133 * flush_user_cache_range(start, end, flags)
134 *
135 * Clean and invalidate a range of cache entries in the
136 * specified address range.
137 *
138 * - start - start address (inclusive)
139 * - end - end address (exclusive)
140 * - flags - vm_flags describing address space
141 */
142ENTRY(feroceon_flush_user_cache_range)
143 mov ip, #0
144 sub r3, r1, r0 @ calculate total size
145 cmp r3, #CACHE_DLIMIT
146 bgt __flush_whole_cache
1471: tst r2, #VM_EXEC
148#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
149 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
150 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
151 add r0, r0, #CACHE_DLINESIZE
152 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
153 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
154 add r0, r0, #CACHE_DLINESIZE
155#else
156 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
157 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
158 add r0, r0, #CACHE_DLINESIZE
159 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
161 add r0, r0, #CACHE_DLINESIZE
162#endif
163 cmp r0, r1
164 blo 1b
165 tst r2, #VM_EXEC
166 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
167 mov pc, lr
168
169/*
170 * coherent_kern_range(start, end)
171 *
172 * Ensure coherency between the Icache and the Dcache in the
173 * region described by start, end. If you have non-snooping
174 * Harvard caches, you need to implement this function.
175 *
176 * - start - virtual start address
177 * - end - virtual end address
178 */
179ENTRY(feroceon_coherent_kern_range)
180 /* FALLTHROUGH */
181
182/*
183 * coherent_user_range(start, end)
184 *
185 * Ensure coherency between the Icache and the Dcache in the
186 * region described by start, end. If you have non-snooping
187 * Harvard caches, you need to implement this function.
188 *
189 * - start - virtual start address
190 * - end - virtual end address
191 */
192ENTRY(feroceon_coherent_user_range)
193 bic r0, r0, #CACHE_DLINESIZE - 1
1941: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
195 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
196 add r0, r0, #CACHE_DLINESIZE
197 cmp r0, r1
198 blo 1b
199 mcr p15, 0, r0, c7, c10, 4 @ drain WB
200 mov pc, lr
201
202/*
203 * flush_kern_dcache_page(void *page)
204 *
205 * Ensure no D cache aliasing occurs, either with itself or
206 * the I cache
207 *
208 * - addr - page aligned address
209 */
210ENTRY(feroceon_flush_kern_dcache_page)
211 add r1, r0, #PAGE_SZ
2121: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
213 add r0, r0, #CACHE_DLINESIZE
214 cmp r0, r1
215 blo 1b
216 mov r0, #0
217 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
218 mcr p15, 0, r0, c7, c10, 4 @ drain WB
219 mov pc, lr
220
221/*
222 * dma_inv_range(start, end)
223 *
224 * Invalidate (discard) the specified virtual address range.
225 * May not write back any entries. If 'start' or 'end'
226 * are not cache line aligned, those lines must be written
227 * back.
228 *
229 * - start - virtual start address
230 * - end - virtual end address
231 *
232 * (same as v4wb)
233 */
234ENTRY(feroceon_dma_inv_range)
235#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
236 tst r0, #CACHE_DLINESIZE - 1
237 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
238 tst r1, #CACHE_DLINESIZE - 1
239 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
240#endif
241 bic r0, r0, #CACHE_DLINESIZE - 1
2421: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
243 add r0, r0, #CACHE_DLINESIZE
244 cmp r0, r1
245 blo 1b
246 mcr p15, 0, r0, c7, c10, 4 @ drain WB
247 mov pc, lr
248
249/*
250 * dma_clean_range(start, end)
251 *
252 * Clean the specified virtual address range.
253 *
254 * - start - virtual start address
255 * - end - virtual end address
256 *
257 * (same as v4wb)
258 */
259ENTRY(feroceon_dma_clean_range)
260#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
261 bic r0, r0, #CACHE_DLINESIZE - 1
2621: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
263 add r0, r0, #CACHE_DLINESIZE
264 cmp r0, r1
265 blo 1b
266#endif
267 mcr p15, 0, r0, c7, c10, 4 @ drain WB
268 mov pc, lr
269
270/*
271 * dma_flush_range(start, end)
272 *
273 * Clean and invalidate the specified virtual address range.
274 *
275 * - start - virtual start address
276 * - end - virtual end address
277 */
278ENTRY(feroceon_dma_flush_range)
279 bic r0, r0, #CACHE_DLINESIZE - 1
2801:
281#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
282 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
283#else
284 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
285#endif
286 add r0, r0, #CACHE_DLINESIZE
287 cmp r0, r1
288 blo 1b
289 mcr p15, 0, r0, c7, c10, 4 @ drain WB
290 mov pc, lr
291
292ENTRY(feroceon_cache_fns)
293 .long feroceon_flush_kern_cache_all
294 .long feroceon_flush_user_cache_all
295 .long feroceon_flush_user_cache_range
296 .long feroceon_coherent_kern_range
297 .long feroceon_coherent_user_range
298 .long feroceon_flush_kern_dcache_page
299 .long feroceon_dma_inv_range
300 .long feroceon_dma_clean_range
301 .long feroceon_dma_flush_range
302
303ENTRY(cpu_feroceon_dcache_clean_area)
304#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
3051: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
306 add r0, r0, #CACHE_DLINESIZE
307 subs r1, r1, #CACHE_DLINESIZE
308 bhi 1b
309#endif
310 mcr p15, 0, r0, c7, c10, 4 @ drain WB
311 mov pc, lr
312
313/* =============================== PageTable ============================== */
314
315/*
316 * cpu_feroceon_switch_mm(pgd)
317 *
318 * Set the translation base pointer to be as described by pgd.
319 *
320 * pgd: new page tables
321 */
322 .align 5
323ENTRY(cpu_feroceon_switch_mm)
324#ifdef CONFIG_MMU
325 mov ip, #0
326#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
327 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
328#else
329@ && 'Clean & Invalidate whole DCache'
3301: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
331 bne 1b
332#endif
333 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
334 mcr p15, 0, ip, c7, c10, 4 @ drain WB
335 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
336 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
337#endif
338 mov pc, lr
339
340/*
341 * cpu_feroceon_set_pte_ext(ptep, pte, ext)
342 *
343 * Set a PTE and flush it out
344 */
345 .align 5
346ENTRY(cpu_feroceon_set_pte_ext)
347#ifdef CONFIG_MMU
348 str r1, [r0], #-2048 @ linux version
349
350 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
351
352 bic r2, r1, #PTE_SMALL_AP_MASK
353 bic r2, r2, #PTE_TYPE_MASK
354 orr r2, r2, #PTE_TYPE_SMALL
355
356 tst r1, #L_PTE_USER @ User?
357 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
358
359 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
360 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
361
362 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
363 movne r2, #0
364
365#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
366 eor r3, r2, #0x0a @ C & small page?
367 tst r3, #0x0b
368 biceq r2, r2, #4
369#endif
370 str r2, [r0] @ hardware version
371 mov r0, r0
372#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
373 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
374#endif
375 mcr p15, 0, r0, c7, c10, 4 @ drain WB
376#endif
377 mov pc, lr
378
379 __INIT
380
381 .type __feroceon_setup, #function
382__feroceon_setup:
383 mov r0, #0
384 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
385 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
386#ifdef CONFIG_MMU
387 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
388#endif
389
390
391#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
392 mov r0, #4 @ disable write-back on caches explicitly
393 mcr p15, 7, r0, c15, c0, 0
394#endif
395
396 adr r5, feroceon_crval
397 ldmia r5, {r5, r6}
398 mrc p15, 0, r0, c1, c0 @ get control register v4
399 bic r0, r0, r5
400 orr r0, r0, r6
401#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
402 orr r0, r0, #0x4000 @ .1.. .... .... ....
403#endif
404 mov pc, lr
405 .size __feroceon_setup, . - __feroceon_setup
406
407 /*
408 * R
409 * .RVI ZFRS BLDP WCAM
410 * .011 0001 ..11 0101
411 *
412 */
413 .type feroceon_crval, #object
414feroceon_crval:
415 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
416
417 __INITDATA
418
419/*
420 * Purpose : Function pointers used to access above functions - all calls
421 * come through these
422 */
423 .type feroceon_processor_functions, #object
424feroceon_processor_functions:
425 .word v5t_early_abort
426 .word cpu_feroceon_proc_init
427 .word cpu_feroceon_proc_fin
428 .word cpu_feroceon_reset
429 .word cpu_feroceon_do_idle
430 .word cpu_feroceon_dcache_clean_area
431 .word cpu_feroceon_switch_mm
432 .word cpu_feroceon_set_pte_ext
433 .size feroceon_processor_functions, . - feroceon_processor_functions
434
435 .section ".rodata"
436
437 .type cpu_arch_name, #object
438cpu_arch_name:
439 .asciz "armv5te"
440 .size cpu_arch_name, . - cpu_arch_name
441
442 .type cpu_elf_name, #object
443cpu_elf_name:
444 .asciz "v5"
445 .size cpu_elf_name, . - cpu_elf_name
446
447 .type cpu_feroceon_name, #object
448cpu_feroceon_name:
449 .asciz "Feroceon"
450 .size cpu_feroceon_name, . - cpu_feroceon_name
451
452 .align
453
454 .section ".proc.info.init", #alloc, #execinstr
455
456#ifdef CONFIG_CPU_FEROCEON_OLD_ID
457 .type __feroceon_old_id_proc_info,#object
458__feroceon_old_id_proc_info:
459 .long 0x41069260
460 .long 0xfffffff0
461 .long PMD_TYPE_SECT | \
462 PMD_SECT_BUFFERABLE | \
463 PMD_SECT_CACHEABLE | \
464 PMD_BIT4 | \
465 PMD_SECT_AP_WRITE | \
466 PMD_SECT_AP_READ
467 .long PMD_TYPE_SECT | \
468 PMD_BIT4 | \
469 PMD_SECT_AP_WRITE | \
470 PMD_SECT_AP_READ
471 b __feroceon_setup
472 .long cpu_arch_name
473 .long cpu_elf_name
474 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
475 .long cpu_feroceon_name
476 .long feroceon_processor_functions
477 .long v4wbi_tlb_fns
478 .long v4wb_user_fns
479 .long feroceon_cache_fns
480 .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
481#endif
482
483 .type __feroceon_proc_info,#object
484__feroceon_proc_info:
485 .long 0x56055310
486 .long 0xfffffff0
487 .long PMD_TYPE_SECT | \
488 PMD_SECT_BUFFERABLE | \
489 PMD_SECT_CACHEABLE | \
490 PMD_BIT4 | \
491 PMD_SECT_AP_WRITE | \
492 PMD_SECT_AP_READ
493 .long PMD_TYPE_SECT | \
494 PMD_BIT4 | \
495 PMD_SECT_AP_WRITE | \
496 PMD_SECT_AP_READ
497 b __feroceon_setup
498 .long cpu_arch_name
499 .long cpu_elf_name
500 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
501 .long cpu_feroceon_name
502 .long feroceon_processor_functions
503 .long v4wbi_tlb_fns
504 .long v4wb_user_fns
505 .long feroceon_cache_fns
506 .size __feroceon_proc_info, . - __feroceon_proc_info
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
index 548a32082e4a..4316f5a48a0f 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -361,12 +361,6 @@ static int __init mv64x60_i2c_device_setup(struct device_node *np, int id)
361 else 361 else
362 pdata.timeout = 1000; /* 1 second */ 362 pdata.timeout = 1000; /* 1 second */
363 363
364 prop = of_get_property(np, "retries", NULL);
365 if (prop)
366 pdata.retries = *prop;
367 else
368 pdata.retries = 1;
369
370 pdev = platform_device_alloc(MV64XXX_I2C_CTLR_NAME, id); 364 pdev = platform_device_alloc(MV64XXX_I2C_CTLR_NAME, id);
371 if (!pdev) 365 if (!pdev)
372 return -ENOMEM; 366 return -ENOMEM;
diff --git a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c
index 2744b8a6f66a..90fe904d3614 100644
--- a/arch/ppc/syslib/mv64x60.c
+++ b/arch/ppc/syslib/mv64x60.c
@@ -411,7 +411,6 @@ static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = {
411 .freq_m = 8, 411 .freq_m = 8,
412 .freq_n = 3, 412 .freq_n = 3,
413 .timeout = 1000, /* Default timeout of 1 second */ 413 .timeout = 1000, /* Default timeout of 1 second */
414 .retries = 1,
415}; 414};
416 415
417static struct resource mv64xxx_i2c_resources[] = { 416static struct resource mv64xxx_i2c_resources[] = {
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 8d12b26bb6c6..b61f56b6f311 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -643,7 +643,7 @@ config I2C_PCA_ISA
643 643
644config I2C_MV64XXX 644config I2C_MV64XXX
645 tristate "Marvell mv64xxx I2C Controller" 645 tristate "Marvell mv64xxx I2C Controller"
646 depends on MV64X60 && EXPERIMENTAL 646 depends on (MV64X60 || ARCH_ORION) && EXPERIMENTAL
647 help 647 help
648 If you say yes to this option, support will be included for the 648 If you say yes to this option, support will be included for the
649 built-in I2C interface on the Marvell 64xxx line of host bridges. 649 built-in I2C interface on the Marvell 64xxx line of host bridges.
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index bb7bf68a7fb6..036e6a883e67 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * Driver for the i2c controller on the Marvell line of host bridges for MIPS 2 * Driver for the i2c controller on the Marvell line of host bridges
3 * and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0). 3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
4 * 4 *
5 * Author: Mark A. Greer <mgreer@mvista.com> 5 * Author: Mark A. Greer <mgreer@mvista.com>
6 * 6 *
@@ -14,7 +14,7 @@
14#include <linux/spinlock.h> 14#include <linux/spinlock.h>
15#include <linux/i2c.h> 15#include <linux/i2c.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/mv643xx.h> 17#include <linux/mv643xx_i2c.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19 19
20#include <asm/io.h> 20#include <asm/io.h>
@@ -86,6 +86,7 @@ struct mv64xxx_i2c_data {
86 u32 cntl_bits; 86 u32 cntl_bits;
87 void __iomem *reg_base; 87 void __iomem *reg_base;
88 u32 reg_base_p; 88 u32 reg_base_p;
89 u32 reg_size;
89 u32 addr1; 90 u32 addr1;
90 u32 addr2; 91 u32 addr2;
91 u32 bytes_left; 92 u32 bytes_left;
@@ -463,17 +464,20 @@ static int __devinit
463mv64xxx_i2c_map_regs(struct platform_device *pd, 464mv64xxx_i2c_map_regs(struct platform_device *pd,
464 struct mv64xxx_i2c_data *drv_data) 465 struct mv64xxx_i2c_data *drv_data)
465{ 466{
466 struct resource *r; 467 int size;
468 struct resource *r = platform_get_resource(pd, IORESOURCE_MEM, 0);
467 469
468 if ((r = platform_get_resource(pd, IORESOURCE_MEM, 0)) && 470 if (!r)
469 request_mem_region(r->start, MV64XXX_I2C_REG_BLOCK_SIZE, 471 return -ENODEV;
470 drv_data->adapter.name)) {
471 472
472 drv_data->reg_base = ioremap(r->start, 473 size = r->end - r->start + 1;
473 MV64XXX_I2C_REG_BLOCK_SIZE); 474
474 drv_data->reg_base_p = r->start; 475 if (!request_mem_region(r->start, size, drv_data->adapter.name))
475 } else 476 return -EBUSY;
476 return -ENOMEM; 477
478 drv_data->reg_base = ioremap(r->start, size);
479 drv_data->reg_base_p = r->start;
480 drv_data->reg_size = size;
477 481
478 return 0; 482 return 0;
479} 483}
@@ -483,8 +487,7 @@ mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data)
483{ 487{
484 if (drv_data->reg_base) { 488 if (drv_data->reg_base) {
485 iounmap(drv_data->reg_base); 489 iounmap(drv_data->reg_base);
486 release_mem_region(drv_data->reg_base_p, 490 release_mem_region(drv_data->reg_base_p, drv_data->reg_size);
487 MV64XXX_I2C_REG_BLOCK_SIZE);
488 } 491 }
489 492
490 drv_data->reg_base = NULL; 493 drv_data->reg_base = NULL;
@@ -529,7 +532,6 @@ mv64xxx_i2c_probe(struct platform_device *pd)
529 drv_data->adapter.owner = THIS_MODULE; 532 drv_data->adapter.owner = THIS_MODULE;
530 drv_data->adapter.class = I2C_CLASS_HWMON; 533 drv_data->adapter.class = I2C_CLASS_HWMON;
531 drv_data->adapter.timeout = pdata->timeout; 534 drv_data->adapter.timeout = pdata->timeout;
532 drv_data->adapter.retries = pdata->retries;
533 drv_data->adapter.nr = pd->id; 535 drv_data->adapter.nr = pd->id;
534 platform_set_drvdata(pd, drv_data); 536 platform_set_drvdata(pd, drv_data);
535 i2c_set_adapdata(&drv_data->adapter, drv_data); 537 i2c_set_adapdata(&drv_data->adapter, drv_data);
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion/debug-macro.S
new file mode 100644
index 000000000000..e2a80641f214
--- /dev/null
+++ b/include/asm-arm/arch-orion/debug-macro.S
@@ -0,0 +1,17 @@
1/*
2 * linux/include/asm-arm/arch-orion/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11 .macro addruart,rx
12 mov \rx, #0xf1000000
13 orr \rx, \rx, #0x00012000
14 .endm
15
16#define UART_SHIFT 2
17#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-orion/dma.h
@@ -0,0 +1 @@
/* empty */
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion/entry-macro.S
new file mode 100644
index 000000000000..b76075a7e44b
--- /dev/null
+++ b/include/asm-arm/arch-orion/entry-macro.S
@@ -0,0 +1,31 @@
1/*
2 * include/asm-arm/arch-orion/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Orion platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/arch/orion.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =MAIN_IRQ_CAUSE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 ldr \irqstat, [\base, #0] @ main cause
25 ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
26 mov \irqnr, #0 @ default irqnr
27 @ find cause bits that are unmasked
28 ands \irqstat, \irqstat, \tmp @ clear Z flag if any
29 clzne \irqnr, \irqstat @ calc irqnr
30 rsbne \irqnr, \irqnr, #31
31 .endm
diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion/gpio.h
new file mode 100644
index 000000000000..d66284f9a14c
--- /dev/null
+++ b/include/asm-arm/arch-orion/gpio.h
@@ -0,0 +1,28 @@
1/*
2 * include/asm-arm/arch-orion/gpio.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9extern int gpio_request(unsigned pin, const char *label);
10extern void gpio_free(unsigned pin);
11extern int gpio_direction_input(unsigned pin);
12extern int gpio_direction_output(unsigned pin, int value);
13extern int gpio_get_value(unsigned pin);
14extern void gpio_set_value(unsigned pin, int value);
15extern void orion_gpio_set_blink(unsigned pin, int blink);
16extern void gpio_display(void); /* debug */
17
18static inline int gpio_to_irq(int pin)
19{
20 return pin + IRQ_ORION_GPIO_START;
21}
22
23static inline int irq_to_gpio(int irq)
24{
25 return irq - IRQ_ORION_GPIO_START;
26}
27
28#include <asm-generic/gpio.h> /* cansleep wrappers */
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion/hardware.h
new file mode 100644
index 000000000000..8a12d213fbdc
--- /dev/null
+++ b/include/asm-arm/arch-orion/hardware.h
@@ -0,0 +1,24 @@
1/*
2 * include/asm-arm/arch-orion/hardware.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __ASM_ARCH_HARDWARE_H__
11#define __ASM_ARCH_HARDWARE_H__
12
13#include "orion.h"
14
15#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE
16#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
17
18#define pcibios_assign_all_busses() 1
19
20#define PCIBIOS_MIN_IO 0x1000
21#define PCIBIOS_MIN_MEM 0x01000000
22#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
23
24#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion/io.h
new file mode 100644
index 000000000000..e0b8c39b9167
--- /dev/null
+++ b/include/asm-arm/arch-orion/io.h
@@ -0,0 +1,27 @@
1/*
2 * include/asm-arm/arch-orion/io.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARM_ARCH_IO_H
12#define __ASM_ARM_ARCH_IO_H
13
14#include "orion.h"
15
16#define IO_SPACE_LIMIT 0xffffffff
17#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE
18
19static inline void __iomem *__io(unsigned long addr)
20{
21 return (void __iomem *)addr;
22}
23
24#define __io(a) __io(a)
25#define __mem_pci(a) (a)
26
27#endif
diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h
new file mode 100644
index 000000000000..eea65ca6076a
--- /dev/null
+++ b/include/asm-arm/arch-orion/irqs.h
@@ -0,0 +1,61 @@
1/*
2 * include/asm-arm/arch-orion/irqs.h
3 *
4 * IRQ definitions for Orion SoC
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __ASM_ARCH_IRQS_H__
14#define __ASM_ARCH_IRQS_H__
15
16#include "orion.h" /* need GPIO_MAX */
17
18/*
19 * Orion Main Interrupt Controller
20 */
21#define IRQ_ORION_BRIDGE 0
22#define IRQ_ORION_DOORBELL_H2C 1
23#define IRQ_ORION_DOORBELL_C2H 2
24#define IRQ_ORION_UART0 3
25#define IRQ_ORION_UART1 4
26#define IRQ_ORION_I2C 5
27#define IRQ_ORION_GPIO_0_7 6
28#define IRQ_ORION_GPIO_8_15 7
29#define IRQ_ORION_GPIO_16_23 8
30#define IRQ_ORION_GPIO_24_31 9
31#define IRQ_ORION_PCIE0_ERR 10
32#define IRQ_ORION_PCIE0_INT 11
33#define IRQ_ORION_USB1_CTRL 12
34#define IRQ_ORION_DEV_BUS_ERR 14
35#define IRQ_ORION_PCI_ERR 15
36#define IRQ_ORION_USB_BR_ERR 16
37#define IRQ_ORION_USB0_CTRL 17
38#define IRQ_ORION_ETH_RX 18
39#define IRQ_ORION_ETH_TX 19
40#define IRQ_ORION_ETH_MISC 20
41#define IRQ_ORION_ETH_SUM 21
42#define IRQ_ORION_ETH_ERR 22
43#define IRQ_ORION_IDMA_ERR 23
44#define IRQ_ORION_IDMA_0 24
45#define IRQ_ORION_IDMA_1 25
46#define IRQ_ORION_IDMA_2 26
47#define IRQ_ORION_IDMA_3 27
48#define IRQ_ORION_CESA 28
49#define IRQ_ORION_SATA 29
50#define IRQ_ORION_XOR0 30
51#define IRQ_ORION_XOR1 31
52
53/*
54 * Orion General Purpose Pins
55 */
56#define IRQ_ORION_GPIO_START 32
57#define NR_GPIO_IRQS GPIO_MAX
58
59#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
60
61#endif /* __ASM_ARCH_IRQS_H__ */
diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion/memory.h
new file mode 100644
index 000000000000..d954dba87ced
--- /dev/null
+++ b/include/asm-arm/arch-orion/memory.h
@@ -0,0 +1,15 @@
1/*
2 * include/asm-arm/arch-orion/memory.h
3 *
4 * Marvell Orion memory definitions
5 */
6
7#ifndef __ASM_ARCH_MMU_H
8#define __ASM_ARCH_MMU_H
9
10#define PHYS_OFFSET UL(0x00000000)
11
12#define __virt_to_bus(x) __virt_to_phys(x)
13#define __bus_to_virt(x) __phys_to_virt(x)
14
15#endif
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
new file mode 100644
index 000000000000..f787f752e58c
--- /dev/null
+++ b/include/asm-arm/arch-orion/orion.h
@@ -0,0 +1,143 @@
1/*
2 * include/asm-arm/arch-orion/orion.h
3 *
4 * Generic definitions of Orion SoC flavors:
5 * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
6 *
7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __ASM_ARCH_ORION_H__
15#define __ASM_ARCH_ORION_H__
16
17/*******************************************************************************
18 * Orion Address Map
19 * Use the same mapping (1:1 virtual:physical) of internal registers and
20 * PCI system (PCI+PCIE) for all machines.
21 * Each machine defines the rest of its mapping (e.g. device bus flashes)
22 ******************************************************************************/
23#define ORION_REGS_BASE 0xf1000000
24#define ORION_REGS_SIZE SZ_1M
25
26#define ORION_PCI_SYS_MEM_BASE 0xe0000000
27#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE
28#define ORION_PCIE_MEM_SIZE SZ_128M
29#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
30#define ORION_PCI_MEM_SIZE SZ_128M
31
32#define ORION_PCI_SYS_IO_BASE 0xf2000000
33#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
34#define ORION_PCIE_IO_SIZE SZ_1M
35#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
36#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
37#define ORION_PCI_IO_SIZE SZ_1M
38#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
39/* Relevant only for Orion-NAS */
40#define ORION_PCIE_WA_BASE 0xf0000000
41#define ORION_PCIE_WA_SIZE SZ_16M
42
43/*******************************************************************************
44 * Supported Devices & Revisions
45 ******************************************************************************/
46/* Orion-1 (88F5181) */
47#define MV88F5181_DEV_ID 0x5181
48#define MV88F5181_REV_B1 3
49/* Orion-NAS (88F5182) */
50#define MV88F5182_DEV_ID 0x5182
51#define MV88F5182_REV_A2 2
52/* Orion-2 (88F5281) */
53#define MV88F5281_DEV_ID 0x5281
54#define MV88F5281_REV_D1 5
55#define MV88F5281_REV_D2 6
56
57/*******************************************************************************
58 * Orion Registers Map
59 ******************************************************************************/
60#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000)
61#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000)
62#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000)
63#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000)
64#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000)
65#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000)
66#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000)
67#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000)
68#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000)
69
70#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x))
71#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x))
72#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x))
73#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x))
74#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x))
75#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x))
76#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x))
77#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x))
78#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x))
79
80/*******************************************************************************
81 * Device Bus Registers
82 ******************************************************************************/
83#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000)
84#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004)
85#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050)
86#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008)
87#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010)
88#define GPIO_OUT ORION_DEV_BUS_REG(0x100)
89#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104)
90#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108)
91#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c)
92#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110)
93#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114)
94#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118)
95#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c)
96#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c)
97#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460)
98#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464)
99#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c)
100#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
101#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
102#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
103#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
104#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
105#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
106#define GPIO_MAX 32
107
108/***************************************************************************
109 * Orion CPU Bridge Registers
110 **************************************************************************/
111#define CPU_CONF ORION_BRIDGE_REG(0x100)
112#define CPU_CTRL ORION_BRIDGE_REG(0x104)
113#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108)
114#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c)
115#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C)
116#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110)
117#define BRIDGE_MASK ORION_BRIDGE_REG(0x114)
118#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
119#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
120#define TIMER_CTRL ORION_BRIDGE_REG(0x300)
121#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8))
122#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8))
123
124#ifndef __ASSEMBLY__
125
126/*******************************************************************************
127 * Helpers to access Orion registers
128 ******************************************************************************/
129#include <asm/types.h>
130#include <asm/io.h>
131
132#define orion_read(r) __raw_readl(r)
133#define orion_write(r, val) __raw_writel(val, r)
134
135/*
136 * These are not preempt safe. Locks, if needed, must be taken care by caller.
137 */
138#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask))
139#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask))
140
141#endif /* __ASSEMBLY__ */
142
143#endif /* __ASM_ARCH_ORION_H__ */
diff --git a/include/asm-arm/arch-orion/platform.h b/include/asm-arm/arch-orion/platform.h
new file mode 100644
index 000000000000..143c38e2fa0b
--- /dev/null
+++ b/include/asm-arm/arch-orion/platform.h
@@ -0,0 +1,25 @@
1/*
2 * asm-arm/arch-orion/platform.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_PLATFORM_H__
12#define __ASM_ARCH_PLATFORM_H__
13
14/*
15 * Device bus NAND private data
16 */
17struct orion_nand_data {
18 struct mtd_partition *parts;
19 u32 nr_parts;
20 u8 ale; /* address line number connected to ALE */
21 u8 cle; /* address line number connected to CLE */
22 u8 width; /* buswidth */
23};
24
25#endif
diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion/system.h
new file mode 100644
index 000000000000..17704c68f90e
--- /dev/null
+++ b/include/asm-arm/arch-orion/system.h
@@ -0,0 +1,31 @@
1/*
2 * include/asm-arm/arch-orion/system.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H
13
14#include <asm/arch/hardware.h>
15#include <asm/arch/orion.h>
16
17static inline void arch_idle(void)
18{
19 cpu_do_idle();
20}
21
22static inline void arch_reset(char mode)
23{
24 /*
25 * Enable and issue soft reset
26 */
27 orion_setbits(CPU_RESET_MASK, (1 << 2));
28 orion_setbits(CPU_SOFT_RESET, 1);
29}
30
31#endif
diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion/timex.h
new file mode 100644
index 000000000000..26c2c91eecf0
--- /dev/null
+++ b/include/asm-arm/arch-orion/timex.h
@@ -0,0 +1,12 @@
1/*
2 * include/asm-arm/arch-orion/timex.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#define ORION_TCLK 166666667
12#define CLOCK_TICK_RATE ORION_TCLK
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion/uncompress.h
new file mode 100644
index 000000000000..a1a222fb438c
--- /dev/null
+++ b/include/asm-arm/arch-orion/uncompress.h
@@ -0,0 +1,44 @@
1/*
2 * include/asm-arm/arch-orion/uncompress.h
3 *
4 * Tzachi Perelstein <tzachi@marvell.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/arch/orion.h>
12
13#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14))
14#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0))
15
16#define LSR_THRE 0x20
17
18static void putc(const char c)
19{
20 int j = 0x1000;
21 while (--j && !(*MV_UART_LSR & LSR_THRE))
22 barrier();
23 *MV_UART_THR = c;
24}
25
26static void flush(void)
27{
28}
29
30static void orion_early_putstr(const char *ptr)
31{
32 char c;
33 while ((c = *ptr++) != '\0') {
34 if (c == '\n')
35 putc('\r');
36 putc(c);
37 }
38}
39
40/*
41 * nothing to do
42 */
43#define arch_decomp_setup()
44#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion/vmalloc.h
new file mode 100644
index 000000000000..23e2a102fe0c
--- /dev/null
+++ b/include/asm-arm/arch-orion/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-arm/arch-orion/vmalloc.h
3 */
4
5#define VMALLOC_END 0xf0000000
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 6c1c968b2987..759a97b56eed 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -94,6 +94,14 @@
94# endif 94# endif
95#endif 95#endif
96 96
97#if defined(CONFIG_CPU_FEROCEON)
98# ifdef _CACHE
99# define MULTI_CACHE 1
100# else
101# define _CACHE feroceon
102# endif
103#endif
104
97#if defined(CONFIG_CPU_V6) 105#if defined(CONFIG_CPU_V6)
98//# ifdef _CACHE 106//# ifdef _CACHE
99# define MULTI_CACHE 1 107# define MULTI_CACHE 1
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
index 5599d4e5e708..a4ce457199d3 100644
--- a/include/asm-arm/proc-fns.h
+++ b/include/asm-arm/proc-fns.h
@@ -185,6 +185,14 @@
185# define CPU_NAME cpu_xsc3 185# define CPU_NAME cpu_xsc3
186# endif 186# endif
187# endif 187# endif
188# ifdef CONFIG_CPU_FEROCEON
189# ifdef CPU_NAME
190# undef MULTI_CPU
191# define MULTI_CPU
192# else
193# define CPU_NAME cpu_feroceon
194# endif
195# endif
188# ifdef CONFIG_CPU_V6 196# ifdef CONFIG_CPU_V6
189# ifdef CPU_NAME 197# ifdef CPU_NAME
190# undef MULTI_CPU 198# undef MULTI_CPU
diff --git a/include/linux/mv643xx.h b/include/linux/mv643xx.h
index d2ae6185f03b..69327b7b4ce4 100644
--- a/include/linux/mv643xx.h
+++ b/include/linux/mv643xx.h
@@ -15,6 +15,7 @@
15 15
16#include <asm/types.h> 16#include <asm/types.h>
17#include <linux/mv643xx_eth.h> 17#include <linux/mv643xx_eth.h>
18#include <linux/mv643xx_i2c.h>
18 19
19/****************************************/ 20/****************************************/
20/* Processor Address Space */ 21/* Processor Address Space */
@@ -863,7 +864,6 @@
863/* I2C Registers */ 864/* I2C Registers */
864/****************************************/ 865/****************************************/
865 866
866#define MV64XXX_I2C_CTLR_NAME "mv64xxx_i2c"
867#define MV64XXX_I2C_OFFSET 0xc000 867#define MV64XXX_I2C_OFFSET 0xc000
868#define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020 868#define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020
869 869
@@ -968,14 +968,6 @@ struct mpsc_pdata {
968 u32 brg_clk_freq; 968 u32 brg_clk_freq;
969}; 969};
970 970
971/* i2c Platform Device, Driver Data */
972struct mv64xxx_i2c_pdata {
973 u32 freq_m;
974 u32 freq_n;
975 u32 timeout; /* In milliseconds */
976 u32 retries;
977};
978
979/* Watchdog Platform Device, Driver Data */ 971/* Watchdog Platform Device, Driver Data */
980#define MV64x60_WDT_NAME "mv64x60_wdt" 972#define MV64x60_WDT_NAME "mv64x60_wdt"
981 973
diff --git a/include/linux/mv643xx_i2c.h b/include/linux/mv643xx_i2c.h
new file mode 100644
index 000000000000..5db5152e9de5
--- /dev/null
+++ b/include/linux/mv643xx_i2c.h
@@ -0,0 +1,22 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 */
7
8#ifndef _MV64XXX_I2C_H_
9#define _MV64XXX_I2C_H_
10
11#include <linux/types.h>
12
13#define MV64XXX_I2C_CTLR_NAME "mv64xxx_i2c"
14
15/* i2c Platform Device, Driver Data */
16struct mv64xxx_i2c_pdata {
17 u32 freq_m;
18 u32 freq_n;
19 u32 timeout; /* In milliseconds */
20};
21
22#endif /*_MV64XXX_I2C_H_*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 16:50:45 -0500