i7core_edac: Add an EDAC memory controller driver for Nehalem chipsets

This driver is meant to support i7 core/i7core extreme desktop
processors and Xeon 35xx/55xx series with integrated memory controller.
It is likely that it can be expanded in the future to work with other
processor series based at the same Memory Controller design.

For now, it has just a few MCH status reads.

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

4 files changed, 486 insertions, 0 deletions

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 55c9c59b3f71..391ddbfb2a34 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -166,6 +166,13 @@ config EDAC_I5400
           Support for error detection and correction the Intel
           i5400 MCH chipset (Seaburg).
 
+config EDAC_I7CORE
+        tristate "Intel i7 Core (Nehalem) processors"
+        depends on EDAC_MM_EDAC && PCI && X86
+        help
+          Support for error detection and correction the Intel
+          i7 Core (Nehalem) Integrated Memory Controller
+
 config EDAC_I82860
         tristate "Intel 82860"
         depends on EDAC_MM_EDAC && PCI && X86_32
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index bc5dc232a0fb..b9996195b233 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_EDAC_CPC925)		+= cpc925_edac.o
 obj-$(CONFIG_EDAC_I5000)                += i5000_edac.o
 obj-$(CONFIG_EDAC_I5100)                += i5100_edac.o
 obj-$(CONFIG_EDAC_I5400)                += i5400_edac.o
+obj-$(CONFIG_EDAC_I7CORE)               += i7core_edac.o
 obj-$(CONFIG_EDAC_E7XXX)                += e7xxx_edac.o
 obj-$(CONFIG_EDAC_E752X)                += e752x_edac.o
 obj-$(CONFIG_EDAC_I82443BXGX)           += i82443bxgx_edac.o
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
new file mode 100644
index 000000000000..7ecf15e66a3f
--- /dev/null
+++ b/drivers/edac/i7core_edac.c
@@ -0,0 +1,462 @@
+/* Intel 7 core  Memory Controller kernel module (Nehalem)
+ *
+ * This file may be distributed under the terms of the
+ * GNU General Public License version 2 only.
+ *
+ * Copyright (c) 2009 by:
+ *       Mauro Carvalho Chehab <mchehab@redhat.com>
+ *
+ * Red Hat Inc. http://www.redhat.com
+ *
+ * Forked and adapted from the i5400_edac driver
+ *
+ * Based on the following public Intel datasheets:
+ * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
+ * Datasheet, Volume 2:
+ *      http://download.intel.com/design/processor/datashts/320835.pdf
+ * Intel Xeon Processor 5500 Series Datasheet Volume 2
+ *      http://www.intel.com/Assets/PDF/datasheet/321322.pdf
+ * also available at:
+ *      http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
+ */
+
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/slab.h>
+#include <linux/edac.h>
+#include <linux/mmzone.h>
+
+#include "edac_core.h"
+
+
+/*
+ * Alter this version for the module when modifications are made
+ */
+#define I7CORE_REVISION    " Ver: 1.0.0 " __DATE__
+#define EDAC_MOD_STR      "i7core_edac"
+
+/* HACK: temporary, just to enable all logs, for now */
+#undef debugf0
+#define debugf0(fmt, arg...)  edac_printk(KERN_INFO, "i7core", fmt, ##arg)
+
+/*
+ * Debug macros
+ */
+#define i7core_printk(level, fmt, arg...)                       \
+        edac_printk(level, "i7core", fmt, ##arg)
+
+#define i7core_mc_printk(mci, level, fmt, arg...)               \
+        edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
+
+/*
+ * i7core Memory Controller Registers
+ */
+
+        /* OFFSETS for Device 3 Function 0 */
+
+#define MC_CONTROL      0x48
+#define MC_STATUS       0x4c
+#define MC_MAX_DOD      0x64
+
+        /* OFFSETS for Devices 4,5 and 6 Function 0 */
+
+#define MC_CHANNEL_ADDR_MATCH   0xf0
+
+#define MC_MASK_DIMM    (1 << 41)
+#define MC_MASK_RANK    (1 << 40)
+#define MC_MASK_BANK    (1 << 39)
+#define MC_MASK_PAGE    (1 << 38)
+#define MC_MASK_COL     (1 << 37)
+
+/*
+ * i7core structs
+ */
+
+#define NUM_CHANS 3
+#define NUM_FUNCS 1
+
+struct i7core_info {
+        u32     mc_control;
+        u32     mc_status;
+        u32     max_dod;
+};
+
+struct i7core_pvt {
+        struct pci_dev          *pci_mcr;       /* Dev 3:0 */
+        struct pci_dev          *pci_ch[NUM_CHANS][NUM_FUNCS];
+        struct i7core_info      info;
+};
+
+/* Device name and register DID (Device ID) */
+struct i7core_dev_info {
+        const char *ctl_name;   /* name for this device */
+        u16 fsb_mapping_errors; /* DID for the branchmap,control */
+};
+
+static int chan_pci_ids[NUM_CHANS] = {
+        PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL,     /* Dev 4 */
+        PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL,     /* Dev 5 */
+        PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL,     /* Dev 6 */
+};
+
+/* Table of devices attributes supported by this driver */
+static const struct i7core_dev_info i7core_devs[] = {
+        {
+                .ctl_name = "i7 Core",
+                .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7_MCR,
+        },
+};
+
+static struct edac_pci_ctl_info *i7core_pci;
+
+/****************************************************************************
+                        Anciliary status routines
+ ****************************************************************************/
+
+        /* MC_CONTROL bits */
+#define CH2_ACTIVE(pvt)         ((pvt)->info.mc_control & 1 << 10)
+#define CH1_ACTIVE(pvt)         ((pvt)->info.mc_control & 1 << 9)
+#define CH0_ACTIVE(pvt)         ((pvt)->info.mc_control & 1 << 8)
+#define ECCx8(pvt)              ((pvt)->info.mc_control & 1 << 1)
+
+        /* MC_STATUS bits */
+#define ECC_ENABLED(pvt)        ((pvt)->info.mc_status & 1 << 3)
+#define CH2_DISABLED(pvt)       ((pvt)->info.mc_status & 1 << 2)
+#define CH1_DISABLED(pvt)       ((pvt)->info.mc_status & 1 << 1)
+#define CH0_DISABLED(pvt)       ((pvt)->info.mc_status & 1 << 0)
+
+        /* MC_MAX_DOD read functions */
+static inline int maxnumdimms(struct i7core_pvt *pvt)
+{
+        return (pvt->info.max_dod & 0x3) + 1;
+}
+
+static inline int maxnumrank(struct i7core_pvt *pvt)
+{
+        static int ranks[4] = { 1, 2, 4, -EINVAL };
+
+        return ranks[(pvt->info.max_dod >> 2) & 0x3];
+}
+
+static inline int maxnumbank(struct i7core_pvt *pvt)
+{
+        static int banks[4] = { 4, 8, 16, -EINVAL };
+
+        return banks[(pvt->info.max_dod >> 4) & 0x3];
+}
+
+static inline int maxnumrow(struct i7core_pvt *pvt)
+{
+        static int rows[8] = {
+                1 << 12, 1 << 13, 1 << 14, 1 << 15,
+                1 << 16, -EINVAL, -EINVAL, -EINVAL,
+        };
+
+        return rows[((pvt->info.max_dod >> 6) & 0x7)];
+}
+
+static inline int maxnumcol(struct i7core_pvt *pvt)