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authorLinus Torvalds <torvalds@linux-foundation.org>2010-12-22 22:47:37 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2010-12-22 22:47:37 -0500
commite819eb8687767cefca7b6abf5ac6d5efcf581eeb (patch)
treeef40a82ddbce3fe12b4205a87b5195e8e9fbb136
parentca5f73a05ebfbf74ea9874d5eaad8d63d7e69b4f (diff)
parent0f16830e9f6de0a44cf1e473ffa80cbe612d5beb (diff)
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm: Include the connector name in the output_poll_execute() debug message drm/radeon/kms: fix bug in r600_gpu_is_lockup drm/radeon/kms: reorder display resume to avoid problems drm/radeon/kms/evergreen: reset the grbm blocks at resume and init drm/radeon/kms: fix evergreen asic reset Revert "drm: Don't try and disable an encoder that was never enabled" drm/radeon: Add early unregister of firmware fb's drm/radeon: use aperture size not vram size for overlap tests drm/radeon/kms/evergreen: flush hdp cache when flushing gart tlb drm/radeon/kms: disable the r600 cb offset checker for linear surfaces drm/radeon/kms: disable ss fixed ref divide drm/i915/bios: Reverse order of 100/120 Mhz SSC clocks agp/intel: Fix missed cached memory flags setting in i965_write_entry() drm/i915/sdvo: Only use the SDVO pin if it is in the valid range drm/i915/ringbuffer: Handle wrapping of the autoreported HEAD drm/i915/dp: Fix I2C/EDID handling with active DisplayPort to DVI converter
-rw-r--r--drivers/char/agp/intel-gtt.c11
-rw-r--r--drivers/gpu/drm/drm_crtc_helper.c7
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c2
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c37
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c19
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h5
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c9
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c7
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c27
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h1
-rw-r--r--drivers/gpu/drm/radeon/r600.c10
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c19
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c2
15 files changed, 115 insertions, 59 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 16a2847b7cdb..29ac6d499fa6 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1192,12 +1192,19 @@ static void i9xx_chipset_flush(void)
1192 writel(1, intel_private.i9xx_flush_page); 1192 writel(1, intel_private.i9xx_flush_page);
1193} 1193}
1194 1194
1195static void i965_write_entry(dma_addr_t addr, unsigned int entry, 1195static void i965_write_entry(dma_addr_t addr,
1196 unsigned int entry,
1196 unsigned int flags) 1197 unsigned int flags)
1197{ 1198{
1199 u32 pte_flags;
1200
1201 pte_flags = I810_PTE_VALID;
1202 if (flags == AGP_USER_CACHED_MEMORY)
1203 pte_flags |= I830_PTE_SYSTEM_CACHED;
1204
1198 /* Shift high bits down */ 1205 /* Shift high bits down */
1199 addr |= (addr >> 28) & 0xf0; 1206 addr |= (addr >> 28) & 0xf0;
1200 writel(addr | I810_PTE_VALID, intel_private.gtt + entry); 1207 writel(addr | pte_flags, intel_private.gtt + entry);
1201} 1208}
1202 1209
1203static bool gen6_check_flags(unsigned int flags) 1210static bool gen6_check_flags(unsigned int flags)
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index bede10a03407..2d4e17a004db 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -241,7 +241,7 @@ void drm_helper_disable_unused_functions(struct drm_device *dev)
241 } 241 }
242 242
243 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 243 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
244 if (encoder->crtc && !drm_helper_encoder_in_use(encoder)) { 244 if (!drm_helper_encoder_in_use(encoder)) {
245 drm_encoder_disable(encoder); 245 drm_encoder_disable(encoder);
246 /* disconnector encoder from any connector */ 246 /* disconnector encoder from any connector */
247 encoder->crtc = NULL; 247 encoder->crtc = NULL;
@@ -874,7 +874,10 @@ static void output_poll_execute(struct work_struct *work)
874 continue; 874 continue;
875 875
876 connector->status = connector->funcs->detect(connector, false); 876 connector->status = connector->funcs->detect(connector, false);
877 DRM_DEBUG_KMS("connector status updated to %d\n", connector->status); 877 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
878 connector->base.id,
879 drm_get_connector_name(connector),
880 old_status, connector->status);
878 if (old_status != connector->status) 881 if (old_status != connector->status)
879 changed = true; 882 changed = true;
880 } 883 }
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index b0b1200ed650..2b2078695d2a 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -270,7 +270,7 @@ parse_general_features(struct drm_i915_private *dev_priv,
270 general->ssc_freq ? 66 : 48; 270 general->ssc_freq ? 66 : 48;
271 else if (IS_GEN5(dev) || IS_GEN6(dev)) 271 else if (IS_GEN5(dev) || IS_GEN6(dev))
272 dev_priv->lvds_ssc_freq = 272 dev_priv->lvds_ssc_freq =
273 general->ssc_freq ? 100 : 120; 273 general->ssc_freq ? 120 : 100;
274 else 274 else
275 dev_priv->lvds_ssc_freq = 275 dev_priv->lvds_ssc_freq =
276 general->ssc_freq ? 100 : 96; 276 general->ssc_freq ? 100 : 96;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index df648cb4c296..864417cffe9a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -479,6 +479,7 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
479 uint16_t address = algo_data->address; 479 uint16_t address = algo_data->address;
480 uint8_t msg[5]; 480 uint8_t msg[5];
481 uint8_t reply[2]; 481 uint8_t reply[2];
482 unsigned retry;
482 int msg_bytes; 483 int msg_bytes;
483 int reply_bytes; 484 int reply_bytes;
484 int ret; 485 int ret;
@@ -513,14 +514,33 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
513 break; 514 break;
514 } 515 }
515 516
516 for (;;) { 517 for (retry = 0; retry < 5; retry++) {
517 ret = intel_dp_aux_ch(intel_dp, 518 ret = intel_dp_aux_ch(intel_dp,
518 msg, msg_bytes, 519 msg, msg_bytes,
519 reply, reply_bytes); 520 reply, reply_bytes);
520 if (ret < 0) { 521 if (ret < 0) {
521 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 522 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
522 return ret; 523 return ret;
523 } 524 }
525
526 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
527 case AUX_NATIVE_REPLY_ACK:
528 /* I2C-over-AUX Reply field is only valid
529 * when paired with AUX ACK.
530 */
531 break;
532 case AUX_NATIVE_REPLY_NACK:
533 DRM_DEBUG_KMS("aux_ch native nack\n");
534 return -EREMOTEIO;
535 case AUX_NATIVE_REPLY_DEFER:
536 udelay(100);
537 continue;
538 default:
539 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
540 reply[0]);
541 return -EREMOTEIO;
542 }
543
524 switch (reply[0] & AUX_I2C_REPLY_MASK) { 544 switch (reply[0] & AUX_I2C_REPLY_MASK) {
525 case AUX_I2C_REPLY_ACK: 545 case AUX_I2C_REPLY_ACK:
526 if (mode == MODE_I2C_READ) { 546 if (mode == MODE_I2C_READ) {
@@ -528,17 +548,20 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
528 } 548 }
529 return reply_bytes - 1; 549 return reply_bytes - 1;
530 case AUX_I2C_REPLY_NACK: 550 case AUX_I2C_REPLY_NACK:
531 DRM_DEBUG_KMS("aux_ch nack\n"); 551 DRM_DEBUG_KMS("aux_i2c nack\n");
532 return -EREMOTEIO; 552 return -EREMOTEIO;
533 case AUX_I2C_REPLY_DEFER: 553 case AUX_I2C_REPLY_DEFER:
534 DRM_DEBUG_KMS("aux_ch defer\n"); 554 DRM_DEBUG_KMS("aux_i2c defer\n");
535 udelay(100); 555 udelay(100);
536 break; 556 break;
537 default: 557 default:
538 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]); 558 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
539 return -EREMOTEIO; 559 return -EREMOTEIO;
540 } 560 }
541 } 561 }
562
563 DRM_ERROR("too many retries, giving up\n");
564 return -EREMOTEIO;
542} 565}
543 566
544static int 567static int
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 89a65be8a3f3..31cd7e33e820 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -696,20 +696,17 @@ int intel_wait_ring_buffer(struct drm_device *dev,
696 drm_i915_private_t *dev_priv = dev->dev_private; 696 drm_i915_private_t *dev_priv = dev->dev_private;
697 u32 head; 697 u32 head;
698 698
699 head = intel_read_status_page(ring, 4);
700 if (head) {
701 ring->head = head & HEAD_ADDR;
702 ring->space = ring->head - (ring->tail + 8);
703 if (ring->space < 0)
704 ring->space += ring->size;
705 if (ring->space >= n)
706 return 0;
707 }
708
709 trace_i915_ring_wait_begin (dev); 699 trace_i915_ring_wait_begin (dev);
710 end = jiffies + 3 * HZ; 700 end = jiffies + 3 * HZ;
711 do { 701 do {
712 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; 702 /* If the reported head position has wrapped or hasn't advanced,
703 * fallback to the slow and accurate path.
704 */
705 head = intel_read_status_page(ring, 4);
706 if (head < ring->actual_head)
707 head = I915_READ_HEAD(ring);
708 ring->actual_head = head;
709 ring->head = head & HEAD_ADDR;
713 ring->space = ring->head - (ring->tail + 8); 710 ring->space = ring->head - (ring->tail + 8);
714 if (ring->space < 0) 711 if (ring->space < 0)
715 ring->space += ring->size; 712 ring->space += ring->size;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 3126c2681983..d2cd0f1efeed 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -30,8 +30,9 @@ struct intel_ring_buffer {
30 struct drm_device *dev; 30 struct drm_device *dev;
31 struct drm_gem_object *gem_object; 31 struct drm_gem_object *gem_object;
32 32
33 unsigned int head; 33 u32 actual_head;
34 unsigned int tail; 34 u32 head;
35 u32 tail;
35 int space; 36 int space;
36 struct intel_hw_status_page status_page; 37 struct intel_hw_status_page status_page;
37 38
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index d97e6cb52d34..27e63abf2a73 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1908,9 +1908,12 @@ intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1908 speed = mapping->i2c_speed; 1908 speed = mapping->i2c_speed;
1909 } 1909 }
1910 1910
1911 sdvo->i2c = &dev_priv->gmbus[pin].adapter; 1911 if (pin < GMBUS_NUM_PORTS) {
1912 intel_gmbus_set_speed(sdvo->i2c, speed); 1912 sdvo->i2c = &dev_priv->gmbus[pin].adapter;
1913 intel_gmbus_force_bit(sdvo->i2c, true); 1913 intel_gmbus_set_speed(sdvo->i2c, speed);
1914 intel_gmbus_force_bit(sdvo->i2c, true);
1915 } else
1916 sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
1914} 1917}
1915 1918
1916static bool 1919static bool
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index df2b6f2b35f8..9fbabaa6ee44 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -253,7 +253,8 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
253 case DRM_MODE_DPMS_SUSPEND: 253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF: 254 case DRM_MODE_DPMS_OFF:
255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
256 atombios_blank_crtc(crtc, ATOM_ENABLE); 256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
257 if (ASIC_IS_DCE3(rdev)) 258 if (ASIC_IS_DCE3(rdev))
258 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
259 atombios_enable_crtc(crtc, ATOM_DISABLE); 260 atombios_enable_crtc(crtc, ATOM_DISABLE);
@@ -530,7 +531,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
530 dp_clock = dig_connector->dp_clock; 531 dp_clock = dig_connector->dp_clock;
531 } 532 }
532 } 533 }
533 534#if 0 /* doesn't work properly on some laptops */
534 /* use recommended ref_div for ss */ 535 /* use recommended ref_div for ss */
535 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 536 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
536 if (ss_enabled) { 537 if (ss_enabled) {
@@ -540,7 +541,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
540 } 541 }
541 } 542 }
542 } 543 }
543 544#endif
544 if (ASIC_IS_AVIVO(rdev)) { 545 if (ASIC_IS_AVIVO(rdev)) {
545 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 546 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
546 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 547 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 4dc5b4714c5a..7b337c361a12 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -748,6 +748,8 @@ void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
748 unsigned i; 748 unsigned i;
749 u32 tmp; 749 u32 tmp;
750 750
751 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
752
751 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 753 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
752 for (i = 0; i < rdev->usec_timeout; i++) { 754 for (i = 0; i < rdev->usec_timeout; i++) {
753 /* read MC_STATUS */ 755 /* read MC_STATUS */
@@ -1922,7 +1924,6 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
1922static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 1924static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
1923{ 1925{
1924 struct evergreen_mc_save save; 1926 struct evergreen_mc_save save;
1925 u32 srbm_reset = 0;
1926 u32 grbm_reset = 0; 1927 u32 grbm_reset = 0;
1927 1928
1928 dev_info(rdev->dev, "GPU softreset \n"); 1929 dev_info(rdev->dev, "GPU softreset \n");
@@ -1961,16 +1962,6 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
1961 udelay(50); 1962 udelay(50);
1962 WREG32(GRBM_SOFT_RESET, 0); 1963 WREG32(GRBM_SOFT_RESET, 0);
1963 (void)RREG32(GRBM_SOFT_RESET); 1964 (void)RREG32(GRBM_SOFT_RESET);
1964
1965 /* reset all the system blocks */
1966 srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
1967
1968 dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
1969 WREG32(SRBM_SOFT_RESET, srbm_reset);
1970 (void)RREG32(SRBM_SOFT_RESET);
1971 udelay(50);
1972 WREG32(SRBM_SOFT_RESET, 0);
1973 (void)RREG32(SRBM_SOFT_RESET);
1974 /* Wait a little for things to settle down */ 1965 /* Wait a little for things to settle down */
1975 udelay(50); 1966 udelay(50);
1976 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 1967 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
@@ -1981,10 +1972,6 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
1981 RREG32(GRBM_STATUS_SE1)); 1972 RREG32(GRBM_STATUS_SE1));
1982 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 1973 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1983 RREG32(SRBM_STATUS)); 1974 RREG32(SRBM_STATUS));
1984 /* After reset we need to reinit the asic as GPU often endup in an
1985 * incoherent state.
1986 */
1987 atom_asic_init(rdev->mode_info.atom_context);
1988 evergreen_mc_resume(rdev, &save); 1975 evergreen_mc_resume(rdev, &save);
1989 return 0; 1976 return 0;
1990} 1977}
@@ -2596,6 +2583,11 @@ int evergreen_resume(struct radeon_device *rdev)
2596{ 2583{
2597 int r; 2584 int r;
2598 2585
2586 /* reset the asic, the gfx blocks are often in a bad state
2587 * after the driver is unloaded or after a resume
2588 */
2589 if (radeon_asic_reset(rdev))
2590 dev_warn(rdev->dev, "GPU reset failed !\n");
2599 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 2591 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2600 * posting will perform necessary task to bring back GPU into good 2592 * posting will perform necessary task to bring back GPU into good
2601 * shape. 2593 * shape.
@@ -2712,6 +2704,11 @@ int evergreen_init(struct radeon_device *rdev)
2712 r = radeon_atombios_init(rdev); 2704 r = radeon_atombios_init(rdev);
2713 if (r) 2705 if (r)
2714 return r; 2706 return r;
2707 /* reset the asic, the gfx blocks are often in a bad state
2708 * after the driver is unloaded or after a resume
2709 */
2710 if (radeon_asic_reset(rdev))
2711 dev_warn(rdev->dev, "GPU reset failed !\n");
2715 /* Post card if necessary */ 2712 /* Post card if necessary */
2716 if (!evergreen_card_posted(rdev)) { 2713 if (!evergreen_card_posted(rdev)) {
2717 if (!rdev->bios) { 2714 if (!rdev->bios) {
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 113c70cc8b39..a73b53c44359 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -174,6 +174,7 @@
174#define HDP_NONSURFACE_BASE 0x2C04 174#define HDP_NONSURFACE_BASE 0x2C04
175#define HDP_NONSURFACE_INFO 0x2C08 175#define HDP_NONSURFACE_INFO 0x2C08
176#define HDP_NONSURFACE_SIZE 0x2C0C 176#define HDP_NONSURFACE_SIZE 0x2C0C
177#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
177#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 178#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
178#define HDP_TILING_CONFIG 0x2F3C 179#define HDP_TILING_CONFIG 0x2F3C
179 180
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 4d7a2e1bdb90..9c92db7c896b 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1342,13 +1342,19 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev)
1342 u32 srbm_status; 1342 u32 srbm_status;
1343 u32 grbm_status; 1343 u32 grbm_status;
1344 u32 grbm_status2; 1344 u32 grbm_status2;
1345 struct r100_gpu_lockup *lockup;
1345 int r; 1346 int r;
1346 1347
1348 if (rdev->family >= CHIP_RV770)
1349 lockup = &rdev->config.rv770.lockup;
1350 else
1351 lockup = &rdev->config.r600.lockup;
1352
1347 srbm_status = RREG32(R_000E50_SRBM_STATUS); 1353 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1348 grbm_status = RREG32(R_008010_GRBM_STATUS); 1354 grbm_status = RREG32(R_008010_GRBM_STATUS);
1349 grbm_status2 = RREG32(R_008014_GRBM_STATUS2); 1355 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1350 if (!G_008010_GUI_ACTIVE(grbm_status)) { 1356 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1351 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); 1357 r100_gpu_lockup_update(lockup, &rdev->cp);
1352 return false; 1358 return false;
1353 } 1359 }
1354 /* force CP activities */ 1360 /* force CP activities */
@@ -1360,7 +1366,7 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev)
1360 radeon_ring_unlock_commit(rdev); 1366 radeon_ring_unlock_commit(rdev);
1361 } 1367 }
1362 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); 1368 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1363 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); 1369 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1364} 1370}
1365 1371
1366int r600_asic_reset(struct radeon_device *rdev) 1372int r600_asic_reset(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 0f90fc3482ce..7831e0890210 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -315,11 +315,10 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
315 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { 315 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
316 /* the initial DDX does bad things with the CB size occasionally */ 316 /* the initial DDX does bad things with the CB size occasionally */
317 /* it rounds up height too far for slice tile max but the BO is smaller */ 317 /* it rounds up height too far for slice tile max but the BO is smaller */
318 tmp = (height - 7) * 8 * bpe; 318 /* r600c,g also seem to flush at bad times in some apps resulting in
319 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { 319 * bogus values here. So for linear just allow anything to avoid breaking
320 dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i])); 320 * broken userspace.
321 return -EINVAL; 321 */
322 }
323 } else { 322 } else {
324 dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i])); 323 dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i]));
325 return -EINVAL; 324 return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index e12e79326cb1..501966a13f48 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -910,11 +910,6 @@ int radeon_resume_kms(struct drm_device *dev)
910 radeon_pm_resume(rdev); 910 radeon_pm_resume(rdev);
911 radeon_restore_bios_scratch_regs(rdev); 911 radeon_restore_bios_scratch_regs(rdev);
912 912
913 /* turn on display hw */
914 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
915 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
916 }
917
918 radeon_fbdev_set_suspend(rdev, 0); 913 radeon_fbdev_set_suspend(rdev, 0);
919 release_console_sem(); 914 release_console_sem();
920 915
@@ -922,6 +917,10 @@ int radeon_resume_kms(struct drm_device *dev)
922 radeon_hpd_init(rdev); 917 radeon_hpd_init(rdev);
923 /* blat the mode back in */ 918 /* blat the mode back in */
924 drm_helper_resume_force_mode(dev); 919 drm_helper_resume_force_mode(dev);
920 /* turn on display hw */
921 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
922 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
923 }
925 return 0; 924 return 0;
926} 925}
927 926
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 88e4ea925900..60e689f2d048 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -232,9 +232,28 @@ static struct drm_driver driver_old = {
232 232
233static struct drm_driver kms_driver; 233static struct drm_driver kms_driver;
234 234
235static void radeon_kick_out_firmware_fb(struct pci_dev *pdev)
236{
237 struct apertures_struct *ap;
238 bool primary = false;
239
240 ap = alloc_apertures(1);
241 ap->ranges[0].base = pci_resource_start(pdev, 0);
242 ap->ranges[0].size = pci_resource_len(pdev, 0);
243
244#ifdef CONFIG_X86
245 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
246#endif
247 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
248 kfree(ap);
249}
250
235static int __devinit 251static int __devinit
236radeon_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 252radeon_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
237{ 253{
254 /* Get rid of things like offb */
255 radeon_kick_out_firmware_fb(pdev);
256
238 return drm_get_pci_dev(pdev, ent, &kms_driver); 257 return drm_get_pci_dev(pdev, ent, &kms_driver);
239} 258}
240 259
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index efa211898fe6..6abea32be5e8 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -245,7 +245,7 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev,
245 goto out_unref; 245 goto out_unref;
246 } 246 }
247 info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base; 247 info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
248 info->apertures->ranges[0].size = rdev->mc.real_vram_size; 248 info->apertures->ranges[0].size = rdev->mc.aper_size;
249 249
250 info->fix.mmio_start = 0; 250 info->fix.mmio_start = 0;
251 info->fix.mmio_len = 0; 251 info->fix.mmio_len = 0;